pmc-rs provides a safe abstraction for interacting with Performance
Monitor Counters on
PMCs are part of the CPU hardware and are typically used to profile CPU micro-architecture events such as L1/L2/etc cache hit ratio, instructions processed per CPU tick, TLB lookups, branch mispredictions, etc for a particular application or algorithm. Using PMCs an algorithm can be tuned for performance by minimising CPU stalls, optimising CPU cache usage, etc.
The events are defined by the CPU manufacturer (here is the Intel 64 and
IA-32 Architectures Developer’s Manual: vol.
where the events can be found in section
18.104.22.168 "Pre-defined Architectural Performance Events",
Table 18-1 "UMask and Event Select Encodings for Pre-Defined Architectural Performance Events").
An allocated PMC counter.
Configure event counter parameters.
A handle to a running PMC counter.