Struct Tx 

pub struct Tx<SM, TxSize = Word>
where
    SM: ValidStateMachine,
{ /* private fields */ }

PIO TX FIFO handle.

Implementations

impl<SM, TxSize> Tx<SM, TxSize>

where SM: ValidStateMachine, TxSize: TransferSize,

pub fn fifo_address(&self) -> *const u32

Gets the FIFO’s address.

This is useful if you want to DMA to this peripheral.

NB: You are responsible for using the pointer correctly and not overflowing the buffer.

pub fn dreq_value(&self) -> u8

Gets the FIFO’s DREQ value.

This is a value between 0 and 39. Each FIFO on each state machine on each PIO has a unique value.

pub fn write(&mut self, value: u32) -> bool

Write a u32 value to TX FIFO.

Returns true if the value was written to FIFO, false otherwise.

pub fn write_u8_replicated(&mut self, value: u8) -> bool

Write a replicated u8 value to TX FIFO.

Memory mapped register writes that are smaller than 32bits will trigger “Narrow IO Register Write” behaviour in rp235x - the value written will be replicated to the rest of the register as described in RP2350 Datasheet: 2.1.5. - Narrow IO Register Writes

This 8bit write will set all 4 bytes of the FIFO to value Eg: if you write 0xBA the value written to the the FIFO will be 0xBABABABA

If you wish to write an 8bit number without replication, use write(my_u8 as u32) instead.

Returns true if the value was written to FIFO, false otherwise.

pub fn write_u16_replicated(&mut self, value: u16) -> bool

Write a replicated 16bit value to TX FIFO.

Memory mapped register writes that are smaller than 32bits will trigger “Narrow IO Register Write” behaviour in rp235x - the value written will be replicated to the rest of the register as described in RP2350 Datasheet: 2.1.5. - Narrow IO Register Writes

This 16bit write will set both the upper and lower half of the FIFO entry to value.

For example, if you write 0xC0DA the value written to the FIFO will be 0xC0DAC0DA

If you wish to write a 16bit number without replication, use write(my_u16 as u32) instead.

Returns true if the value was written to FIFO, false otherwise.

pub fn has_stalled(&self) -> bool

Checks if the state machine has stalled on empty TX FIFO during a blocking PULL, or an OUT with autopull enabled.

Note this is a sticky flag and may not reflect the current state of the machine.

pub fn clear_stalled_flag(&self)

Clears the tx_stalled flag.

pub fn is_empty(&self) -> bool

Indicate if the tx FIFO is empty

pub fn is_full(&self) -> bool

Indicate if the tx FIFO is full

pub fn enable_tx_not_full_interrupt(&self, id: PioIRQ)

Enable TX FIFO not full interrupt.

This interrupt is raised when the TX FIFO is not full, i.e. one could push more data to it.

pub fn disable_tx_not_full_interrupt(&self, id: PioIRQ)

Disable TX FIFO not full interrupt.

pub fn force_tx_not_full_interrupt(&self, id: PioIRQ)

Force TX FIFO not full interrupt.

pub fn transfer_size<RSZ>(self, size: RSZ) -> Tx<SM, RSZ>

where RSZ: TransferSize,

Set the transfer size used in DMA transfers.

Trait Implementations

impl<SM, TxSize> WriteTarget for Tx<SM, TxSize>

where SM: ValidStateMachine, TxSize: TransferSize,

type TransmittedWord = <TxSize as TransferSize>::Type

Type which is transferred in a single DMA transfer.

fn tx_treq() -> Option<u8>

Returns the DREQ number for this data sink (None for memory buffers).

fn tx_address_count(&mut self) -> (u32, u32)

Returns the address and the maximum number of words that can be transferred from this data source in a single DMA operation.

fn tx_increment(&self) -> bool

Returns whether the address shall be incremented after each transfer.

impl<SM, TxSize> EndlessWriteTarget for Tx<SM, TxSize>

where SM: ValidStateMachine, TxSize: TransferSize,

impl<SM, TxSize> Send for Tx<SM, TxSize>

where SM: ValidStateMachine + Send,