Struct Rx 

pub struct Rx<SM, RxSize = Word>
where
    SM: ValidStateMachine,
{ /* private fields */ }

PIO RX FIFO handle.

Implementations

impl<SM, RxSize> Rx<SM, RxSize>

where SM: ValidStateMachine, RxSize: TransferSize,

pub fn fifo_address(&self) -> *const u32

Gets the FIFO’s address.

This is useful if you want to DMA from this peripheral.

NB: You are responsible for using the pointer correctly and not underflowing the buffer.

pub fn dreq_value(&self) -> u8

Gets the FIFO’s DREQ value.

This is a value between 0 and 39. Each FIFO on each state machine on each PIO has a unique value.

pub fn read(&mut self) -> Option<u32>

Get the next element from RX FIFO.

Returns None if the FIFO is empty.

pub fn enable_autopush(&mut self, enable: bool)

Enable/Disable the autopush feature of the state machine.

pub fn is_empty(&self) -> bool

Indicate if the rx FIFO is empty

pub fn is_full(&self) -> bool

Indicate if the rx FIFO is full

pub fn enable_rx_not_empty_interrupt(&self, id: PioIRQ)

Enable RX FIFO not empty interrupt.

This interrupt is raised when the RX FIFO is not empty, i.e. one could read more data from it.

pub fn disable_rx_not_empty_interrupt(&self, id: PioIRQ)

Disable RX FIFO not empty interrupt.

pub fn force_rx_not_empty_interrupt(&self, id: PioIRQ, state: bool)

Force RX FIFO not empty interrupt.

pub fn transfer_size<RSZ>(self, size: RSZ) -> Rx<SM, RSZ>

where RSZ: TransferSize,

Set the transfer size used in DMA transfers.

Trait Implementations

impl<SM, RxSize> ReadTarget for Rx<SM, RxSize>

where SM: ValidStateMachine, RxSize: TransferSize,

type ReceivedWord = <RxSize as TransferSize>::Type

Type which is transferred in a single DMA transfer.

fn rx_treq() -> Option<u8>

Returns the DREQ number for this data source (None for memory buffers).

fn rx_address_count(&self) -> (u32, u32)

Returns the address and the maximum number of words that can be transferred from this data source in a single DMA operation.

fn rx_increment(&self) -> bool

Returns whether the address shall be incremented after each transfer.

impl<SM, RxSize> EndlessReadTarget for Rx<SM, RxSize>

where SM: ValidStateMachine, RxSize: TransferSize,

impl<SM, RxSize> Send for Rx<SM, RxSize>

where SM: ValidStateMachine + Send,