Struct PPB_NS 

pub struct PPB_NS { /* private fields */ }

TEAL registers accessible through the debug interface

Implementations

impl PPB_NS

pub const PTR: *const RegisterBlock = {0xe0020000 as *const rp235x_hal::rp235x_pac::ppb::RegisterBlock}

Pointer to the register block

pub const fn ptr() -> *const RegisterBlock

Return the pointer to the register block

pub unsafe fn steal() -> PPB_NS

Steal an instance of this peripheral

Safety

Ensure that the new instance of the peripheral cannot be used in a way that may race with any existing instances, for example by only accessing read-only or write-only registers, or by consuming the original peripheral and using critical sections to coordinate access between multiple new instances.

Additionally, other software such as HALs may rely on only one peripheral instance existing to ensure memory safety; ensure no stolen instances are passed to such software.

Methods from Deref<Target = RegisterBlock>

pub fn itm_stim0(&self) -> &Reg<ITM_STIM0_SPEC>

0x00 - Provides the interface for generating Instrumentation packets

pub fn itm_stim1(&self) -> &Reg<ITM_STIM1_SPEC>

0x04 - Provides the interface for generating Instrumentation packets

pub fn itm_stim2(&self) -> &Reg<ITM_STIM2_SPEC>

0x08 - Provides the interface for generating Instrumentation packets

pub fn itm_stim3(&self) -> &Reg<ITM_STIM3_SPEC>

0x0c - Provides the interface for generating Instrumentation packets

pub fn itm_stim4(&self) -> &Reg<ITM_STIM4_SPEC>

0x10 - Provides the interface for generating Instrumentation packets

pub fn itm_stim5(&self) -> &Reg<ITM_STIM5_SPEC>

0x14 - Provides the interface for generating Instrumentation packets

pub fn itm_stim6(&self) -> &Reg<ITM_STIM6_SPEC>

0x18 - Provides the interface for generating Instrumentation packets

pub fn itm_stim7(&self) -> &Reg<ITM_STIM7_SPEC>

0x1c - Provides the interface for generating Instrumentation packets

pub fn itm_stim8(&self) -> &Reg<ITM_STIM8_SPEC>

0x20 - Provides the interface for generating Instrumentation packets

pub fn itm_stim9(&self) -> &Reg<ITM_STIM9_SPEC>

0x24 - Provides the interface for generating Instrumentation packets

pub fn itm_stim10(&self) -> &Reg<ITM_STIM10_SPEC>

0x28 - Provides the interface for generating Instrumentation packets

pub fn itm_stim11(&self) -> &Reg<ITM_STIM11_SPEC>

0x2c - Provides the interface for generating Instrumentation packets

pub fn itm_stim12(&self) -> &Reg<ITM_STIM12_SPEC>

0x30 - Provides the interface for generating Instrumentation packets

pub fn itm_stim13(&self) -> &Reg<ITM_STIM13_SPEC>

0x34 - Provides the interface for generating Instrumentation packets

pub fn itm_stim14(&self) -> &Reg<ITM_STIM14_SPEC>

0x38 - Provides the interface for generating Instrumentation packets

pub fn itm_stim15(&self) -> &Reg<ITM_STIM15_SPEC>

0x3c - Provides the interface for generating Instrumentation packets

pub fn itm_stim16(&self) -> &Reg<ITM_STIM16_SPEC>

0x40 - Provides the interface for generating Instrumentation packets

pub fn itm_stim17(&self) -> &Reg<ITM_STIM17_SPEC>

0x44 - Provides the interface for generating Instrumentation packets

pub fn itm_stim18(&self) -> &Reg<ITM_STIM18_SPEC>

0x48 - Provides the interface for generating Instrumentation packets

pub fn itm_stim19(&self) -> &Reg<ITM_STIM19_SPEC>

0x4c - Provides the interface for generating Instrumentation packets

pub fn itm_stim20(&self) -> &Reg<ITM_STIM20_SPEC>

0x50 - Provides the interface for generating Instrumentation packets

pub fn itm_stim21(&self) -> &Reg<ITM_STIM21_SPEC>

0x54 - Provides the interface for generating Instrumentation packets

pub fn itm_stim22(&self) -> &Reg<ITM_STIM22_SPEC>

0x58 - Provides the interface for generating Instrumentation packets

pub fn itm_stim23(&self) -> &Reg<ITM_STIM23_SPEC>

0x5c - Provides the interface for generating Instrumentation packets

pub fn itm_stim24(&self) -> &Reg<ITM_STIM24_SPEC>

0x60 - Provides the interface for generating Instrumentation packets

pub fn itm_stim25(&self) -> &Reg<ITM_STIM25_SPEC>

0x64 - Provides the interface for generating Instrumentation packets

pub fn itm_stim26(&self) -> &Reg<ITM_STIM26_SPEC>

0x68 - Provides the interface for generating Instrumentation packets

pub fn itm_stim27(&self) -> &Reg<ITM_STIM27_SPEC>

0x6c - Provides the interface for generating Instrumentation packets

pub fn itm_stim28(&self) -> &Reg<ITM_STIM28_SPEC>

0x70 - Provides the interface for generating Instrumentation packets

pub fn itm_stim29(&self) -> &Reg<ITM_STIM29_SPEC>

0x74 - Provides the interface for generating Instrumentation packets

pub fn itm_stim30(&self) -> &Reg<ITM_STIM30_SPEC>

0x78 - Provides the interface for generating Instrumentation packets

pub fn itm_stim31(&self) -> &Reg<ITM_STIM31_SPEC>

0x7c - Provides the interface for generating Instrumentation packets

pub fn itm_ter0(&self) -> &Reg<ITM_TER0_SPEC>

0xe00 - Provide an individual enable bit for each ITM_STIM register

pub fn itm_tpr(&self) -> &Reg<ITM_TPR_SPEC>

0xe40 - Controls which stimulus ports can be accessed by unprivileged code

pub fn itm_tcr(&self) -> &Reg<ITM_TCR_SPEC>

0xe80 - Configures and controls transfers through the ITM interface

pub fn int_atready(&self) -> &Reg<INT_ATREADY_SPEC>

0xef0 - Integration Mode: Read ATB Ready

pub fn int_atvalid(&self) -> &Reg<INT_ATVALID_SPEC>

0xef8 - Integration Mode: Write ATB Valid

pub fn itm_itctrl(&self) -> &Reg<ITM_ITCTRL_SPEC>

0xf00 - Integration Mode Control Register

pub fn itm_devarch(&self) -> &Reg<ITM_DEVARCH_SPEC>

0xfbc - Provides CoreSight discovery information for the ITM

pub fn itm_devtype(&self) -> &Reg<ITM_DEVTYPE_SPEC>

0xfcc - Provides CoreSight discovery information for the ITM

pub fn itm_pidr4(&self) -> &Reg<ITM_PIDR4_SPEC>

0xfd0 - Provides CoreSight discovery information for the ITM

pub fn itm_pidr5(&self) -> &Reg<ITM_PIDR5_SPEC>

0xfd4 - Provides CoreSight discovery information for the ITM

pub fn itm_pidr6(&self) -> &Reg<ITM_PIDR6_SPEC>

0xfd8 - Provides CoreSight discovery information for the ITM

pub fn itm_pidr7(&self) -> &Reg<ITM_PIDR7_SPEC>

0xfdc - Provides CoreSight discovery information for the ITM

pub fn itm_pidr0(&self) -> &Reg<ITM_PIDR0_SPEC>

0xfe0 - Provides CoreSight discovery information for the ITM

pub fn itm_pidr1(&self) -> &Reg<ITM_PIDR1_SPEC>

0xfe4 - Provides CoreSight discovery information for the ITM

pub fn itm_pidr2(&self) -> &Reg<ITM_PIDR2_SPEC>

0xfe8 - Provides CoreSight discovery information for the ITM

pub fn itm_pidr3(&self) -> &Reg<ITM_PIDR3_SPEC>

0xfec - Provides CoreSight discovery information for the ITM

pub fn itm_cidr0(&self) -> &Reg<ITM_CIDR0_SPEC>

0xff0 - Provides CoreSight discovery information for the ITM

pub fn itm_cidr1(&self) -> &Reg<ITM_CIDR1_SPEC>

0xff4 - Provides CoreSight discovery information for the ITM

pub fn itm_cidr2(&self) -> &Reg<ITM_CIDR2_SPEC>

0xff8 - Provides CoreSight discovery information for the ITM

pub fn itm_cidr3(&self) -> &Reg<ITM_CIDR3_SPEC>

0xffc - Provides CoreSight discovery information for the ITM

pub fn dwt_ctrl(&self) -> &Reg<DWT_CTRL_SPEC>

0x1000 - Provides configuration and status information for the DWT unit, and used to control features of the unit

pub fn dwt_cyccnt(&self) -> &Reg<DWT_CYCCNT_SPEC>

0x1004 - Shows or sets the value of the processor cycle counter, CYCCNT

pub fn dwt_exccnt(&self) -> &Reg<DWT_EXCCNT_SPEC>

0x100c - Counts the total cycles spent in exception processing

pub fn dwt_lsucnt(&self) -> &Reg<DWT_LSUCNT_SPEC>

0x1014 - Increments on the additional cycles required to execute all load or store instructions

pub fn dwt_foldcnt(&self) -> &Reg<DWT_FOLDCNT_SPEC>

0x1018 - Increments on the additional cycles required to execute all load or store instructions

pub fn dwt_comp0(&self) -> &Reg<DWT_COMP0_SPEC>

0x1020 - Provides a reference value for use by watchpoint comparator 0

pub fn dwt_function0(&self) -> &Reg<DWT_FUNCTION0_SPEC>

0x1028 - Controls the operation of watchpoint comparator 0

pub fn dwt_comp1(&self) -> &Reg<DWT_COMP1_SPEC>

0x1030 - Provides a reference value for use by watchpoint comparator 1

pub fn dwt_function1(&self) -> &Reg<DWT_FUNCTION1_SPEC>

0x1038 - Controls the operation of watchpoint comparator 1

pub fn dwt_comp2(&self) -> &Reg<DWT_COMP2_SPEC>

0x1040 - Provides a reference value for use by watchpoint comparator 2

pub fn dwt_function2(&self) -> &Reg<DWT_FUNCTION2_SPEC>

0x1048 - Controls the operation of watchpoint comparator 2

pub fn dwt_comp3(&self) -> &Reg<DWT_COMP3_SPEC>

0x1050 - Provides a reference value for use by watchpoint comparator 3

pub fn dwt_function3(&self) -> &Reg<DWT_FUNCTION3_SPEC>

0x1058 - Controls the operation of watchpoint comparator 3

pub fn dwt_devarch(&self) -> &Reg<DWT_DEVARCH_SPEC>

0x1fbc - Provides CoreSight discovery information for the DWT

pub fn dwt_devtype(&self) -> &Reg<DWT_DEVTYPE_SPEC>

0x1fcc - Provides CoreSight discovery information for the DWT

pub fn dwt_pidr4(&self) -> &Reg<DWT_PIDR4_SPEC>

0x1fd0 - Provides CoreSight discovery information for the DWT

pub fn dwt_pidr5(&self) -> &Reg<DWT_PIDR5_SPEC>

0x1fd4 - Provides CoreSight discovery information for the DWT

pub fn dwt_pidr6(&self) -> &Reg<DWT_PIDR6_SPEC>

0x1fd8 - Provides CoreSight discovery information for the DWT

pub fn dwt_pidr7(&self) -> &Reg<DWT_PIDR7_SPEC>

0x1fdc - Provides CoreSight discovery information for the DWT

pub fn dwt_pidr0(&self) -> &Reg<DWT_PIDR0_SPEC>

0x1fe0 - Provides CoreSight discovery information for the DWT

pub fn dwt_pidr1(&self) -> &Reg<DWT_PIDR1_SPEC>

0x1fe4 - Provides CoreSight discovery information for the DWT

pub fn dwt_pidr2(&self) -> &Reg<DWT_PIDR2_SPEC>

0x1fe8 - Provides CoreSight discovery information for the DWT

pub fn dwt_pidr3(&self) -> &Reg<DWT_PIDR3_SPEC>

0x1fec - Provides CoreSight discovery information for the DWT

pub fn dwt_cidr0(&self) -> &Reg<DWT_CIDR0_SPEC>

0x1ff0 - Provides CoreSight discovery information for the DWT

pub fn dwt_cidr1(&self) -> &Reg<DWT_CIDR1_SPEC>

0x1ff4 - Provides CoreSight discovery information for the DWT

pub fn dwt_cidr2(&self) -> &Reg<DWT_CIDR2_SPEC>

0x1ff8 - Provides CoreSight discovery information for the DWT

pub fn dwt_cidr3(&self) -> &Reg<DWT_CIDR3_SPEC>

0x1ffc - Provides CoreSight discovery information for the DWT

pub fn fp_ctrl(&self) -> &Reg<FP_CTRL_SPEC>

0x2000 - Provides FPB implementation information, and the global enable for the FPB unit

pub fn fp_remap(&self) -> &Reg<FP_REMAP_SPEC>

0x2004 - Indicates whether the implementation supports Flash Patch remap and, if it does, holds the target address for remap

pub fn fp_comp0(&self) -> &Reg<FP_COMP0_SPEC>

0x2008 - Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator

pub fn fp_comp1(&self) -> &Reg<FP_COMP1_SPEC>

0x200c - Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator

pub fn fp_comp2(&self) -> &Reg<FP_COMP2_SPEC>

0x2010 - Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator

pub fn fp_comp3(&self) -> &Reg<FP_COMP3_SPEC>

0x2014 - Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator

pub fn fp_comp4(&self) -> &Reg<FP_COMP4_SPEC>

0x2018 - Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator

pub fn fp_comp5(&self) -> &Reg<FP_COMP5_SPEC>

0x201c - Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator

pub fn fp_comp6(&self) -> &Reg<FP_COMP6_SPEC>

0x2020 - Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator

pub fn fp_comp7(&self) -> &Reg<FP_COMP7_SPEC>

0x2024 - Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator

pub fn fp_devarch(&self) -> &Reg<FP_DEVARCH_SPEC>

0x2fbc - Provides CoreSight discovery information for the FPB

pub fn fp_devtype(&self) -> &Reg<FP_DEVTYPE_SPEC>

0x2fcc - Provides CoreSight discovery information for the FPB

pub fn fp_pidr4(&self) -> &Reg<FP_PIDR4_SPEC>

0x2fd0 - Provides CoreSight discovery information for the FP

pub fn fp_pidr5(&self) -> &Reg<FP_PIDR5_SPEC>

0x2fd4 - Provides CoreSight discovery information for the FP

pub fn fp_pidr6(&self) -> &Reg<FP_PIDR6_SPEC>

0x2fd8 - Provides CoreSight discovery information for the FP

pub fn fp_pidr7(&self) -> &Reg<FP_PIDR7_SPEC>

0x2fdc - Provides CoreSight discovery information for the FP

pub fn fp_pidr0(&self) -> &Reg<FP_PIDR0_SPEC>

0x2fe0 - Provides CoreSight discovery information for the FP

pub fn fp_pidr1(&self) -> &Reg<FP_PIDR1_SPEC>

0x2fe4 - Provides CoreSight discovery information for the FP

pub fn fp_pidr2(&self) -> &Reg<FP_PIDR2_SPEC>

0x2fe8 - Provides CoreSight discovery information for the FP

pub fn fp_pidr3(&self) -> &Reg<FP_PIDR3_SPEC>

0x2fec - Provides CoreSight discovery information for the FP

pub fn fp_cidr0(&self) -> &Reg<FP_CIDR0_SPEC>

0x2ff0 - Provides CoreSight discovery information for the FP

pub fn fp_cidr1(&self) -> &Reg<FP_CIDR1_SPEC>

0x2ff4 - Provides CoreSight discovery information for the FP

pub fn fp_cidr2(&self) -> &Reg<FP_CIDR2_SPEC>

0x2ff8 - Provides CoreSight discovery information for the FP

pub fn fp_cidr3(&self) -> &Reg<FP_CIDR3_SPEC>

0x2ffc - Provides CoreSight discovery information for the FP

pub fn ictr(&self) -> &Reg<ICTR_SPEC>

0xe004 - Provides information about the interrupt controller

pub fn actlr(&self) -> &Reg<ACTLR_SPEC>

0xe008 - Provides IMPLEMENTATION DEFINED configuration and control options

pub fn syst_csr(&self) -> &Reg<SYST_CSR_SPEC>

0xe010 - Use the SysTick Control and Status Register to enable the SysTick features.

pub fn syst_rvr(&self) -> &Reg<SYST_RVR_SPEC>

0xe014 - Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 0 and 0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0. The reset value of this register is UNKNOWN. To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example, if the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99.

pub fn syst_cvr(&self) -> &Reg<SYST_CVR_SPEC>

0xe018 - Use the SysTick Current Value Register to find the current value in the register. The reset value of this register is UNKNOWN.

pub fn syst_calib(&self) -> &Reg<SYST_CALIB_SPEC>

0xe01c - Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply.

pub fn nvic_iser0(&self) -> &Reg<NVIC_ISER0_SPEC>

0xe100 - Enables or reads the enabled state of each group of 32 interrupts

pub fn nvic_iser1(&self) -> &Reg<NVIC_ISER1_SPEC>

0xe104 - Enables or reads the enabled state of each group of 32 interrupts

pub fn nvic_icer0(&self) -> &Reg<NVIC_ICER0_SPEC>

0xe180 - Clears or reads the enabled state of each group of 32 interrupts

pub fn nvic_icer1(&self) -> &Reg<NVIC_ICER1_SPEC>

0xe184 - Clears or reads the enabled state of each group of 32 interrupts

pub fn nvic_ispr0(&self) -> &Reg<NVIC_ISPR0_SPEC>

0xe200 - Enables or reads the pending state of each group of 32 interrupts

pub fn nvic_ispr1(&self) -> &Reg<NVIC_ISPR1_SPEC>

0xe204 - Enables or reads the pending state of each group of 32 interrupts

pub fn nvic_icpr0(&self) -> &Reg<NVIC_ICPR0_SPEC>

0xe280 - Clears or reads the pending state of each group of 32 interrupts

pub fn nvic_icpr1(&self) -> &Reg<NVIC_ICPR1_SPEC>

0xe284 - Clears or reads the pending state of each group of 32 interrupts

pub fn nvic_iabr0(&self) -> &Reg<NVIC_IABR0_SPEC>

0xe300 - For each group of 32 interrupts, shows the active state of each interrupt

pub fn nvic_iabr1(&self) -> &Reg<NVIC_IABR1_SPEC>

0xe304 - For each group of 32 interrupts, shows the active state of each interrupt

pub fn nvic_itns0(&self) -> &Reg<NVIC_ITNS0_SPEC>

0xe380 - For each group of 32 interrupts, determines whether each interrupt targets Non-secure or Secure state

pub fn nvic_itns1(&self) -> &Reg<NVIC_ITNS1_SPEC>

0xe384 - For each group of 32 interrupts, determines whether each interrupt targets Non-secure or Secure state

pub fn nvic_ipr0(&self) -> &Reg<NVIC_IPR0_SPEC>

0xe400 - Sets or reads interrupt priorities

pub fn nvic_ipr1(&self) -> &Reg<NVIC_IPR1_SPEC>

0xe404 - Sets or reads interrupt priorities

pub fn nvic_ipr2(&self) -> &Reg<NVIC_IPR2_SPEC>

0xe408 - Sets or reads interrupt priorities

pub fn nvic_ipr3(&self) -> &Reg<NVIC_IPR3_SPEC>

0xe40c - Sets or reads interrupt priorities

pub fn nvic_ipr4(&self) -> &Reg<NVIC_IPR4_SPEC>

0xe410 - Sets or reads interrupt priorities

pub fn nvic_ipr5(&self) -> &Reg<NVIC_IPR5_SPEC>

0xe414 - Sets or reads interrupt priorities

pub fn nvic_ipr6(&self) -> &Reg<NVIC_IPR6_SPEC>

0xe418 - Sets or reads interrupt priorities

pub fn nvic_ipr7(&self) -> &Reg<NVIC_IPR7_SPEC>

0xe41c - Sets or reads interrupt priorities

pub fn nvic_ipr8(&self) -> &Reg<NVIC_IPR8_SPEC>

0xe420 - Sets or reads interrupt priorities

pub fn nvic_ipr9(&self) -> &Reg<NVIC_IPR9_SPEC>

0xe424 - Sets or reads interrupt priorities

pub fn nvic_ipr10(&self) -> &Reg<NVIC_IPR10_SPEC>

0xe428 - Sets or reads interrupt priorities

pub fn nvic_ipr11(&self) -> &Reg<NVIC_IPR11_SPEC>

0xe42c - Sets or reads interrupt priorities

pub fn nvic_ipr12(&self) -> &Reg<NVIC_IPR12_SPEC>

0xe430 - Sets or reads interrupt priorities

pub fn nvic_ipr13(&self) -> &Reg<NVIC_IPR13_SPEC>

0xe434 - Sets or reads interrupt priorities

pub fn nvic_ipr14(&self) -> &Reg<NVIC_IPR14_SPEC>

0xe438 - Sets or reads interrupt priorities

pub fn nvic_ipr15(&self) -> &Reg<NVIC_IPR15_SPEC>

0xe43c - Sets or reads interrupt priorities

pub fn cpuid(&self) -> &Reg<CPUID_SPEC>

0xed00 - Provides identification information for the PE, including an implementer code for the device and a device ID number

pub fn icsr(&self) -> &Reg<ICSR_SPEC>

0xed04 - Controls and provides status information for NMI, PendSV, SysTick and interrupts

pub fn vtor(&self) -> &Reg<VTOR_SPEC>

0xed08 - The VTOR indicates the offset of the vector table base address from memory address 0x00000000.

pub fn aircr(&self) -> &Reg<AIRCR_SPEC>

0xed0c - Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state information from debug halt mode, request a system reset.

pub fn scr(&self) -> &Reg<SCR_SPEC>

0xed10 - System Control Register. Use the System Control Register for power-management functions: signal to the system when the processor can enter a low power state, control how the processor enters and exits low power states.

pub fn ccr(&self) -> &Reg<CCR_SPEC>

0xed14 - Sets or returns configuration and control data

pub fn shpr1(&self) -> &Reg<SHPR1_SPEC>

0xed18 - Sets or returns priority for system handlers 4 - 7

pub fn shpr2(&self) -> &Reg<SHPR2_SPEC>

0xed1c - Sets or returns priority for system handlers 8 - 11

pub fn shpr3(&self) -> &Reg<SHPR3_SPEC>

0xed20 - Sets or returns priority for system handlers 12 - 15

pub fn shcsr(&self) -> &Reg<SHCSR_SPEC>

0xed24 - Provides access to the active and pending status of system exceptions

pub fn cfsr(&self) -> &Reg<CFSR_SPEC>

0xed28 - Contains the three Configurable Fault Status Registers. 31:16 UFSR: Provides information on UsageFault exceptions 15:8 BFSR: Provides information on BusFault exceptions 7:0 MMFSR: Provides information on MemManage exceptions

pub fn hfsr(&self) -> &Reg<HFSR_SPEC>

0xed2c - Shows the cause of any HardFaults

pub fn dfsr(&self) -> &Reg<DFSR_SPEC>

0xed30 - Shows which debug event occurred

pub fn mmfar(&self) -> &Reg<MMFAR_SPEC>

0xed34 - Shows the address of the memory location that caused an MPU fault

pub fn bfar(&self) -> &Reg<BFAR_SPEC>

0xed38 - Shows the address associated with a precise data access BusFault

pub fn id_pfr0(&self) -> &Reg<ID_PFR0_SPEC>

0xed40 - Gives top-level information about the instruction set supported by the PE

pub fn id_pfr1(&self) -> &Reg<ID_PFR1_SPEC>

0xed44 - Gives information about the programmers’ model and Extensions support

pub fn id_dfr0(&self) -> &Reg<ID_DFR0_SPEC>

0xed48 - Provides top level information about the debug system

pub fn id_afr0(&self) -> &Reg<ID_AFR0_SPEC>

0xed4c - Provides information about the IMPLEMENTATION DEFINED features of the PE

pub fn id_mmfr0(&self) -> &Reg<ID_MMFR0_SPEC>

0xed50 - Provides information about the implemented memory model and memory management support

pub fn id_mmfr1(&self) -> &Reg<ID_MMFR1_SPEC>

0xed54 - Provides information about the implemented memory model and memory management support

pub fn id_mmfr2(&self) -> &Reg<ID_MMFR2_SPEC>

0xed58 - Provides information about the implemented memory model and memory management support

pub fn id_mmfr3(&self) -> &Reg<ID_MMFR3_SPEC>

0xed5c - Provides information about the implemented memory model and memory management support

pub fn id_isar0(&self) -> &Reg<ID_ISAR0_SPEC>

0xed60 - Provides information about the instruction set implemented by the PE

pub fn id_isar1(&self) -> &Reg<ID_ISAR1_SPEC>

0xed64 - Provides information about the instruction set implemented by the PE

pub fn id_isar2(&self) -> &Reg<ID_ISAR2_SPEC>

0xed68 - Provides information about the instruction set implemented by the PE

pub fn id_isar3(&self) -> &Reg<ID_ISAR3_SPEC>

0xed6c - Provides information about the instruction set implemented by the PE

pub fn id_isar4(&self) -> &Reg<ID_ISAR4_SPEC>

0xed70 - Provides information about the instruction set implemented by the PE

pub fn id_isar5(&self) -> &Reg<ID_ISAR5_SPEC>

0xed74 - Provides information about the instruction set implemented by the PE

pub fn ctr(&self) -> &Reg<CTR_SPEC>

0xed7c - Provides information about the architecture of the caches. CTR is RES0 if CLIDR is zero.

pub fn cpacr(&self) -> &Reg<CPACR_SPEC>

0xed88 - Specifies the access privileges for coprocessors and the FP Extension

pub fn nsacr(&self) -> &Reg<NSACR_SPEC>

0xed8c - Defines the Non-secure access permissions for both the FP Extension and coprocessors CP0 to CP7

pub fn mpu_type(&self) -> &Reg<MPU_TYPE_SPEC>

0xed90 - The MPU Type Register indicates how many regions the MPU `FTSSS supports

pub fn mpu_ctrl(&self) -> &Reg<MPU_CTRL_SPEC>

0xed94 - Enables the MPU and, when the MPU is enabled, controls whether the default memory map is enabled as a background region for privileged accesses, and whether the MPU is enabled for HardFaults, NMIs, and exception handlers when FAULTMASK is set to 1

pub fn mpu_rnr(&self) -> &Reg<MPU_RNR_SPEC>

0xed98 - Selects the region currently accessed by MPU_RBAR and MPU_RLAR

pub fn mpu_rbar(&self) -> &Reg<MPU_RBAR_SPEC>

0xed9c - Provides indirect read and write access to the base address of the currently selected MPU region `FTSSS

pub fn mpu_rlar(&self) -> &Reg<MPU_RLAR_SPEC>

0xeda0 - Provides indirect read and write access to the limit address of the currently selected MPU region `FTSSS

pub fn mpu_rbar_a1(&self) -> &Reg<MPU_RBAR_A1_SPEC>

0xeda4 - Provides indirect read and write access to the base address of the MPU region selected by MPU_RNR[7:2]:(1[1:0]) `FTSSS

pub fn mpu_rlar_a1(&self) -> &Reg<MPU_RLAR_A1_SPEC>

0xeda8 - Provides indirect read and write access to the limit address of the currently selected MPU region selected by MPU_RNR[7:2]:(1[1:0]) `FTSSS

pub fn mpu_rbar_a2(&self) -> &Reg<MPU_RBAR_A2_SPEC>

0xedac - Provides indirect read and write access to the base address of the MPU region selected by MPU_RNR[7:2]:(2[1:0]) `FTSSS

pub fn mpu_rlar_a2(&self) -> &Reg<MPU_RLAR_A2_SPEC>

0xedb0 - Provides indirect read and write access to the limit address of the currently selected MPU region selected by MPU_RNR[7:2]:(2[1:0]) `FTSSS

pub fn mpu_rbar_a3(&self) -> &Reg<MPU_RBAR_A3_SPEC>

0xedb4 - Provides indirect read and write access to the base address of the MPU region selected by MPU_RNR[7:2]:(3[1:0]) `FTSSS

pub fn mpu_rlar_a3(&self) -> &Reg<MPU_RLAR_A3_SPEC>

0xedb8 - Provides indirect read and write access to the limit address of the currently selected MPU region selected by MPU_RNR[7:2]:(3[1:0]) `FTSSS

pub fn mpu_mair0(&self) -> &Reg<MPU_MAIR0_SPEC>

0xedc0 - Along with MPU_MAIR1, provides the memory attribute encodings corresponding to the AttrIndex values

pub fn mpu_mair1(&self) -> &Reg<MPU_MAIR1_SPEC>

0xedc4 - Along with MPU_MAIR0, provides the memory attribute encodings corresponding to the AttrIndex values

pub fn sau_ctrl(&self) -> &Reg<SAU_CTRL_SPEC>

0xedd0 - Allows enabling of the Security Attribution Unit

pub fn sau_type(&self) -> &Reg<SAU_TYPE_SPEC>

0xedd4 - Indicates the number of regions implemented by the Security Attribution Unit

pub fn sau_rnr(&self) -> &Reg<SAU_RNR_SPEC>

0xedd8 - Selects the region currently accessed by SAU_RBAR and SAU_RLAR

pub fn sau_rbar(&self) -> &Reg<SAU_RBAR_SPEC>

0xeddc - Provides indirect read and write access to the base address of the currently selected SAU region

pub fn sau_rlar(&self) -> &Reg<SAU_RLAR_SPEC>

0xede0 - Provides indirect read and write access to the limit address of the currently selected SAU region

pub fn sfsr(&self) -> &Reg<SFSR_SPEC>

0xede4 - Provides information about any security related faults

pub fn sfar(&self) -> &Reg<SFAR_SPEC>

0xede8 - Shows the address of the memory location that caused a Security violation

pub fn dhcsr(&self) -> &Reg<DHCSR_SPEC>

0xedf0 - Controls halting debug

pub fn dcrsr(&self) -> &Reg<DCRSR_SPEC>

0xedf4 - With the DCRDR, provides debug access to the general-purpose registers, special-purpose registers, and the FP extension registers. A write to the DCRSR specifies the register to transfer, whether the transfer is a read or write, and starts the transfer

pub fn dcrdr(&self) -> &Reg<DCRDR_SPEC>

0xedf8 - With the DCRSR, provides debug access to the general-purpose registers, special-purpose registers, and the FP Extension registers. If the Main Extension is implemented, it can also be used for message passing between an external debugger and a debug agent running on the PE

pub fn demcr(&self) -> &Reg<DEMCR_SPEC>

0xedfc - Manages vector catch behavior and DebugMonitor handling when debugging

pub fn dscsr(&self) -> &Reg<DSCSR_SPEC>

0xee08 - Provides control and status information for Secure debug

pub fn stir(&self) -> &Reg<STIR_SPEC>

0xef00 - Provides a mechanism for software to generate an interrupt

pub fn fpccr(&self) -> &Reg<FPCCR_SPEC>

0xef34 - Holds control data for the Floating-point extension

pub fn fpcar(&self) -> &Reg<FPCAR_SPEC>

0xef38 - Holds the location of the unpopulated floating-point register space allocated on an exception stack frame

pub fn fpdscr(&self) -> &Reg<FPDSCR_SPEC>

0xef3c - Holds the default values for the floating-point status control data that the PE assigns to the FPSCR when it creates a new floating-point context

pub fn mvfr0(&self) -> &Reg<MVFR0_SPEC>

0xef40 - Describes the features provided by the Floating-point Extension

pub fn mvfr1(&self) -> &Reg<MVFR1_SPEC>

0xef44 - Describes the features provided by the Floating-point Extension

pub fn mvfr2(&self) -> &Reg<MVFR2_SPEC>

0xef48 - Describes the features provided by the Floating-point Extension

pub fn ddevarch(&self) -> &Reg<DDEVARCH_SPEC>

0xefbc - Provides CoreSight discovery information for the SCS

pub fn ddevtype(&self) -> &Reg<DDEVTYPE_SPEC>

0xefcc - Provides CoreSight discovery information for the SCS

pub fn dpidr4(&self) -> &Reg<DPIDR4_SPEC>

0xefd0 - Provides CoreSight discovery information for the SCS

pub fn dpidr5(&self) -> &Reg<DPIDR5_SPEC>

0xefd4 - Provides CoreSight discovery information for the SCS

pub fn dpidr6(&self) -> &Reg<DPIDR6_SPEC>

0xefd8 - Provides CoreSight discovery information for the SCS

pub fn dpidr7(&self) -> &Reg<DPIDR7_SPEC>

0xefdc - Provides CoreSight discovery information for the SCS

pub fn dpidr0(&self) -> &Reg<DPIDR0_SPEC>

0xefe0 - Provides CoreSight discovery information for the SCS

pub fn dpidr1(&self) -> &Reg<DPIDR1_SPEC>

0xefe4 - Provides CoreSight discovery information for the SCS

pub fn dpidr2(&self) -> &Reg<DPIDR2_SPEC>

0xefe8 - Provides CoreSight discovery information for the SCS

pub fn dpidr3(&self) -> &Reg<DPIDR3_SPEC>

0xefec - Provides CoreSight discovery information for the SCS

pub fn dcidr0(&self) -> &Reg<DCIDR0_SPEC>

0xeff0 - Provides CoreSight discovery information for the SCS

pub fn dcidr1(&self) -> &Reg<DCIDR1_SPEC>

0xeff4 - Provides CoreSight discovery information for the SCS

pub fn dcidr2(&self) -> &Reg<DCIDR2_SPEC>

0xeff8 - Provides CoreSight discovery information for the SCS

pub fn dcidr3(&self) -> &Reg<DCIDR3_SPEC>

0xeffc - Provides CoreSight discovery information for the SCS

pub fn trcprgctlr(&self) -> &Reg<TRCPRGCTLR_SPEC>

0x41004 - Programming Control Register

pub fn trcstatr(&self) -> &Reg<TRCSTATR_SPEC>

0x4100c - The TRCSTATR indicates the ETM-Teal status

pub fn trcconfigr(&self) -> &Reg<TRCCONFIGR_SPEC>

0x41010 - The TRCCONFIGR sets the basic tracing options for the trace unit

pub fn trceventctl0r(&self) -> &Reg<TRCEVENTCTL0R_SPEC>

0x41020 - The TRCEVENTCTL0R controls the tracing of events in the trace stream. The events also drive the ETM-Teal external outputs.

pub fn trceventctl1r(&self) -> &Reg<TRCEVENTCTL1R_SPEC>

0x41024 - The TRCEVENTCTL1R controls how the events selected by TRCEVENTCTL0R behave

pub fn trcstallctlr(&self) -> &Reg<TRCSTALLCTLR_SPEC>

0x4102c - The TRCSTALLCTLR enables ETM-Teal to stall the processor if the ETM-Teal FIFO goes over the programmed level to minimize risk of overflow

pub fn trctsctlr(&self) -> &Reg<TRCTSCTLR_SPEC>

0x41030 - The TRCTSCTLR controls the insertion of global timestamps into the trace stream. A timestamp is always inserted into the instruction trace stream

pub fn trcsyncpr(&self) -> &Reg<TRCSYNCPR_SPEC>

0x41034 - The TRCSYNCPR specifies the period of trace synchronization of the trace streams. TRCSYNCPR defines a number of bytes of trace between requests for trace synchronization. This value is always a power of two

pub fn trcccctlr(&self) -> &Reg<TRCCCCTLR_SPEC>

0x41038 - The TRCCCCTLR sets the threshold value for instruction trace cycle counting. The threshold represents the minimum interval between cycle count trace packets

pub fn trcvictlr(&self) -> &Reg<TRCVICTLR_SPEC>

0x41080 - The TRCVICTLR controls instruction trace filtering

pub fn trccntrldvr0(&self) -> &Reg<TRCCNTRLDVR0_SPEC>

0x41140 - The TRCCNTRLDVR defines the reload value for the reduced function counter

pub fn trcidr8(&self) -> &Reg<TRCIDR8_SPEC>

0x41180 - TRCIDR8

pub fn trcidr9(&self) -> &Reg<TRCIDR9_SPEC>

0x41184 - TRCIDR9

pub fn trcidr10(&self) -> &Reg<TRCIDR10_SPEC>

0x41188 - TRCIDR10

pub fn trcidr11(&self) -> &Reg<TRCIDR11_SPEC>

0x4118c - TRCIDR11

pub fn trcidr12(&self) -> &Reg<TRCIDR12_SPEC>

0x41190 - TRCIDR12

pub fn trcidr13(&self) -> &Reg<TRCIDR13_SPEC>

0x41194 - TRCIDR13

pub fn trcimspec(&self) -> &Reg<TRCIMSPEC_SPEC>

0x411c0 - The TRCIMSPEC shows the presence of any IMPLEMENTATION SPECIFIC features, and enables any features that are provided

pub fn trcidr0(&self) -> &Reg<TRCIDR0_SPEC>

0x411e0 - TRCIDR0

pub fn trcidr1(&self) -> &Reg<TRCIDR1_SPEC>

0x411e4 - TRCIDR1

pub fn trcidr2(&self) -> &Reg<TRCIDR2_SPEC>

0x411e8 - TRCIDR2

pub fn trcidr3(&self) -> &Reg<TRCIDR3_SPEC>

0x411ec - TRCIDR3

pub fn trcidr4(&self) -> &Reg<TRCIDR4_SPEC>

0x411f0 - TRCIDR4

pub fn trcidr5(&self) -> &Reg<TRCIDR5_SPEC>

0x411f4 - TRCIDR5

pub fn trcidr6(&self) -> &Reg<TRCIDR6_SPEC>

0x411f8 - TRCIDR6

pub fn trcidr7(&self) -> &Reg<TRCIDR7_SPEC>

0x411fc - TRCIDR7

pub fn trcrsctlr2(&self) -> &Reg<TRCRSCTLR2_SPEC>

0x41208 - The TRCRSCTLR controls the trace resources

pub fn trcrsctlr3(&self) -> &Reg<TRCRSCTLR3_SPEC>

0x4120c - The TRCRSCTLR controls the trace resources

pub fn trcsscsr(&self) -> &Reg<TRCSSCSR_SPEC>

0x412a0 - Controls the corresponding single-shot comparator resource

pub fn trcsspcicr(&self) -> &Reg<TRCSSPCICR_SPEC>

0x412c0 - Selects the PE comparator inputs for Single-shot control

pub fn trcpdcr(&self) -> &Reg<TRCPDCR_SPEC>

0x41310 - Requests the system to provide power to the trace unit

pub fn trcpdsr(&self) -> &Reg<TRCPDSR_SPEC>

0x41314 - Returns the following information about the trace unit: - OS Lock status. - Core power domain status. - Power interruption status

pub fn trcitatbidr(&self) -> &Reg<TRCITATBIDR_SPEC>

0x41ee4 - Trace Integration ATB Identification Register

pub fn trcitiatbinr(&self) -> &Reg<TRCITIATBINR_SPEC>

0x41ef4 - Trace Integration Instruction ATB In Register

pub fn trcitiatboutr(&self) -> &Reg<TRCITIATBOUTR_SPEC>

0x41efc - Trace Integration Instruction ATB Out Register

pub fn trcclaimset(&self) -> &Reg<TRCCLAIMSET_SPEC>

0x41fa0 - Claim Tag Set Register

pub fn trcclaimclr(&self) -> &Reg<TRCCLAIMCLR_SPEC>

0x41fa4 - Claim Tag Clear Register

pub fn trcauthstatus(&self) -> &Reg<TRCAUTHSTATUS_SPEC>

0x41fb8 - Returns the level of tracing that the trace unit can support

pub fn trcdevarch(&self) -> &Reg<TRCDEVARCH_SPEC>

0x41fbc - TRCDEVARCH

pub fn trcdevid(&self) -> &Reg<TRCDEVID_SPEC>

0x41fc8 - TRCDEVID

pub fn trcdevtype(&self) -> &Reg<TRCDEVTYPE_SPEC>

0x41fcc - TRCDEVTYPE

pub fn trcpidr4(&self) -> &Reg<TRCPIDR4_SPEC>

0x41fd0 - TRCPIDR4

pub fn trcpidr5(&self) -> &Reg<TRCPIDR5_SPEC>

0x41fd4 - TRCPIDR5

pub fn trcpidr6(&self) -> &Reg<TRCPIDR6_SPEC>

0x41fd8 - TRCPIDR6

pub fn trcpidr7(&self) -> &Reg<TRCPIDR7_SPEC>

0x41fdc - TRCPIDR7

pub fn trcpidr0(&self) -> &Reg<TRCPIDR0_SPEC>

0x41fe0 - TRCPIDR0

pub fn trcpidr1(&self) -> &Reg<TRCPIDR1_SPEC>

0x41fe4 - TRCPIDR1

pub fn trcpidr2(&self) -> &Reg<TRCPIDR2_SPEC>

0x41fe8 - TRCPIDR2

pub fn trcpidr3(&self) -> &Reg<TRCPIDR3_SPEC>

0x41fec - TRCPIDR3

pub fn trccidr0(&self) -> &Reg<TRCCIDR0_SPEC>

0x41ff0 - TRCCIDR0

pub fn trccidr1(&self) -> &Reg<TRCCIDR1_SPEC>

0x41ff4 - TRCCIDR1

pub fn trccidr2(&self) -> &Reg<TRCCIDR2_SPEC>

0x41ff8 - TRCCIDR2

pub fn trccidr3(&self) -> &Reg<TRCCIDR3_SPEC>

0x41ffc - TRCCIDR3

pub fn cticontrol(&self) -> &Reg<CTICONTROL_SPEC>

0x42000 - CTI Control Register

pub fn ctiintack(&self) -> &Reg<CTIINTACK_SPEC>

0x42010 - CTI Interrupt Acknowledge Register

pub fn ctiappset(&self) -> &Reg<CTIAPPSET_SPEC>

0x42014 - CTI Application Trigger Set Register

pub fn ctiappclear(&self) -> &Reg<CTIAPPCLEAR_SPEC>

0x42018 - CTI Application Trigger Clear Register

pub fn ctiapppulse(&self) -> &Reg<CTIAPPPULSE_SPEC>

0x4201c - CTI Application Pulse Register

pub fn ctiinen0(&self) -> &Reg<CTIINEN0_SPEC>

0x42020 - CTI Trigger to Channel Enable Registers

pub fn ctiinen1(&self) -> &Reg<CTIINEN1_SPEC>

0x42024 - CTI Trigger to Channel Enable Registers

pub fn ctiinen2(&self) -> &Reg<CTIINEN2_SPEC>

0x42028 - CTI Trigger to Channel Enable Registers

pub fn ctiinen3(&self) -> &Reg<CTIINEN3_SPEC>

0x4202c - CTI Trigger to Channel Enable Registers

pub fn ctiinen4(&self) -> &Reg<CTIINEN4_SPEC>

0x42030 - CTI Trigger to Channel Enable Registers

pub fn ctiinen5(&self) -> &Reg<CTIINEN5_SPEC>

0x42034 - CTI Trigger to Channel Enable Registers

pub fn ctiinen6(&self) -> &Reg<CTIINEN6_SPEC>

0x42038 - CTI Trigger to Channel Enable Registers

pub fn ctiinen7(&self) -> &Reg<CTIINEN7_SPEC>

0x4203c - CTI Trigger to Channel Enable Registers

pub fn ctiouten0(&self) -> &Reg<CTIOUTEN0_SPEC>

0x420a0 - CTI Trigger to Channel Enable Registers

pub fn ctiouten1(&self) -> &Reg<CTIOUTEN1_SPEC>

0x420a4 - CTI Trigger to Channel Enable Registers

pub fn ctiouten2(&self) -> &Reg<CTIOUTEN2_SPEC>

0x420a8 - CTI Trigger to Channel Enable Registers

pub fn ctiouten3(&self) -> &Reg<CTIOUTEN3_SPEC>

0x420ac - CTI Trigger to Channel Enable Registers

pub fn ctiouten4(&self) -> &Reg<CTIOUTEN4_SPEC>

0x420b0 - CTI Trigger to Channel Enable Registers

pub fn ctiouten5(&self) -> &Reg<CTIOUTEN5_SPEC>

0x420b4 - CTI Trigger to Channel Enable Registers

pub fn ctiouten6(&self) -> &Reg<CTIOUTEN6_SPEC>

0x420b8 - CTI Trigger to Channel Enable Registers

pub fn ctiouten7(&self) -> &Reg<CTIOUTEN7_SPEC>

0x420bc - CTI Trigger to Channel Enable Registers

pub fn ctitriginstatus(&self) -> &Reg<CTITRIGINSTATUS_SPEC>

0x42130 - CTI Trigger to Channel Enable Registers

pub fn ctitrigoutstatus(&self) -> &Reg<CTITRIGOUTSTATUS_SPEC>

0x42134 - CTI Trigger In Status Register

pub fn ctichinstatus(&self) -> &Reg<CTICHINSTATUS_SPEC>

0x42138 - CTI Channel In Status Register

pub fn ctigate(&self) -> &Reg<CTIGATE_SPEC>

0x42140 - Enable CTI Channel Gate register

pub fn asicctl(&self) -> &Reg<ASICCTL_SPEC>

0x42144 - External Multiplexer Control register

pub fn itchout(&self) -> &Reg<ITCHOUT_SPEC>

0x42ee4 - Integration Test Channel Output register

pub fn ittrigout(&self) -> &Reg<ITTRIGOUT_SPEC>

0x42ee8 - Integration Test Trigger Output register

pub fn itchin(&self) -> &Reg<ITCHIN_SPEC>

0x42ef4 - Integration Test Channel Input register

pub fn itctrl(&self) -> &Reg<ITCTRL_SPEC>

0x42f00 - Integration Mode Control register

pub fn devarch(&self) -> &Reg<DEVARCH_SPEC>

0x42fbc - Device Architecture register

pub fn devid(&self) -> &Reg<DEVID_SPEC>

0x42fc8 - Device Configuration register

pub fn devtype(&self) -> &Reg<DEVTYPE_SPEC>

0x42fcc - Device Type Identifier register

pub fn pidr4(&self) -> &Reg<PIDR4_SPEC>

0x42fd0 - CoreSight Peripheral ID4

pub fn pidr5(&self) -> &Reg<PIDR5_SPEC>

0x42fd4 - CoreSight Peripheral ID5

pub fn pidr6(&self) -> &Reg<PIDR6_SPEC>

0x42fd8 - CoreSight Peripheral ID6

pub fn pidr7(&self) -> &Reg<PIDR7_SPEC>

0x42fdc - CoreSight Peripheral ID7

pub fn pidr0(&self) -> &Reg<PIDR0_SPEC>

0x42fe0 - CoreSight Peripheral ID0

pub fn pidr1(&self) -> &Reg<PIDR1_SPEC>

0x42fe4 - CoreSight Peripheral ID1

pub fn pidr2(&self) -> &Reg<PIDR2_SPEC>

0x42fe8 - CoreSight Peripheral ID2

pub fn pidr3(&self) -> &Reg<PIDR3_SPEC>

0x42fec - CoreSight Peripheral ID3

pub fn cidr0(&self) -> &Reg<CIDR0_SPEC>

0x42ff0 - CoreSight Component ID0

pub fn cidr1(&self) -> &Reg<CIDR1_SPEC>

0x42ff4 - CoreSight Component ID1

pub fn cidr2(&self) -> &Reg<CIDR2_SPEC>

0x42ff8 - CoreSight Component ID2

pub fn cidr3(&self) -> &Reg<CIDR3_SPEC>

0x42ffc - CoreSight Component ID3

Trait Implementations

impl Debug for PPB_NS

fn fmt(&self, f: &mut Formatter<'_>) -> Result<(), Error>

Formats the value using the given formatter.

impl Deref for PPB_NS

type Target = RegisterBlock

The resulting type after dereferencing.

fn deref(&self) -> &<PPB_NS as Deref>::Target

Dereferences the value.

impl Send for PPB_NS