Struct RegisterBlock 

pub struct RegisterBlock { /* private fields */ }

Register block

Implementations

impl RegisterBlock

pub const fn cpuid(&self) -> &Reg<CPUID_SPEC>

0x00 - Processor core identifier

pub const fn gpio_in(&self) -> &Reg<GPIO_IN_SPEC>

0x04 - Input value for GPIO0…31. In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) appear as zero.

pub const fn gpio_hi_in(&self) -> &Reg<GPIO_HI_IN_SPEC>

0x08 - Input value on GPIO32…47, QSPI IOs and USB pins In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) appear as zero.

pub const fn gpio_out(&self) -> &Reg<GPIO_OUT_SPEC>

0x10 - GPIO0…31 output value

pub const fn gpio_hi_out(&self) -> &Reg<GPIO_HI_OUT_SPEC>

0x14 - Output value for GPIO32…47, QSPI IOs and USB pins. Write to set output level (1/0 -> high/low). Reading back gives the last value written, NOT the input value from the pins. If core 0 and core 1 both write to GPIO_HI_OUT simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result. In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) ignore writes, and their output status reads back as zero. This is also true for SET/CLR/XOR aliases of this register.

pub const fn gpio_out_set(&self) -> &Reg<GPIO_OUT_SET_SPEC>

0x18 - GPIO0…31 output value set

pub const fn gpio_hi_out_set(&self) -> &Reg<GPIO_HI_OUT_SET_SPEC>

0x1c - Output value set for GPIO32..47, QSPI IOs and USB pins. Perform an atomic bit-set on GPIO_HI_OUT, i.e. GPIO_HI_OUT |= wdata

pub const fn gpio_out_clr(&self) -> &Reg<GPIO_OUT_CLR_SPEC>

0x20 - GPIO0…31 output value clear

pub const fn gpio_hi_out_clr(&self) -> &Reg<GPIO_HI_OUT_CLR_SPEC>

0x24 - Output value clear for GPIO32..47, QSPI IOs and USB pins. Perform an atomic bit-clear on GPIO_HI_OUT, i.e. GPIO_HI_OUT &= ~wdata

pub const fn gpio_out_xor(&self) -> &Reg<GPIO_OUT_XOR_SPEC>

0x28 - GPIO0…31 output value XOR

pub const fn gpio_hi_out_xor(&self) -> &Reg<GPIO_HI_OUT_XOR_SPEC>

0x2c - Output value XOR for GPIO32..47, QSPI IOs and USB pins. Perform an atomic bitwise XOR on GPIO_HI_OUT, i.e. GPIO_HI_OUT ^= wdata

pub const fn gpio_oe(&self) -> &Reg<GPIO_OE_SPEC>

0x30 - GPIO0…31 output enable

pub const fn gpio_hi_oe(&self) -> &Reg<GPIO_HI_OE_SPEC>

0x34 - Output enable value for GPIO32…47, QSPI IOs and USB pins. Write output enable (1/0 -> output/input). Reading back gives the last value written. If core 0 and core 1 both write to GPIO_HI_OE simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result. In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) ignore writes, and their output status reads back as zero. This is also true for SET/CLR/XOR aliases of this register.

pub const fn gpio_oe_set(&self) -> &Reg<GPIO_OE_SET_SPEC>

0x38 - GPIO0…31 output enable set

pub const fn gpio_hi_oe_set(&self) -> &Reg<GPIO_HI_OE_SET_SPEC>

0x3c - Output enable set for GPIO32…47, QSPI IOs and USB pins. Perform an atomic bit-set on GPIO_HI_OE, i.e. GPIO_HI_OE |= wdata

pub const fn gpio_oe_clr(&self) -> &Reg<GPIO_OE_CLR_SPEC>

0x40 - GPIO0…31 output enable clear

pub const fn gpio_hi_oe_clr(&self) -> &Reg<GPIO_HI_OE_CLR_SPEC>

0x44 - Output enable clear for GPIO32…47, QSPI IOs and USB pins. Perform an atomic bit-clear on GPIO_HI_OE, i.e. GPIO_HI_OE &= ~wdata

pub const fn gpio_oe_xor(&self) -> &Reg<GPIO_OE_XOR_SPEC>

0x48 - GPIO0…31 output enable XOR

pub const fn gpio_hi_oe_xor(&self) -> &Reg<GPIO_HI_OE_XOR_SPEC>

0x4c - Output enable XOR for GPIO32…47, QSPI IOs and USB pins. Perform an atomic bitwise XOR on GPIO_HI_OE, i.e. GPIO_HI_OE ^= wdata

pub const fn fifo_st(&self) -> &Reg<FIFO_ST_SPEC>

0x50 - Status register for inter-core FIFOs (mailboxes). There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep. Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX). Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX). The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register.

pub const fn fifo_wr(&self) -> &Reg<FIFO_WR_SPEC>

0x54 - Write access to this core’s TX FIFO

pub const fn fifo_rd(&self) -> &Reg<FIFO_RD_SPEC>

0x58 - Read access to this core’s RX FIFO

pub const fn spinlock_st(&self) -> &Reg<SPINLOCK_ST_SPEC>

0x5c - Spinlock state A bitmap containing the state of all 32 spinlocks (1=locked). Mainly intended for debugging.

pub const fn interp0_accum0(&self) -> &Reg<INTERP0_ACCUM0_SPEC>

0x80 - Read/write access to accumulator 0

pub const fn interp0_accum1(&self) -> &Reg<INTERP0_ACCUM1_SPEC>

0x84 - Read/write access to accumulator 1

pub const fn interp0_base0(&self) -> &Reg<INTERP0_BASE0_SPEC>

0x88 - Read/write access to BASE0 register.

pub const fn interp0_base1(&self) -> &Reg<INTERP0_BASE1_SPEC>

0x8c - Read/write access to BASE1 register.

pub const fn interp0_base2(&self) -> &Reg<INTERP0_BASE2_SPEC>

0x90 - Read/write access to BASE2 register.

pub const fn interp0_pop_lane0(&self) -> &Reg<INTERP0_POP_LANE0_SPEC>

0x94 - Read LANE0 result, and simultaneously write lane results to both accumulators (POP).

pub const fn interp0_pop_lane1(&self) -> &Reg<INTERP0_POP_LANE1_SPEC>

0x98 - Read LANE1 result, and simultaneously write lane results to both accumulators (POP).

pub const fn interp0_pop_full(&self) -> &Reg<INTERP0_POP_FULL_SPEC>

0x9c - Read FULL result, and simultaneously write lane results to both accumulators (POP).

pub const fn interp0_peek_lane0(&self) -> &Reg<INTERP0_PEEK_LANE0_SPEC>

0xa0 - Read LANE0 result, without altering any internal state (PEEK).

pub const fn interp0_peek_lane1(&self) -> &Reg<INTERP0_PEEK_LANE1_SPEC>

0xa4 - Read LANE1 result, without altering any internal state (PEEK).

pub const fn interp0_peek_full(&self) -> &Reg<INTERP0_PEEK_FULL_SPEC>

0xa8 - Read FULL result, without altering any internal state (PEEK).

pub const fn interp0_ctrl_lane0(&self) -> &Reg<INTERP0_CTRL_LANE0_SPEC>

0xac - Control register for lane 0

pub const fn interp0_ctrl_lane1(&self) -> &Reg<INTERP0_CTRL_LANE1_SPEC>

0xb0 - Control register for lane 1

pub const fn interp0_accum0_add(&self) -> &Reg<INTERP0_ACCUM0_ADD_SPEC>

0xb4 - Values written here are atomically added to ACCUM0 Reading yields lane 0’s raw shift and mask value (BASE0 not added).

pub const fn interp0_accum1_add(&self) -> &Reg<INTERP0_ACCUM1_ADD_SPEC>

0xb8 - Values written here are atomically added to ACCUM1 Reading yields lane 1’s raw shift and mask value (BASE1 not added).

pub const fn interp0_base_1and0(&self) -> &Reg<INTERP0_BASE_1AND0_SPEC>

0xbc - On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. Each half is sign-extended to 32 bits if that lane’s SIGNED flag is set.

pub const fn interp1_accum0(&self) -> &Reg<INTERP1_ACCUM0_SPEC>

0xc0 - Read/write access to accumulator 0

pub const fn interp1_accum1(&self) -> &Reg<INTERP1_ACCUM1_SPEC>

0xc4 - Read/write access to accumulator 1

pub const fn interp1_base0(&self) -> &Reg<INTERP1_BASE0_SPEC>

0xc8 - Read/write access to BASE0 register.

pub const fn interp1_base1(&self) -> &Reg<INTERP1_BASE1_SPEC>

0xcc - Read/write access to BASE1 register.

pub const fn interp1_base2(&self) -> &Reg<INTERP1_BASE2_SPEC>

0xd0 - Read/write access to BASE2 register.

pub const fn interp1_pop_lane0(&self) -> &Reg<INTERP1_POP_LANE0_SPEC>

0xd4 - Read LANE0 result, and simultaneously write lane results to both accumulators (POP).

pub const fn interp1_pop_lane1(&self) -> &Reg<INTERP1_POP_LANE1_SPEC>

0xd8 - Read LANE1 result, and simultaneously write lane results to both accumulators (POP).

pub const fn interp1_pop_full(&self) -> &Reg<INTERP1_POP_FULL_SPEC>

0xdc - Read FULL result, and simultaneously write lane results to both accumulators (POP).

pub const fn interp1_peek_lane0(&self) -> &Reg<INTERP1_PEEK_LANE0_SPEC>

0xe0 - Read LANE0 result, without altering any internal state (PEEK).

pub const fn interp1_peek_lane1(&self) -> &Reg<INTERP1_PEEK_LANE1_SPEC>

0xe4 - Read LANE1 result, without altering any internal state (PEEK).

pub const fn interp1_peek_full(&self) -> &Reg<INTERP1_PEEK_FULL_SPEC>

0xe8 - Read FULL result, without altering any internal state (PEEK).

pub const fn interp1_ctrl_lane0(&self) -> &Reg<INTERP1_CTRL_LANE0_SPEC>

0xec - Control register for lane 0

pub const fn interp1_ctrl_lane1(&self) -> &Reg<INTERP1_CTRL_LANE1_SPEC>

0xf0 - Control register for lane 1

pub const fn interp1_accum0_add(&self) -> &Reg<INTERP1_ACCUM0_ADD_SPEC>

0xf4 - Values written here are atomically added to ACCUM0 Reading yields lane 0’s raw shift and mask value (BASE0 not added).

pub const fn interp1_accum1_add(&self) -> &Reg<INTERP1_ACCUM1_ADD_SPEC>

0xf8 - Values written here are atomically added to ACCUM1 Reading yields lane 1’s raw shift and mask value (BASE1 not added).

pub const fn interp1_base_1and0(&self) -> &Reg<INTERP1_BASE_1AND0_SPEC>

0xfc - On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. Each half is sign-extended to 32 bits if that lane’s SIGNED flag is set.

pub const fn spinlock(&self, n: usize) -> &Reg<SPINLOCK_SPEC>

0x100..0x180 - Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number.

pub fn spinlock_iter(&self) -> impl Iterator<Item = &Reg<SPINLOCK_SPEC>>

Iterator for array of: 0x100..0x180 - Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number.

pub const fn doorbell_out_set(&self) -> &Reg<DOORBELL_OUT_SET_SPEC>

0x180 - Trigger a doorbell interrupt on the opposite core. Write 1 to a bit to set the corresponding bit in DOORBELL_IN on the opposite core. This raises the opposite core’s doorbell interrupt. Read to get the status of the doorbells currently asserted on the opposite core. This is equivalent to that core reading its own DOORBELL_IN status.

pub const fn doorbell_out_clr(&self) -> &Reg<DOORBELL_OUT_CLR_SPEC>

0x184 - Clear doorbells which have been posted to the opposite core. This register is intended for debugging and initialisation purposes. Writing 1 to a bit in DOORBELL_OUT_CLR clears the corresponding bit in DOORBELL_IN on the opposite core. Clearing all bits will cause that core’s doorbell interrupt to deassert. Since the usual order of events is for software to send events using DOORBELL_OUT_SET, and acknowledge incoming events by writing to DOORBELL_IN_CLR, this register should be used with caution to avoid race conditions. Reading returns the status of the doorbells currently asserted on the other core, i.e. is equivalent to that core reading its own DOORBELL_IN status.

pub const fn doorbell_in_set(&self) -> &Reg<DOORBELL_IN_SET_SPEC>

0x188 - Write 1s to trigger doorbell interrupts on this core. Read to get status of doorbells currently asserted on this core.

pub const fn doorbell_in_clr(&self) -> &Reg<DOORBELL_IN_CLR_SPEC>

0x18c - Check and acknowledge doorbells posted to this core. This core’s doorbell interrupt is asserted when any bit in this register is 1. Write 1 to each bit to clear that bit. The doorbell interrupt deasserts once all bits are cleared. Read to get status of doorbells currently asserted on this core.

pub const fn peri_nonsec(&self) -> &Reg<PERI_NONSEC_SPEC>

0x190 - Detach certain core-local peripherals from Secure SIO, and attach them to Non-secure SIO, so that Non-secure software can use them. Attempting to access one of these peripherals from the Secure SIO when it is attached to the Non-secure SIO, or vice versa, will generate a bus error. This register is per-core, and is only present on the Secure SIO. Most SIO hardware is duplicated across the Secure and Non-secure SIO, so is not listed in this register.

pub const fn riscv_softirq(&self) -> &Reg<RISCV_SOFTIRQ_SPEC>

0x1a0 - Control the assertion of the standard software interrupt (MIP.MSIP) on the RISC-V cores. Unlike the RISC-V timer, this interrupt is not routed to a normal system-level interrupt line, so can not be used by the Arm cores. It is safe for both cores to write to this register on the same cycle. The set/clear effect is accumulated across both cores, and then applied. If a flag is both set and cleared on the same cycle, only the set takes effect.

pub const fn mtime_ctrl(&self) -> &Reg<MTIME_CTRL_SPEC>

0x1a4 - Control register for the RISC-V 64-bit Machine-mode timer. This timer is only present in the Secure SIO, so is only accessible to an Arm core in Secure mode or a RISC-V core in Machine mode. Note whilst this timer follows the RISC-V privileged specification, it is equally usable by the Arm cores. The interrupts are routed to normal system-level interrupt lines as well as to the MIP.MTIP inputs on the RISC-V cores.

pub const fn mtime(&self) -> &Reg<MTIME_SPEC>

0x1b0 - Read/write access to the high half of RISC-V Machine-mode timer. This register is shared between both cores. If both cores write on the same cycle, core 1 takes precedence.

pub const fn mtimeh(&self) -> &Reg<MTIMEH_SPEC>

0x1b4 - Read/write access to the high half of RISC-V Machine-mode timer. This register is shared between both cores. If both cores write on the same cycle, core 1 takes precedence.

pub const fn mtimecmp(&self) -> &Reg<MTIMECMP_SPEC>

0x1b8 - Low half of RISC-V Machine-mode timer comparator. This register is core-local, i.e., each core gets a copy of this register, with the comparison result routed to its own interrupt line. The timer interrupt is asserted whenever MTIME is greater than or equal to MTIMECMP. This comparison is unsigned, and performed on the full 64-bit values.

pub const fn mtimecmph(&self) -> &Reg<MTIMECMPH_SPEC>

0x1bc - High half of RISC-V Machine-mode timer comparator. This register is core-local. The timer interrupt is asserted whenever MTIME is greater than or equal to MTIMECMP. This comparison is unsigned, and performed on the full 64-bit values.

pub const fn tmds_ctrl(&self) -> &Reg<TMDS_CTRL_SPEC>

0x1c0 - Control register for TMDS encoder.

pub const fn tmds_wdata(&self) -> &Reg<TMDS_WDATA_SPEC>

0x1c4 - Write-only access to the TMDS colour data register.

pub const fn tmds_peek_single(&self) -> &Reg<TMDS_PEEK_SINGLE_SPEC>

0x1c8 - Get the encoding of one pixel’s worth of colour data, packed into a 32-bit value (3x10-bit symbols). The PEEK alias does not shift the colour register when read, but still advances the running DC balance state of each encoder. This is useful for pixel doubling.

pub const fn tmds_pop_single(&self) -> &Reg<TMDS_POP_SINGLE_SPEC>

0x1cc - Get the encoding of one pixel’s worth of colour data, packed into a 32-bit value. The packing is 5 chunks of 3 lanes times 2 bits (30 bits total). Each chunk contains two bits of a TMDS symbol per lane. This format is intended for shifting out with the HSTX peripheral on RP2350. The POP alias shifts the colour register when read, as well as advancing the running DC balance state of each encoder.

pub const fn tmds_peek_double_l0(&self) -> &Reg<TMDS_PEEK_DOUBLE_L0_SPEC>

0x1d0 - Get lane 0 of the encoding of two pixels’ worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. The PEEK alias does not shift the colour register when read, but still advances the lane 0 DC balance state. This is useful if all 3 lanes’ worth of encode are to be read at once, rather than processing the entire scanline for one lane before moving to the next lane.

pub const fn tmds_pop_double_l0(&self) -> &Reg<TMDS_POP_DOUBLE_L0_SPEC>

0x1d4 - Get lane 0 of the encoding of two pixels’ worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. The POP alias shifts the colour register when read, according to the values of PIX_SHIFT and PIX2_NOSHIFT.

pub const fn tmds_peek_double_l1(&self) -> &Reg<TMDS_PEEK_DOUBLE_L1_SPEC>

0x1d8 - Get lane 1 of the encoding of two pixels’ worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. The PEEK alias does not shift the colour register when read, but still advances the lane 1 DC balance state. This is useful if all 3 lanes’ worth of encode are to be read at once, rather than processing the entire scanline for one lane before moving to the next lane.

pub const fn tmds_pop_double_l1(&self) -> &Reg<TMDS_POP_DOUBLE_L1_SPEC>

0x1dc - Get lane 1 of the encoding of two pixels’ worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. The POP alias shifts the colour register when read, according to the values of PIX_SHIFT and PIX2_NOSHIFT.

pub const fn tmds_peek_double_l2(&self) -> &Reg<TMDS_PEEK_DOUBLE_L2_SPEC>

0x1e0 - Get lane 2 of the encoding of two pixels’ worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. The PEEK alias does not shift the colour register when read, but still advances the lane 2 DC balance state. This is useful if all 3 lanes’ worth of encode are to be read at once, rather than processing the entire scanline for one lane before moving to the next lane.

pub const fn tmds_pop_double_l2(&self) -> &Reg<TMDS_POP_DOUBLE_L2_SPEC>

0x1e4 - Get lane 2 of the encoding of two pixels’ worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. The POP alias shifts the colour register when read, according to the values of PIX_SHIFT and PIX2_NOSHIFT.