Struct RegisterBlock 

pub struct RegisterBlock { /* private fields */ }

Register block

Implementations

impl RegisterBlock

pub const fn badpasswd(&self) -> &Reg<BADPASSWD_SPEC>

0x00 - Indicates a bad password has been used

pub const fn vreg_ctrl(&self) -> &Reg<VREG_CTRL_SPEC>

0x04 - Voltage Regulator Control

pub const fn vreg_sts(&self) -> &Reg<VREG_STS_SPEC>

0x08 - Voltage Regulator Status

pub const fn vreg(&self) -> &Reg<VREG_SPEC>

0x0c - Voltage Regulator Settings

pub const fn vreg_lp_entry(&self) -> &Reg<VREG_LP_ENTRY_SPEC>

0x10 - Voltage Regulator Low Power Entry Settings

pub const fn vreg_lp_exit(&self) -> &Reg<VREG_LP_EXIT_SPEC>

0x14 - Voltage Regulator Low Power Exit Settings

pub const fn bod_ctrl(&self) -> &Reg<BOD_CTRL_SPEC>

0x18 - Brown-out Detection Control

pub const fn bod(&self) -> &Reg<BOD_SPEC>

0x1c - Brown-out Detection Settings

pub const fn bod_lp_entry(&self) -> &Reg<BOD_LP_ENTRY_SPEC>

0x20 - Brown-out Detection Low Power Entry Settings

pub const fn bod_lp_exit(&self) -> &Reg<BOD_LP_EXIT_SPEC>

0x24 - Brown-out Detection Low Power Exit Settings

pub const fn lposc(&self) -> &Reg<LPOSC_SPEC>

0x28 - Low power oscillator control register.

pub const fn chip_reset(&self) -> &Reg<CHIP_RESET_SPEC>

0x2c - Chip reset control and status

pub const fn wdsel(&self) -> &Reg<WDSEL_SPEC>

0x30 - Allows a watchdog reset to reset the internal state of powman in addition to the power-on state machine (PSM). Note that powman ignores watchdog resets that do not select at least the CLOCKS stage or earlier stages in the PSM. If using these bits, it’s recommended to set PSM_WDSEL to all-ones in addition to the desired bits in this register. Failing to select CLOCKS or earlier will result in the POWMAN_WDSEL register having no effect.

pub const fn seq_cfg(&self) -> &Reg<SEQ_CFG_SPEC>

0x34 - For configuration of the power sequencer Writes are ignored while POWMAN_STATE_CHANGING=1

pub const fn state(&self) -> &Reg<STATE_SPEC>

0x38 - This register controls the power state of the 4 power domains. The current power state is indicated in POWMAN_STATE_CURRENT which is read-only. To change the state, write to POWMAN_STATE_REQ. The coding of POWMAN_STATE_CURRENT & POWMAN_STATE_REQ corresponds to the power states defined in the datasheet: bit 3 = SWCORE bit 2 = XIP cache bit 1 = SRAM0 bit 0 = SRAM1 0 = powered up 1 = powered down When POWMAN_STATE_REQ is written, the POWMAN_STATE_WAITING flag is set while the Power Manager determines what is required. If an invalid transition is requested the Power Manager will still register the request in POWMAN_STATE_REQ but will also set the POWMAN_BAD_REQ flag. It will then implement the power-up requests and ignore the power down requests. To do nothing would risk entering an unrecoverable lock-up state. Invalid requests are: any combination of power up and power down requests any request that results in swcore boing powered and xip unpowered If the request is to power down the switched-core domain then POWMAN_STATE_WAITING stays active until the processors halt. During this time the POWMAN_STATE_REQ field can be re-written to change or cancel the request. When the power state transition begins the POWMAN_STATE_WAITING_flag is cleared, the POWMAN_STATE_CHANGING flag is set and POWMAN register writes are ignored until the transition completes.

pub const fn pow_fastdiv(&self) -> &Reg<POW_FASTDIV_SPEC>

0x3c -

pub const fn pow_delay(&self) -> &Reg<POW_DELAY_SPEC>

0x40 - power state machine delays

pub const fn ext_ctrl0(&self) -> &Reg<EXT_CTRL0_SPEC>

0x44 - Configures a gpio as a power mode aware control output

pub const fn ext_ctrl1(&self) -> &Reg<EXT_CTRL1_SPEC>

0x48 - Configures a gpio as a power mode aware control output

pub const fn ext_time_ref(&self) -> &Reg<EXT_TIME_REF_SPEC>

0x4c - Select a GPIO to use as a time reference, the source can be used to drive the low power clock at 32kHz, or to provide a 1ms tick to the timer, or provide a 1Hz tick to the timer. The tick selection is controlled by the POWMAN_TIMER register.

pub const fn lposc_freq_khz_int(&self) -> &Reg<LPOSC_FREQ_KHZ_INT_SPEC>

0x50 - Informs the AON Timer of the integer component of the clock frequency when running off the LPOSC.

pub const fn lposc_freq_khz_frac(&self) -> &Reg<LPOSC_FREQ_KHZ_FRAC_SPEC>

0x54 - Informs the AON Timer of the fractional component of the clock frequency when running off the LPOSC.

pub const fn xosc_freq_khz_int(&self) -> &Reg<XOSC_FREQ_KHZ_INT_SPEC>

0x58 - Informs the AON Timer of the integer component of the clock frequency when running off the XOSC.

pub const fn xosc_freq_khz_frac(&self) -> &Reg<XOSC_FREQ_KHZ_FRAC_SPEC>

0x5c - Informs the AON Timer of the fractional component of the clock frequency when running off the XOSC.

pub const fn set_time_63to48(&self) -> &Reg<SET_TIME_63TO48_SPEC>

0x60 -

pub const fn set_time_47to32(&self) -> &Reg<SET_TIME_47TO32_SPEC>

0x64 -

pub const fn set_time_31to16(&self) -> &Reg<SET_TIME_31TO16_SPEC>

0x68 -

pub const fn set_time_15to0(&self) -> &Reg<SET_TIME_15TO0_SPEC>

0x6c -

pub const fn read_time_upper(&self) -> &Reg<READ_TIME_UPPER_SPEC>

0x70 -

pub const fn read_time_lower(&self) -> &Reg<READ_TIME_LOWER_SPEC>

0x74 -

pub const fn alarm_time_63to48(&self) -> &Reg<ALARM_TIME_63TO48_SPEC>

0x78 -

pub const fn alarm_time_47to32(&self) -> &Reg<ALARM_TIME_47TO32_SPEC>

0x7c -

pub const fn alarm_time_31to16(&self) -> &Reg<ALARM_TIME_31TO16_SPEC>

0x80 -

pub const fn alarm_time_15to0(&self) -> &Reg<ALARM_TIME_15TO0_SPEC>

0x84 -

pub const fn timer(&self) -> &Reg<TIMER_SPEC>

0x88 -

pub const fn pwrup0(&self) -> &Reg<PWRUP0_SPEC>

0x8c - 4 GPIO powerup events can be configured to wake the chip up from a low power state. The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event The number of gpios available depends on the package option. An invalid selection will be ignored source = 0 selects gpio0 . . source = 47 selects gpio47 source = 48 selects qspi_ss source = 49 selects qspi_sd0 source = 50 selects qspi_sd1 source = 51 selects qspi_sd2 source = 52 selects qspi_sd3 source = 53 selects qspi_sclk level = 0 triggers the pwrup when the source is low level = 1 triggers the pwrup when the source is high

pub const fn pwrup1(&self) -> &Reg<PWRUP1_SPEC>

0x90 - 4 GPIO powerup events can be configured to wake the chip up from a low power state. The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event The number of gpios available depends on the package option. An invalid selection will be ignored source = 0 selects gpio0 . . source = 47 selects gpio47 source = 48 selects qspi_ss source = 49 selects qspi_sd0 source = 50 selects qspi_sd1 source = 51 selects qspi_sd2 source = 52 selects qspi_sd3 source = 53 selects qspi_sclk level = 0 triggers the pwrup when the source is low level = 1 triggers the pwrup when the source is high

pub const fn pwrup2(&self) -> &Reg<PWRUP2_SPEC>

0x94 - 4 GPIO powerup events can be configured to wake the chip up from a low power state. The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event The number of gpios available depends on the package option. An invalid selection will be ignored source = 0 selects gpio0 . . source = 47 selects gpio47 source = 48 selects qspi_ss source = 49 selects qspi_sd0 source = 50 selects qspi_sd1 source = 51 selects qspi_sd2 source = 52 selects qspi_sd3 source = 53 selects qspi_sclk level = 0 triggers the pwrup when the source is low level = 1 triggers the pwrup when the source is high

pub const fn pwrup3(&self) -> &Reg<PWRUP3_SPEC>

0x98 - 4 GPIO powerup events can be configured to wake the chip up from a low power state. The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event The number of gpios available depends on the package option. An invalid selection will be ignored source = 0 selects gpio0 . . source = 47 selects gpio47 source = 48 selects qspi_ss source = 49 selects qspi_sd0 source = 50 selects qspi_sd1 source = 51 selects qspi_sd2 source = 52 selects qspi_sd3 source = 53 selects qspi_sclk level = 0 triggers the pwrup when the source is low level = 1 triggers the pwrup when the source is high

pub const fn current_pwrup_req(&self) -> &Reg<CURRENT_PWRUP_REQ_SPEC>

0x9c - Indicates current powerup request state pwrup events can be cleared by removing the enable from the pwrup register. The alarm pwrup req can be cleared by clearing timer.alarm_enab 0 = chip reset, for the source of the last reset see POWMAN_CHIP_RESET 1 = pwrup0 2 = pwrup1 3 = pwrup2 4 = pwrup3 5 = coresight_pwrup 6 = alarm_pwrup

pub const fn last_swcore_pwrup(&self) -> &Reg<LAST_SWCORE_PWRUP_SPEC>

0xa0 - Indicates which pwrup source triggered the last switched-core power up 0 = chip reset, for the source of the last reset see POWMAN_CHIP_RESET 1 = pwrup0 2 = pwrup1 3 = pwrup2 4 = pwrup3 5 = coresight_pwrup 6 = alarm_pwrup

pub const fn dbg_pwrcfg(&self) -> &Reg<DBG_PWRCFG_SPEC>

0xa4 -

pub const fn bootdis(&self) -> &Reg<BOOTDIS_SPEC>

0xa8 - Tell the bootrom to ignore the BOOT0..3 registers following the next RSM reset (e.g. the next core power down/up). If an early boot stage has soft-locked some OTP pages in order to protect their contents from later stages, there is a risk that Secure code running at a later stage can unlock the pages by powering the core up and down. This register can be used to ensure that the bootloader runs as normal on the next power up, preventing Secure code at a later stage from accessing OTP in its unlocked state. Should be used in conjunction with the OTP BOOTDIS register.

pub const fn dbgconfig(&self) -> &Reg<DBGCONFIG_SPEC>

0xac -

pub const fn scratch0(&self) -> &Reg<SCRATCH0_SPEC>

0xb0 - Scratch register. Information persists in low power mode

pub const fn scratch1(&self) -> &Reg<SCRATCH1_SPEC>

0xb4 - Scratch register. Information persists in low power mode

pub const fn scratch2(&self) -> &Reg<SCRATCH2_SPEC>

0xb8 - Scratch register. Information persists in low power mode

pub const fn scratch3(&self) -> &Reg<SCRATCH3_SPEC>

0xbc - Scratch register. Information persists in low power mode

pub const fn scratch4(&self) -> &Reg<SCRATCH4_SPEC>

0xc0 - Scratch register. Information persists in low power mode

pub const fn scratch5(&self) -> &Reg<SCRATCH5_SPEC>

0xc4 - Scratch register. Information persists in low power mode

pub const fn scratch6(&self) -> &Reg<SCRATCH6_SPEC>

0xc8 - Scratch register. Information persists in low power mode

pub const fn scratch7(&self) -> &Reg<SCRATCH7_SPEC>

0xcc - Scratch register. Information persists in low power mode

pub const fn boot0(&self) -> &Reg<BOOT0_SPEC>

0xd0 - Scratch register. Information persists in low power mode

pub const fn boot1(&self) -> &Reg<BOOT1_SPEC>

0xd4 - Scratch register. Information persists in low power mode

pub const fn boot2(&self) -> &Reg<BOOT2_SPEC>

0xd8 - Scratch register. Information persists in low power mode

pub const fn boot3(&self) -> &Reg<BOOT3_SPEC>

0xdc - Scratch register. Information persists in low power mode

pub const fn intr(&self) -> &Reg<INTR_SPEC>

0xe0 - Raw Interrupts

pub const fn inte(&self) -> &Reg<INTE_SPEC>

0xe4 - Interrupt Enable

pub const fn intf(&self) -> &Reg<INTF_SPEC>

0xe8 - Interrupt Force

pub const fn ints(&self) -> &Reg<INTS_SPEC>

0xec - Interrupt status after masking & forcing