Struct RegisterBlock 

pub struct RegisterBlock { /* private fields */ }

Register block

Implementations

impl RegisterBlock

pub const fn arm(&self) -> &Reg<ARM_SPEC>

0x00 - Forcibly arm the glitch detectors, if they are not already armed by OTP. When armed, any individual detector trigger will cause a restart of the switched core power domain’s power-on reset state machine. Glitch detector triggers are recorded accumulatively in TRIG_STATUS. If the system is reset by a glitch detector trigger, this is recorded in POWMAN_CHIP_RESET. This register is Secure read/write only.

pub const fn disarm(&self) -> &Reg<DISARM_SPEC>

0x04 -

pub const fn sensitivity(&self) -> &Reg<SENSITIVITY_SPEC>

0x08 - Adjust the sensitivity of glitch detectors to values other than their OTP-provided defaults. This register is Secure read/write only.

pub const fn lock(&self) -> &Reg<LOCK_SPEC>

0x0c -

pub const fn trig_status(&self) -> &Reg<TRIG_STATUS_SPEC>

0x10 - Set when a detector output triggers. Write-1-clear. (May immediately return high if the detector remains in a failed state. Detectors can only be cleared by a full reset of the switched core power domain.) This register is Secure read/write only.

pub const fn trig_force(&self) -> &Reg<TRIG_FORCE_SPEC>

0x14 - Simulate the firing of one or more detectors. Writing ones to this register will set the matching bits in STATUS_TRIG. If the glitch detectors are currently armed, writing ones will also immediately reset the switched core power domain, and set the reset reason latches in POWMAN_CHIP_RESET to indicate a glitch detector resets. This register is Secure read/write only.