CH

pico_engine_hal::pac::dma

Struct CH 

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pub struct CH { /* private fields */ }
Expand description

Cluster CH%s, containing CH?_READ_ADDR,CH??_READ_ADDR, CH?_WRITE_ADDR,CH??_WRITE_ADDR, CH?_TRANS_COUNT,CH??_TRANS_COUNT, CH?_CTRL_TRIG,CH??_CTRL_TRIG, CH?_AL1_CTRL,CH??_AL1_CTRL, CH?_AL1_READ_ADDR,CH??_AL1_READ_ADDR, CH?_AL1_WRITE_ADDR,CH??_AL1_WRITE_ADDR, CH?_AL1_TRANS_COUNT_TRIG,CH??_AL1_TRANS_COUNT_TRIG, CH?_AL2_CTRL,CH??_AL2_CTRL, CH?_AL2_TRANS_COUNT,CH??_AL2_TRANS_COUNT, CH?_AL2_READ_ADDR,CH??_AL2_READ_ADDR, CH?_AL2_WRITE_ADDR_TRIG,CH??_AL2_WRITE_ADDR_TRIG, CH?_AL3_CTRL,CH??_AL3_CTRL, CH?_AL3_WRITE_ADDR,CH??_AL3_WRITE_ADDR, CH?_AL3_TRANS_COUNT,CH??_AL3_TRANS_COUNT, CH?_AL3_READ_ADDR_TRIG,CH??_AL3_READ_ADDR_TRIG

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impl CH

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pub const fn ch_read_addr(&self) -> &Reg<CH_READ_ADDR_SPEC>

0x00 - DMA Channel 0 Read Address pointer

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pub const fn ch_write_addr(&self) -> &Reg<CH_WRITE_ADDR_SPEC>

0x04 - DMA Channel 0 Write Address pointer

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pub const fn ch_trans_count(&self) -> &Reg<CH_TRANS_COUNT_SPEC>

0x08 - DMA Channel 0 Transfer Count

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pub const fn ch_ctrl_trig(&self) -> &Reg<CH_CTRL_TRIG_SPEC>

0x0c - DMA Channel 0 Control and Status

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pub const fn ch_al1_ctrl(&self) -> &Reg<CH_AL1_CTRL_SPEC>

0x10 - DMA Channel 0 Control and Status

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pub const fn ch_al1_read_addr(&self) -> &Reg<CH_AL1_READ_ADDR_SPEC>

0x14 - Alias for channel 0 READ_ADDR register

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pub const fn ch_al1_write_addr(&self) -> &Reg<CH_AL1_WRITE_ADDR_SPEC>

0x18 - Alias for channel 0 WRITE_ADDR register

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pub const fn ch_al1_trans_count_trig( &self, ) -> &Reg<CH_AL1_TRANS_COUNT_TRIG_SPEC>

0x1c - Alias for channel 0 TRANS_COUNT register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel.

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pub const fn ch_al2_ctrl(&self) -> &Reg<CH_AL2_CTRL_SPEC>

0x20 - DMA Channel 0 Control and Status

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pub const fn ch_al2_trans_count(&self) -> &Reg<CH_AL2_TRANS_COUNT_SPEC>

0x24 - Alias for channel 0 TRANS_COUNT register

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pub const fn ch_al2_read_addr(&self) -> &Reg<CH_AL2_READ_ADDR_SPEC>

0x28 - Alias for channel 0 READ_ADDR register

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pub const fn ch_al2_write_addr_trig(&self) -> &Reg<CH_AL2_WRITE_ADDR_TRIG_SPEC>

0x2c - Alias for channel 0 WRITE_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel.

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pub const fn ch_al3_ctrl(&self) -> &Reg<CH_AL3_CTRL_SPEC>

0x30 - DMA Channel 0 Control and Status

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pub const fn ch_al3_write_addr(&self) -> &Reg<CH_AL3_WRITE_ADDR_SPEC>

0x34 - Alias for channel 0 WRITE_ADDR register

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pub const fn ch_al3_trans_count(&self) -> &Reg<CH_AL3_TRANS_COUNT_SPEC>

0x38 - Alias for channel 0 TRANS_COUNT register

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pub const fn ch_al3_read_addr_trig(&self) -> &Reg<CH_AL3_READ_ADDR_TRIG_SPEC>

0x3c - Alias for channel 0 READ_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel.

Auto Trait Implementations§

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impl !Freeze for CH

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impl !RefUnwindSafe for CH

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impl Send for CH

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impl !Sync for CH

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impl Unpin for CH

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impl UnwindSafe for CH

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