Trait ReadTarget 

pub unsafe trait ReadTarget {
    type ReceivedWord;

    // Required methods
    fn rx_treq() -> Option<u8>;
    fn rx_address_count(&self) -> (u32, u32);
    fn rx_increment(&self) -> bool;
}

Trait which is implemented by anything that can be read via DMA.

Safety

The implementing type must be safe to use for DMA reads. This means:

• The range returned by rx_address_count must point to a valid address, and if rx_increment is true, count must fit into the allocated buffer.
• As long as no &mut self method is called on the implementing object:
  • rx_address_count must always return the same value, if called multiple times.
  • The memory specified by the pointer and size returned by rx_address_count must not be freed during the transfer it is used in as long as self is not dropped.

Required Associated Types

type ReceivedWord

Type which is transferred in a single DMA transfer.

Required Methods

fn rx_treq() -> Option<u8>

Returns the DREQ number for this data source (None for memory buffers).

fn rx_address_count(&self) -> (u32, u32)

Returns the address and the maximum number of words that can be transferred from this data source in a single DMA operation.

For peripherals, the count should likely be u32::MAX. If a data source implements EndlessReadTarget, it is suitable for infinite transfers from or to ring buffers. Note that ring buffers designated for endless transfers, but with a finite buffer size, should return the size of their individual buffers here.

Safety

This function has the same safety guarantees as ReadBuffer::read_buffer.

fn rx_increment(&self) -> bool

Returns whether the address shall be incremented after each transfer.

Dyn Compatibility

This trait is not dyn compatible.

In older versions of Rust, dyn compatibility was called "object safety", so this trait is not object safe.

Implementors

impl<B> ReadTarget for B

where B: ReadBuffer,

Safety: ReadBuffer and ReadTarget have the same safety requirements.

type ReceivedWord = <B as ReadBuffer>::Word

impl<D, P> ReadTarget for Spi<Enabled, D, P>

where D: SpiDevice, P: ValidSpiPinout<D>,

type ReceivedWord = u8

impl<D, P> ReadTarget for Spi<Enabled, D, P, 4>

where D: SpiDevice, P: ValidSpiPinout<D>,

type ReceivedWord = u8

impl<D, P> ReadTarget for Spi<Enabled, D, P, 5>

where D: SpiDevice, P: ValidSpiPinout<D>,

type ReceivedWord = u8

impl<D, P> ReadTarget for Spi<Enabled, D, P, 6>

where D: SpiDevice, P: ValidSpiPinout<D>,

type ReceivedWord = u8

impl<D, P> ReadTarget for Spi<Enabled, D, P, 7>

where D: SpiDevice, P: ValidSpiPinout<D>,

type ReceivedWord = u8

impl<D, P> ReadTarget for Spi<Enabled, D, P, 9>

where D: SpiDevice, P: ValidSpiPinout<D>,

type ReceivedWord = u16

impl<D, P> ReadTarget for Spi<Enabled, D, P, 10>

where D: SpiDevice, P: ValidSpiPinout<D>,

type ReceivedWord = u16

impl<D, P> ReadTarget for Spi<Enabled, D, P, 11>

where D: SpiDevice, P: ValidSpiPinout<D>,

type ReceivedWord = u16

impl<D, P> ReadTarget for Spi<Enabled, D, P, 12>

where D: SpiDevice, P: ValidSpiPinout<D>,

type ReceivedWord = u16

impl<D, P> ReadTarget for Spi<Enabled, D, P, 13>

where D: SpiDevice, P: ValidSpiPinout<D>,

type ReceivedWord = u16

impl<D, P> ReadTarget for Spi<Enabled, D, P, 14>

where D: SpiDevice, P: ValidSpiPinout<D>,

type ReceivedWord = u16

impl<D, P> ReadTarget for Spi<Enabled, D, P, 15>

where D: SpiDevice, P: ValidSpiPinout<D>,

type ReceivedWord = u16

impl<D, P> ReadTarget for Spi<Enabled, D, P, 16>

where D: SpiDevice, P: ValidSpiPinout<D>,

type ReceivedWord = u16

impl<D, P> ReadTarget for Reader<D, P>

where D: UartDevice, P: ValidUartPinout<D>,

type ReceivedWord = u8

impl<SM, RxSize> ReadTarget for Rx<SM, RxSize>

where SM: ValidStateMachine, RxSize: TransferSize,

type ReceivedWord = <RxSize as TransferSize>::Type

impl<Word> ReadTarget for DmaReadTarget<Word>

Safety: rx_address_count points to a register which is always a valid read target.

type ReceivedWord = Word