FifoWatermark

pico_engine_hal::uart

Enum FifoWatermark 

Source 
pub enum FifoWatermark {
    Bytes4,
    Bytes8,
    Bytes16,
    Bytes24,
    Bytes28,
}
Expand description

Rx/Tx FIFO Watermark

Determine the FIFO level that trigger DMA/Interrupt Default is Bytes16, see DS Table 423 and UARTIFLS Register Example of use: uart0.set_fifos(true); // Default is false uart0.set_rx_watermark(hal::uart::FifoWatermark::Bytes8); uart0.enable_rx_interrupt();

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Bytes4

Trigger when 4 bytes are (Rx: filled / Tx: available)

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Bytes8

Trigger when 8 bytes are (Rx: filled / Tx: available)

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Bytes16

Trigger when 16 bytes are (Rx: filled / Tx: available)

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Bytes24

Trigger when 24 bytes are (Rx: filled / Tx: available)

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Bytes28

Trigger when 28 bytes are (Rx: filled / Tx: available)

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