Struct SPI0 

pub struct SPI0 { /* private fields */ }

SPI0

Implementations

impl SPI0

pub const PTR: *const RegisterBlock = {0x40080000 as *const rp235x_hal::rp235x_pac::spi0::RegisterBlock}

Pointer to the register block

pub const fn ptr() -> *const RegisterBlock

Return the pointer to the register block

pub unsafe fn steal() -> SPI0

Steal an instance of this peripheral

Safety

Ensure that the new instance of the peripheral cannot be used in a way that may race with any existing instances, for example by only accessing read-only or write-only registers, or by consuming the original peripheral and using critical sections to coordinate access between multiple new instances.

Additionally, other software such as HALs may rely on only one peripheral instance existing to ensure memory safety; ensure no stolen instances are passed to such software.

Methods from Deref<Target = RegisterBlock>

pub fn sspcr0(&self) -> &Reg<SSPCR0_SPEC>

0x00 - Control register 0, SSPCR0 on page 3-4

pub fn sspcr1(&self) -> &Reg<SSPCR1_SPEC>

0x04 - Control register 1, SSPCR1 on page 3-5

pub fn sspdr(&self) -> &Reg<SSPDR_SPEC>

0x08 - Data register, SSPDR on page 3-6

pub fn sspsr(&self) -> &Reg<SSPSR_SPEC>

0x0c - Status register, SSPSR on page 3-7

pub fn sspcpsr(&self) -> &Reg<SSPCPSR_SPEC>

0x10 - Clock prescale register, SSPCPSR on page 3-8

pub fn sspimsc(&self) -> &Reg<SSPIMSC_SPEC>

0x14 - Interrupt mask set or clear register, SSPIMSC on page 3-9

pub fn sspris(&self) -> &Reg<SSPRIS_SPEC>

0x18 - Raw interrupt status register, SSPRIS on page 3-10

pub fn sspmis(&self) -> &Reg<SSPMIS_SPEC>

0x1c - Masked interrupt status register, SSPMIS on page 3-11

pub fn sspicr(&self) -> &Reg<SSPICR_SPEC>

0x20 - Interrupt clear register, SSPICR on page 3-11

pub fn sspdmacr(&self) -> &Reg<SSPDMACR_SPEC>

0x24 - DMA control register, SSPDMACR on page 3-12

pub fn sspperiphid0(&self) -> &Reg<SSPPERIPHID0_SPEC>

0xfe0 - Peripheral identification registers, SSPPeriphID0-3 on page 3-13

pub fn sspperiphid1(&self) -> &Reg<SSPPERIPHID1_SPEC>

0xfe4 - Peripheral identification registers, SSPPeriphID0-3 on page 3-13

pub fn sspperiphid2(&self) -> &Reg<SSPPERIPHID2_SPEC>

0xfe8 - Peripheral identification registers, SSPPeriphID0-3 on page 3-13

pub fn sspperiphid3(&self) -> &Reg<SSPPERIPHID3_SPEC>

0xfec - Peripheral identification registers, SSPPeriphID0-3 on page 3-13

pub fn ssppcellid0(&self) -> &Reg<SSPPCELLID0_SPEC>

0xff0 - PrimeCell identification registers, SSPPCellID0-3 on page 3-16

pub fn ssppcellid1(&self) -> &Reg<SSPPCELLID1_SPEC>

0xff4 - PrimeCell identification registers, SSPPCellID0-3 on page 3-16

pub fn ssppcellid2(&self) -> &Reg<SSPPCELLID2_SPEC>

0xff8 - PrimeCell identification registers, SSPPCellID0-3 on page 3-16

pub fn ssppcellid3(&self) -> &Reg<SSPPCELLID3_SPEC>

0xffc - PrimeCell identification registers, SSPPCellID0-3 on page 3-16

Trait Implementations

impl Debug for SPI0

fn fmt(&self, f: &mut Formatter<'_>) -> Result<(), Error>

Formats the value using the given formatter.

impl Deref for SPI0

type Target = RegisterBlock

The resulting type after dereferencing.

fn deref(&self) -> &<SPI0 as Deref>::Target

Dereferences the value.

impl SpiDevice for SPI0

const ID: usize = 0usize

Index of the peripheral.

fn tx_dreq() -> u8

The DREQ number for which TX DMA requests are triggered.

fn rx_dreq() -> u8

The DREQ number for which RX DMA requests are triggered.

impl Send for SPI0

impl ValidPinIdCs<SPI0> for Gpio1

impl ValidPinIdCs<SPI0> for Gpio17

impl ValidPinIdCs<SPI0> for Gpio21

impl ValidPinIdCs<SPI0> for Gpio5

impl ValidPinIdRx<SPI0> for Gpio0

impl ValidPinIdRx<SPI0> for Gpio16

impl ValidPinIdRx<SPI0> for Gpio20

impl ValidPinIdRx<SPI0> for Gpio4

impl ValidPinIdSck<SPI0> for Gpio18

impl ValidPinIdSck<SPI0> for Gpio2

impl ValidPinIdSck<SPI0> for Gpio22

impl ValidPinIdSck<SPI0> for Gpio6

impl ValidPinIdTx<SPI0> for Gpio19

impl ValidPinIdTx<SPI0> for Gpio23

impl ValidPinIdTx<SPI0> for Gpio3

impl ValidPinIdTx<SPI0> for Gpio7