Struct PIO2 

pub struct PIO2 { /* private fields */ }

Programmable IO block

Implementations

impl PIO2

pub const PTR: *const RegisterBlock = {0x50400000 as *const rp235x_hal::rp235x_pac::pio0::RegisterBlock}

Pointer to the register block

pub const fn ptr() -> *const RegisterBlock

Return the pointer to the register block

pub unsafe fn steal() -> PIO2

Steal an instance of this peripheral

Safety

Ensure that the new instance of the peripheral cannot be used in a way that may race with any existing instances, for example by only accessing read-only or write-only registers, or by consuming the original peripheral and using critical sections to coordinate access between multiple new instances.

Additionally, other software such as HALs may rely on only one peripheral instance existing to ensure memory safety; ensure no stolen instances are passed to such software.

Methods from Deref<Target = RegisterBlock>

pub fn ctrl(&self) -> &Reg<CTRL_SPEC>

0x00 - PIO control register

pub fn fstat(&self) -> &Reg<FSTAT_SPEC>

0x04 - FIFO status register

pub fn fdebug(&self) -> &Reg<FDEBUG_SPEC>

0x08 - FIFO debug register

pub fn flevel(&self) -> &Reg<FLEVEL_SPEC>

0x0c - FIFO levels

pub fn txf(&self, n: usize) -> &Reg<TXF_SPEC>

0x10..0x20 - Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.

pub fn txf_iter(&self) -> impl Iterator<Item = &Reg<TXF_SPEC>>

Iterator for array of: 0x10..0x20 - Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.

pub fn rxf(&self, n: usize) -> &Reg<RXF_SPEC>

0x20..0x30 - Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined.

pub fn rxf_iter(&self) -> impl Iterator<Item = &Reg<RXF_SPEC>>

Iterator for array of: 0x20..0x30 - Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined.

pub fn irq(&self) -> &Reg<IRQ_SPEC>

0x30 - State machine IRQ flags register. Write 1 to clear. There are eight state machine IRQ flags, which can be set, cleared, and waited on by the state machines. There’s no fixed association between flags and state machines – any state machine can use any flag. Any of the eight flags can be used for timing synchronisation between state machines, using IRQ and WAIT instructions. Any combination of the eight flags can also routed out to either of the two system-level interrupt requests, alongside FIFO status interrupts – see e.g. IRQ0_INTE.

pub fn irq_force(&self) -> &Reg<IRQ_FORCE_SPEC>

0x34 - Writing a 1 to each of these bits will forcibly assert the corresponding IRQ. Note this is different to the INTF register: writing here affects PIO internal state. INTF just asserts the processor-facing IRQ signal for testing ISRs, and is not visible to the state machines.

pub fn input_sync_bypass(&self) -> &Reg<INPUT_SYNC_BYPASS_SPEC>

0x38 - There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities. This increases input delay, and for fast synchronous IO (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this register corresponds to one GPIO. 0 -> input is synchronized (default) 1 -> synchronizer is bypassed If in doubt, leave this register as all zeroes.

pub fn dbg_padout(&self) -> &Reg<DBG_PADOUT_SPEC>

0x3c - Read to sample the pad output values PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0.

pub fn dbg_padoe(&self) -> &Reg<DBG_PADOE_SPEC>

0x40 - Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0.

pub fn dbg_cfginfo(&self) -> &Reg<DBG_CFGINFO_SPEC>

0x44 - The PIO hardware has some free parameters that may vary between chip products. These should be provided in the chip datasheet, but are also exposed here.

pub fn instr_mem(&self, n: usize) -> &Reg<INSTR_MEM_SPEC>

0x48..0xc8 - Write-only access to instruction memory location %s

pub fn instr_mem_iter(&self) -> impl Iterator<Item = &Reg<INSTR_MEM_SPEC>>

Iterator for array of: 0x48..0xc8 - Write-only access to instruction memory location %s

pub fn sm(&self, n: usize) -> &SM

0xc8..0x128 - Cluster SM%s, containing SM*_CLKDIV, SM*_EXECCTRL, SM*_SHIFTCTRL, SM*_ADDR, SM*_INSTR, SM*_PINCTRL

pub fn sm_iter(&self) -> impl Iterator<Item = &SM>

Iterator for array of: 0xc8..0x128 - Cluster SM%s, containing SM*_CLKDIV, SM*_EXECCTRL, SM*_SHIFTCTRL, SM*_ADDR, SM*_INSTR, SM*_PINCTRL

pub fn rxf0_putget(&self, n: usize) -> &Reg<RXF0_PUTGET_SPEC>

0x128..0x138 - Direct read/write access to entry %s of SM0’s RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set.

pub fn rxf0_putget_iter(&self) -> impl Iterator<Item = &Reg<RXF0_PUTGET_SPEC>>

Iterator for array of: 0x128..0x138 - Direct read/write access to entry %s of SM0’s RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set.

pub fn rxf1_putget(&self, n: usize) -> &Reg<RXF1_PUTGET_SPEC>

0x138..0x148 - Direct read/write access to entry %s of SM1’s RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set.

pub fn rxf1_putget_iter(&self) -> impl Iterator<Item = &Reg<RXF1_PUTGET_SPEC>>

Iterator for array of: 0x138..0x148 - Direct read/write access to entry %s of SM1’s RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set.

pub fn rxf2_putget(&self, n: usize) -> &Reg<RXF2_PUTGET_SPEC>

0x148..0x158 - Direct read/write access to entry %s of SM2’s RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set.

pub fn rxf2_putget_iter(&self) -> impl Iterator<Item = &Reg<RXF2_PUTGET_SPEC>>

Iterator for array of: 0x148..0x158 - Direct read/write access to entry %s of SM2’s RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set.

pub fn rxf3_putget(&self, n: usize) -> &Reg<RXF3_PUTGET_SPEC>

0x158..0x168 - Direct read/write access to entry %s of SM3’s RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set.

pub fn rxf3_putget_iter(&self) -> impl Iterator<Item = &Reg<RXF3_PUTGET_SPEC>>

Iterator for array of: 0x158..0x168 - Direct read/write access to entry %s of SM3’s RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set.

pub fn gpiobase(&self) -> &Reg<GPIOBASE_SPEC>

0x168 - Relocate GPIO 0 (from PIO’s point of view) in the system GPIO numbering, to access more than 32 GPIOs from PIO. Only the values 0 and 16 are supported (only bit 4 is writable).

pub fn intr(&self) -> &Reg<INTR_SPEC>

0x16c - Raw Interrupts

pub fn sm_irq(&self, n: usize) -> &SM_IRQ

0x170..0x188 - Cluster SM_IRQ%s, containing IRQ*_INTE, IRQ*_INTF, IRQ*_INTS

pub fn sm_irq_iter(&self) -> impl Iterator<Item = &SM_IRQ>

Iterator for array of: 0x170..0x188 - Cluster SM_IRQ%s, containing IRQ*_INTE, IRQ*_INTF, IRQ*_INTS

Trait Implementations

impl Debug for PIO2

fn fmt(&self, f: &mut Formatter<'_>) -> Result<(), Error>

Formats the value using the given formatter.

impl Deref for PIO2

type Target = RegisterBlock

The resulting type after dereferencing.

fn deref(&self) -> &<PIO2 as Deref>::Target

Dereferences the value.

impl Send for PIO2