Struct GLITCH_DETECTOR 

pub struct GLITCH_DETECTOR { /* private fields */ }

Glitch detector controls

Implementations

impl GLITCH_DETECTOR

pub const PTR: *const RegisterBlock = {0x40158000 as *const rp235x_hal::rp235x_pac::glitch_detector::RegisterBlock}

Pointer to the register block

pub const fn ptr() -> *const RegisterBlock

Return the pointer to the register block

pub unsafe fn steal() -> GLITCH_DETECTOR

Steal an instance of this peripheral

Safety

Ensure that the new instance of the peripheral cannot be used in a way that may race with any existing instances, for example by only accessing read-only or write-only registers, or by consuming the original peripheral and using critical sections to coordinate access between multiple new instances.

Additionally, other software such as HALs may rely on only one peripheral instance existing to ensure memory safety; ensure no stolen instances are passed to such software.

Methods from Deref<Target = RegisterBlock>

pub fn arm(&self) -> &Reg<ARM_SPEC>

0x00 - Forcibly arm the glitch detectors, if they are not already armed by OTP. When armed, any individual detector trigger will cause a restart of the switched core power domain’s power-on reset state machine. Glitch detector triggers are recorded accumulatively in TRIG_STATUS. If the system is reset by a glitch detector trigger, this is recorded in POWMAN_CHIP_RESET. This register is Secure read/write only.

pub fn disarm(&self) -> &Reg<DISARM_SPEC>

0x04 -

pub fn sensitivity(&self) -> &Reg<SENSITIVITY_SPEC>

0x08 - Adjust the sensitivity of glitch detectors to values other than their OTP-provided defaults. This register is Secure read/write only.

pub fn lock(&self) -> &Reg<LOCK_SPEC>

0x0c -

pub fn trig_status(&self) -> &Reg<TRIG_STATUS_SPEC>

0x10 - Set when a detector output triggers. Write-1-clear. (May immediately return high if the detector remains in a failed state. Detectors can only be cleared by a full reset of the switched core power domain.) This register is Secure read/write only.

pub fn trig_force(&self) -> &Reg<TRIG_FORCE_SPEC>

0x14 - Simulate the firing of one or more detectors. Writing ones to this register will set the matching bits in STATUS_TRIG. If the glitch detectors are currently armed, writing ones will also immediately reset the switched core power domain, and set the reset reason latches in POWMAN_CHIP_RESET to indicate a glitch detector resets. This register is Secure read/write only.

Trait Implementations

impl Debug for GLITCH_DETECTOR

fn fmt(&self, f: &mut Formatter<'_>) -> Result<(), Error>

Formats the value using the given formatter.

impl Deref for GLITCH_DETECTOR

type Target = RegisterBlock

The resulting type after dereferencing.

fn deref(&self) -> &<GLITCH_DETECTOR as Deref>::Target

Dereferences the value.

impl Send for GLITCH_DETECTOR