Struct DMA 

pub struct DMA { /* private fields */ }

DMA with separate read and write masters

Implementations

impl DMA

pub const PTR: *const RegisterBlock = {0x50000000 as *const rp235x_hal::rp235x_pac::dma::RegisterBlock}

Pointer to the register block

pub const fn ptr() -> *const RegisterBlock

Return the pointer to the register block

pub unsafe fn steal() -> DMA

Steal an instance of this peripheral

Safety

Ensure that the new instance of the peripheral cannot be used in a way that may race with any existing instances, for example by only accessing read-only or write-only registers, or by consuming the original peripheral and using critical sections to coordinate access between multiple new instances.

Additionally, other software such as HALs may rely on only one peripheral instance existing to ensure memory safety; ensure no stolen instances are passed to such software.

Methods from Deref<Target = RegisterBlock>

pub fn ch(&self, n: usize) -> &CH

0x00..0x400 - Cluster CH%s, containing CH?_READ_ADDR,CH??_READ_ADDR, CH?_WRITE_ADDR,CH??_WRITE_ADDR, CH?_TRANS_COUNT,CH??_TRANS_COUNT, CH?_CTRL_TRIG,CH??_CTRL_TRIG, CH?_AL1_CTRL,CH??_AL1_CTRL, CH?_AL1_READ_ADDR,CH??_AL1_READ_ADDR, CH?_AL1_WRITE_ADDR,CH??_AL1_WRITE_ADDR, CH?_AL1_TRANS_COUNT_TRIG,CH??_AL1_TRANS_COUNT_TRIG, CH?_AL2_CTRL,CH??_AL2_CTRL, CH?_AL2_TRANS_COUNT,CH??_AL2_TRANS_COUNT, CH?_AL2_READ_ADDR,CH??_AL2_READ_ADDR, CH?_AL2_WRITE_ADDR_TRIG,CH??_AL2_WRITE_ADDR_TRIG, CH?_AL3_CTRL,CH??_AL3_CTRL, CH?_AL3_WRITE_ADDR,CH??_AL3_WRITE_ADDR, CH?_AL3_TRANS_COUNT,CH??_AL3_TRANS_COUNT, CH?_AL3_READ_ADDR_TRIG,CH??_AL3_READ_ADDR_TRIG

pub fn ch_iter(&self) -> impl Iterator<Item = &CH>

Iterator for array of: 0x00..0x400 - Cluster CH%s, containing CH?_READ_ADDR,CH??_READ_ADDR, CH?_WRITE_ADDR,CH??_WRITE_ADDR, CH?_TRANS_COUNT,CH??_TRANS_COUNT, CH?_CTRL_TRIG,CH??_CTRL_TRIG, CH?_AL1_CTRL,CH??_AL1_CTRL, CH?_AL1_READ_ADDR,CH??_AL1_READ_ADDR, CH?_AL1_WRITE_ADDR,CH??_AL1_WRITE_ADDR, CH?_AL1_TRANS_COUNT_TRIG,CH??_AL1_TRANS_COUNT_TRIG, CH?_AL2_CTRL,CH??_AL2_CTRL, CH?_AL2_TRANS_COUNT,CH??_AL2_TRANS_COUNT, CH?_AL2_READ_ADDR,CH??_AL2_READ_ADDR, CH?_AL2_WRITE_ADDR_TRIG,CH??_AL2_WRITE_ADDR_TRIG, CH?_AL3_CTRL,CH??_AL3_CTRL, CH?_AL3_WRITE_ADDR,CH??_AL3_WRITE_ADDR, CH?_AL3_TRANS_COUNT,CH??_AL3_TRANS_COUNT, CH?_AL3_READ_ADDR_TRIG,CH??_AL3_READ_ADDR_TRIG

pub fn intr(&self) -> &Reg<INTR_SPEC>

0x400 - Interrupt Status (raw)

pub fn inte0(&self) -> &Reg<INTE0_SPEC>

0x404 - Interrupt Enables for IRQ 0

pub fn intf0(&self) -> &Reg<INTF0_SPEC>

0x408 - Force Interrupts

pub fn ints0(&self) -> &Reg<INTS0_SPEC>

0x40c - Interrupt Status for IRQ 0

pub fn intr1(&self) -> &Reg<INTR1_SPEC>

0x410 - Interrupt Status (raw)

pub fn inte1(&self) -> &Reg<INTE1_SPEC>

0x414 - Interrupt Enables for IRQ 1

pub fn intf1(&self) -> &Reg<INTF1_SPEC>

0x418 - Force Interrupts

pub fn ints1(&self) -> &Reg<INTS1_SPEC>

0x41c - Interrupt Status for IRQ 1

pub fn intr2(&self) -> &Reg<INTR2_SPEC>

0x420 - Interrupt Status (raw)

pub fn inte2(&self) -> &Reg<INTE2_SPEC>

0x424 - Interrupt Enables for IRQ 2

pub fn intf2(&self) -> &Reg<INTF2_SPEC>

0x428 - Force Interrupts

pub fn ints2(&self) -> &Reg<INTS2_SPEC>

0x42c - Interrupt Status for IRQ 2

pub fn intr3(&self) -> &Reg<INTR3_SPEC>

0x430 - Interrupt Status (raw)

pub fn inte3(&self) -> &Reg<INTE3_SPEC>

0x434 - Interrupt Enables for IRQ 3

pub fn intf3(&self) -> &Reg<INTF3_SPEC>

0x438 - Force Interrupts

pub fn ints3(&self) -> &Reg<INTS3_SPEC>

0x43c - Interrupt Status for IRQ 3

pub fn timer0(&self) -> &Reg<TIMER0_SPEC>

0x440 - Pacing (X/Y) fractional timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.

pub fn timer1(&self) -> &Reg<TIMER1_SPEC>

0x444 - Pacing (X/Y) fractional timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.

pub fn timer2(&self) -> &Reg<TIMER2_SPEC>

0x448 - Pacing (X/Y) fractional timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.

pub fn timer3(&self) -> &Reg<TIMER3_SPEC>

0x44c - Pacing (X/Y) fractional timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.

pub fn multi_chan_trigger(&self) -> &Reg<MULTI_CHAN_TRIGGER_SPEC>

0x450 - Trigger one or more channels simultaneously

pub fn sniff_ctrl(&self) -> &Reg<SNIFF_CTRL_SPEC>

0x454 - Sniffer Control

pub fn sniff_data(&self) -> &Reg<SNIFF_DATA_SPEC>

0x458 - Data accumulator for sniff hardware

pub fn fifo_levels(&self) -> &Reg<FIFO_LEVELS_SPEC>

0x460 - Debug RAF, WAF, TDF levels

pub fn chan_abort(&self) -> &Reg<CHAN_ABORT_SPEC>

0x464 - Abort an in-progress transfer sequence on one or more channels

pub fn n_channels(&self) -> &Reg<N_CHANNELS_SPEC>

0x468 - The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area.

pub fn seccfg_ch0(&self) -> &Reg<SECCFG_CH0_SPEC>

0x480 - Security configuration for channel 0. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context.

pub fn seccfg_ch1(&self) -> &Reg<SECCFG_CH1_SPEC>

0x484 - Security configuration for channel 1. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context.

pub fn seccfg_ch2(&self) -> &Reg<SECCFG_CH2_SPEC>

0x488 - Security configuration for channel 2. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context.

pub fn seccfg_ch3(&self) -> &Reg<SECCFG_CH3_SPEC>

0x48c - Security configuration for channel 3. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context.

pub fn seccfg_ch4(&self) -> &Reg<SECCFG_CH4_SPEC>

0x490 - Security configuration for channel 4. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context.

pub fn seccfg_ch5(&self) -> &Reg<SECCFG_CH5_SPEC>

0x494 - Security configuration for channel 5. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context.

pub fn seccfg_ch6(&self) -> &Reg<SECCFG_CH6_SPEC>

0x498 - Security configuration for channel 6. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context.

pub fn seccfg_ch7(&self) -> &Reg<SECCFG_CH7_SPEC>

0x49c - Security configuration for channel 7. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context.

pub fn seccfg_ch8(&self) -> &Reg<SECCFG_CH8_SPEC>

0x4a0 - Security configuration for channel 8. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context.

pub fn seccfg_ch9(&self) -> &Reg<SECCFG_CH9_SPEC>

0x4a4 - Security configuration for channel 9. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context.

pub fn seccfg_ch10(&self) -> &Reg<SECCFG_CH10_SPEC>

0x4a8 - Security configuration for channel 10. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context.

pub fn seccfg_ch11(&self) -> &Reg<SECCFG_CH11_SPEC>

0x4ac - Security configuration for channel 11. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context.

pub fn seccfg_ch12(&self) -> &Reg<SECCFG_CH12_SPEC>

0x4b0 - Security configuration for channel 12. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context.

pub fn seccfg_ch13(&self) -> &Reg<SECCFG_CH13_SPEC>

0x4b4 - Security configuration for channel 13. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context.

pub fn seccfg_ch14(&self) -> &Reg<SECCFG_CH14_SPEC>

0x4b8 - Security configuration for channel 14. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context.

pub fn seccfg_ch15(&self) -> &Reg<SECCFG_CH15_SPEC>

0x4bc - Security configuration for channel 15. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context.

pub fn seccfg_irq0(&self) -> &Reg<SECCFG_IRQ0_SPEC>

0x4c0 - Security configuration for IRQ 0. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags.

pub fn seccfg_irq1(&self) -> &Reg<SECCFG_IRQ1_SPEC>

0x4c4 - Security configuration for IRQ 1. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags.

pub fn seccfg_irq2(&self) -> &Reg<SECCFG_IRQ2_SPEC>

0x4c8 - Security configuration for IRQ 2. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags.

pub fn seccfg_irq3(&self) -> &Reg<SECCFG_IRQ3_SPEC>

0x4cc - Security configuration for IRQ 3. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags.

pub fn seccfg_misc(&self) -> &Reg<SECCFG_MISC_SPEC>

0x4d0 - Miscellaneous security configuration

pub fn mpu_ctrl(&self) -> &Reg<MPU_CTRL_SPEC>

0x500 - Control register for DMA MPU. Accessible only from a Privileged context.

pub fn mpu_bar0(&self) -> &Reg<MPU_BAR0_SPEC>

0x504 - Base address register for MPU region 0. Writable only from a Secure, Privileged context.

pub fn mpu_lar0(&self) -> &Reg<MPU_LAR0_SPEC>

0x508 - Limit address register for MPU region 0. Writable only from a Secure, Privileged context, with the exception of the P bit.

pub fn mpu_bar1(&self) -> &Reg<MPU_BAR1_SPEC>

0x50c - Base address register for MPU region 1. Writable only from a Secure, Privileged context.

pub fn mpu_lar1(&self) -> &Reg<MPU_LAR1_SPEC>

0x510 - Limit address register for MPU region 1. Writable only from a Secure, Privileged context, with the exception of the P bit.

pub fn mpu_bar2(&self) -> &Reg<MPU_BAR2_SPEC>

0x514 - Base address register for MPU region 2. Writable only from a Secure, Privileged context.

pub fn mpu_lar2(&self) -> &Reg<MPU_LAR2_SPEC>

0x518 - Limit address register for MPU region 2. Writable only from a Secure, Privileged context, with the exception of the P bit.

pub fn mpu_bar3(&self) -> &Reg<MPU_BAR3_SPEC>

0x51c - Base address register for MPU region 3. Writable only from a Secure, Privileged context.

pub fn mpu_lar3(&self) -> &Reg<MPU_LAR3_SPEC>

0x520 - Limit address register for MPU region 3. Writable only from a Secure, Privileged context, with the exception of the P bit.

pub fn mpu_bar4(&self) -> &Reg<MPU_BAR4_SPEC>

0x524 - Base address register for MPU region 4. Writable only from a Secure, Privileged context.

pub fn mpu_lar4(&self) -> &Reg<MPU_LAR4_SPEC>

0x528 - Limit address register for MPU region 4. Writable only from a Secure, Privileged context, with the exception of the P bit.

pub fn mpu_bar5(&self) -> &Reg<MPU_BAR5_SPEC>

0x52c - Base address register for MPU region 5. Writable only from a Secure, Privileged context.

pub fn mpu_lar5(&self) -> &Reg<MPU_LAR5_SPEC>

0x530 - Limit address register for MPU region 5. Writable only from a Secure, Privileged context, with the exception of the P bit.

pub fn mpu_bar6(&self) -> &Reg<MPU_BAR6_SPEC>

0x534 - Base address register for MPU region 6. Writable only from a Secure, Privileged context.

pub fn mpu_lar6(&self) -> &Reg<MPU_LAR6_SPEC>

0x538 - Limit address register for MPU region 6. Writable only from a Secure, Privileged context, with the exception of the P bit.

pub fn mpu_bar7(&self) -> &Reg<MPU_BAR7_SPEC>

0x53c - Base address register for MPU region 7. Writable only from a Secure, Privileged context.

pub fn mpu_lar7(&self) -> &Reg<MPU_LAR7_SPEC>

0x540 - Limit address register for MPU region 7. Writable only from a Secure, Privileged context, with the exception of the P bit.

pub fn ch0_dbg_ctdreq(&self) -> &Reg<CH0_DBG_CTDREQ_SPEC>

0x800 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.

pub fn ch0_dbg_tcr(&self) -> &Reg<CH0_DBG_TCR_SPEC>

0x804 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer

pub fn ch1_dbg_ctdreq(&self) -> &Reg<CH1_DBG_CTDREQ_SPEC>

0x840 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.

pub fn ch1_dbg_tcr(&self) -> &Reg<CH1_DBG_TCR_SPEC>

0x844 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer

pub fn ch2_dbg_ctdreq(&self) -> &Reg<CH2_DBG_CTDREQ_SPEC>

0x880 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.

pub fn ch2_dbg_tcr(&self) -> &Reg<CH2_DBG_TCR_SPEC>

0x884 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer

pub fn ch3_dbg_ctdreq(&self) -> &Reg<CH3_DBG_CTDREQ_SPEC>

0x8c0 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.

pub fn ch3_dbg_tcr(&self) -> &Reg<CH3_DBG_TCR_SPEC>

0x8c4 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer

pub fn ch4_dbg_ctdreq(&self) -> &Reg<CH4_DBG_CTDREQ_SPEC>

0x900 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.

pub fn ch4_dbg_tcr(&self) -> &Reg<CH4_DBG_TCR_SPEC>

0x904 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer

pub fn ch5_dbg_ctdreq(&self) -> &Reg<CH5_DBG_CTDREQ_SPEC>

0x940 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.

pub fn ch5_dbg_tcr(&self) -> &Reg<CH5_DBG_TCR_SPEC>

0x944 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer

pub fn ch6_dbg_ctdreq(&self) -> &Reg<CH6_DBG_CTDREQ_SPEC>

0x980 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.

pub fn ch6_dbg_tcr(&self) -> &Reg<CH6_DBG_TCR_SPEC>

0x984 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer

pub fn ch7_dbg_ctdreq(&self) -> &Reg<CH7_DBG_CTDREQ_SPEC>

0x9c0 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.

pub fn ch7_dbg_tcr(&self) -> &Reg<CH7_DBG_TCR_SPEC>

0x9c4 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer

pub fn ch8_dbg_ctdreq(&self) -> &Reg<CH8_DBG_CTDREQ_SPEC>

0xa00 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.

pub fn ch8_dbg_tcr(&self) -> &Reg<CH8_DBG_TCR_SPEC>

0xa04 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer

pub fn ch9_dbg_ctdreq(&self) -> &Reg<CH9_DBG_CTDREQ_SPEC>

0xa40 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.

pub fn ch9_dbg_tcr(&self) -> &Reg<CH9_DBG_TCR_SPEC>

0xa44 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer

pub fn ch10_dbg_ctdreq(&self) -> &Reg<CH10_DBG_CTDREQ_SPEC>

0xa80 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.

pub fn ch10_dbg_tcr(&self) -> &Reg<CH10_DBG_TCR_SPEC>

0xa84 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer

pub fn ch11_dbg_ctdreq(&self) -> &Reg<CH11_DBG_CTDREQ_SPEC>

0xac0 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.

pub fn ch11_dbg_tcr(&self) -> &Reg<CH11_DBG_TCR_SPEC>

0xac4 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer

pub fn ch12_dbg_ctdreq(&self) -> &Reg<CH12_DBG_CTDREQ_SPEC>

0xb00 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.

pub fn ch12_dbg_tcr(&self) -> &Reg<CH12_DBG_TCR_SPEC>

0xb04 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer

pub fn ch13_dbg_ctdreq(&self) -> &Reg<CH13_DBG_CTDREQ_SPEC>

0xb40 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.

pub fn ch13_dbg_tcr(&self) -> &Reg<CH13_DBG_TCR_SPEC>

0xb44 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer

pub fn ch14_dbg_ctdreq(&self) -> &Reg<CH14_DBG_CTDREQ_SPEC>

0xb80 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.

pub fn ch14_dbg_tcr(&self) -> &Reg<CH14_DBG_TCR_SPEC>

0xb84 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer

pub fn ch15_dbg_ctdreq(&self) -> &Reg<CH15_DBG_CTDREQ_SPEC>

0xbc0 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.

pub fn ch15_dbg_tcr(&self) -> &Reg<CH15_DBG_TCR_SPEC>

0xbc4 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer

Trait Implementations

impl DMAExt for DMA

fn split(self, resets: &mut RESETS) -> Channels

Splits the DMA unit into its individual channels.

fn dyn_split(self, resets: &mut RESETS) -> DynChannels

Splits the DMA unit into its individual channels with runtime ownership

impl Debug for DMA

fn fmt(&self, f: &mut Formatter<'_>) -> Result<(), Error>

Formats the value using the given formatter.

impl Deref for DMA

type Target = RegisterBlock

The resulting type after dereferencing.

fn deref(&self) -> &<DMA as Deref>::Target

Dereferences the value.

impl Send for DMA