Struct RegisterBlock 

pub struct RegisterBlock { /* private fields */ }

Register block

Implementations

impl RegisterBlock

pub const fn ctrl(&self) -> &Reg<CTRL_SPEC>

0x00 - Ring Oscillator control

pub const fn freqa(&self) -> &Reg<FREQA_SPEC>

0x04 - The FREQA & FREQB registers control the frequency by controlling the drive strength of each stage The drive strength has 4 levels determined by the number of bits set Increasing the number of bits set increases the drive strength and increases the oscillation frequency 0 bits set is the default drive strength 1 bit set doubles the drive strength 2 bits set triples drive strength 3 bits set quadruples drive strength For frequency randomisation set both DS0_RANDOM=1 & DS1_RANDOM=1

pub const fn freqb(&self) -> &Reg<FREQB_SPEC>

0x08 - For a detailed description see freqa register

pub const fn random(&self) -> &Reg<RANDOM_SPEC>

0x0c - Loads a value to the LFSR randomiser

pub const fn dormant(&self) -> &Reg<DORMANT_SPEC>

0x10 - Ring Oscillator pause control

pub const fn div(&self) -> &Reg<DIV_SPEC>

0x14 - Controls the output divider

pub const fn phase(&self) -> &Reg<PHASE_SPEC>

0x18 - Controls the phase shifted output

pub const fn status(&self) -> &Reg<STATUS_SPEC>

0x1c - Ring Oscillator Status

pub const fn randombit(&self) -> &Reg<RANDOMBIT_SPEC>

0x20 - This just reads the state of the oscillator output so randomness is compromised if the ring oscillator is stopped or run at a harmonic of the bus frequency

pub const fn count(&self) -> &Reg<COUNT_SPEC>

0x24 - A down counter running at the ROSC frequency which counts to zero and stops. To start the counter write a non-zero value. Can be used for short software pauses when setting up time sensitive hardware.