Struct RegisterBlock

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pub struct RegisterBlock { /* private fields */ }

Expand description

Register block

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impl RegisterBlock

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pub const fn cs(&self) -> &Reg<CS_SPEC>

0x00 - Control and Status GENERAL CONSTRAINTS: Reference clock frequency min=5MHz, max=800MHz Feedback divider min=16, max=320 VCO frequency min=750MHz, max=1600MHz

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pub const fn pwr(&self) -> &Reg<PWR_SPEC>

0x04 - Controls the PLL power modes.

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pub const fn fbdiv_int(&self) -> &Reg<FBDIV_INT_SPEC>

0x08 - Feedback divisor (note: this PLL does not support fractional division)

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pub const fn prim(&self) -> &Reg<PRIM_SPEC>

0x0c - Controls the PLL post dividers for the primary output (note: this PLL does not have a secondary output) the primary output is driven from VCO divided by postdiv1*postdiv2

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pub const fn intr(&self) -> &Reg<INTR_SPEC>

0x10 - Raw Interrupts

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pub const fn inte(&self) -> &Reg<INTE_SPEC>

0x14 - Interrupt Enable

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pub const fn intf(&self) -> &Reg<INTF_SPEC>

0x18 - Interrupt Force

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pub const fn ints(&self) -> &Reg<INTS_SPEC>

0x1c - Interrupt status after masking & forcing

Auto Trait Implementations§

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impl UnwindSafe for RegisterBlock

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impl<T> Any for T
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impl<Choices> CoproductSubsetter<CNil, HNil> for Choices

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type Remainder = Choices

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Calls U::from(self).

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Converts self into a Left variant of Either<Self, Self> if into_left is true. Converts self into a Right variant of Either<Self, Self> otherwise. Read more

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