Struct TIMER0_SPEC 

pub struct TIMER0_SPEC;

Control whether debugger, DMA, core 0 and core 1 can access TIMER0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.

You can read this register and get timer0::R. You can reset, write, write_with_zero this register using timer0::W. You can also modify this register. See API.

Trait Implementations

impl RegisterSpec for TIMER0_SPEC

type Ux = u32

Raw register type (u8, u16, u32, …).

impl Resettable for TIMER0_SPEC

reset() method sets TIMER0 to value 0xfc

const RESET_VALUE: u32 = 252u32

Reset value of the register.

fn reset_value() -> Self::Ux

Reset value of the register.

impl Writable for TIMER0_SPEC

write(|w| ..) method takes timer0::W writer structure

const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0u32

Specifies the register bits that are not changed if you pass 1 and are changed if you pass 0

const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0u32

Specifies the register bits that are not changed if you pass 0 and are changed if you pass 1

type Safety = Unsafe

Is it safe to write any bits to register

impl Readable for TIMER0_SPEC

read() method returns timer0::R reader structure