Trait WriteTarget 

pub unsafe trait WriteTarget {
    type TransmittedWord;

    // Required methods
    fn tx_treq() -> Option<u8>;
    fn tx_address_count(&mut self) -> (u32, u32);
    fn tx_increment(&self) -> bool;
}

Trait which is implemented by anything that can be written via DMA.

Safety

The implementing type must be safe to use for DMA writes. This means:

• The range returned by tx_address_count must point to a valid address, and if tx_increment is true, count must fit into the allocated buffer.
• As long as no other &mut self method is called on the implementing object:
  • tx_address_count must always return the same value, if called multiple times.
  • The memory specified by the pointer and size returned by tx_address_count must not be freed during the transfer it is used in as long as self is not dropped.

Required Associated Types

type TransmittedWord

Type which is transferred in a single DMA transfer.

Required Methods

fn tx_treq() -> Option<u8>

Returns the DREQ number for this data sink (None for memory buffers).

fn tx_address_count(&mut self) -> (u32, u32)

Returns the address and the maximum number of words that can be transferred from this data source in a single DMA operation.

See ReadTarget::rx_address_count for a complete description of the semantics of this function.

fn tx_increment(&self) -> bool

Returns whether the address shall be incremented after each transfer.

Dyn Compatibility

This trait is not dyn compatible.

In older versions of Rust, dyn compatibility was called "object safety", so this trait is not object safe.

Implementors

impl<B> WriteTarget for B

where B: WriteBuffer,

Safety: WriteBuffer and WriteTarget have the same safety requirements.

type TransmittedWord = <B as WriteBuffer>::Word

impl<D, P> WriteTarget for Spi<Enabled, D, P>

where D: SpiDevice, P: ValidSpiPinout<D>,

type TransmittedWord = u8

impl<D, P> WriteTarget for Spi<Enabled, D, P, 4>

where D: SpiDevice, P: ValidSpiPinout<D>,

type TransmittedWord = u8

impl<D, P> WriteTarget for Spi<Enabled, D, P, 5>

where D: SpiDevice, P: ValidSpiPinout<D>,

type TransmittedWord = u8

impl<D, P> WriteTarget for Spi<Enabled, D, P, 6>

where D: SpiDevice, P: ValidSpiPinout<D>,

type TransmittedWord = u8

impl<D, P> WriteTarget for Spi<Enabled, D, P, 7>

where D: SpiDevice, P: ValidSpiPinout<D>,

type TransmittedWord = u8

impl<D, P> WriteTarget for Spi<Enabled, D, P, 9>

where D: SpiDevice, P: ValidSpiPinout<D>,

type TransmittedWord = u16

impl<D, P> WriteTarget for Spi<Enabled, D, P, 10>

where D: SpiDevice, P: ValidSpiPinout<D>,

type TransmittedWord = u16

impl<D, P> WriteTarget for Spi<Enabled, D, P, 11>

where D: SpiDevice, P: ValidSpiPinout<D>,

type TransmittedWord = u16

impl<D, P> WriteTarget for Spi<Enabled, D, P, 12>

where D: SpiDevice, P: ValidSpiPinout<D>,

type TransmittedWord = u16

impl<D, P> WriteTarget for Spi<Enabled, D, P, 13>

where D: SpiDevice, P: ValidSpiPinout<D>,

type TransmittedWord = u16

impl<D, P> WriteTarget for Spi<Enabled, D, P, 14>

where D: SpiDevice, P: ValidSpiPinout<D>,

type TransmittedWord = u16

impl<D, P> WriteTarget for Spi<Enabled, D, P, 15>

where D: SpiDevice, P: ValidSpiPinout<D>,

type TransmittedWord = u16

impl<D, P> WriteTarget for Spi<Enabled, D, P, 16>

where D: SpiDevice, P: ValidSpiPinout<D>,

type TransmittedWord = u16

impl<D, P> WriteTarget for Writer<D, P>

where D: UartDevice, P: ValidUartPinout<D>,

type TransmittedWord = u8

impl<S, M> WriteTarget for SliceDmaWriteCc<S, M>

where S: SliceId, M: ValidSliceMode<S>,

Safety: tx_address_count points to a register which is always a valid write target.

type TransmittedWord = CcFormat

impl<S, M> WriteTarget for SliceDmaWriteTop<S, M>

where S: SliceId, M: ValidSliceMode<S>,

Safety: tx_address_count points to a register which is always a valid write target.

type TransmittedWord = TopFormat

impl<SM, TxSize> WriteTarget for Tx<SM, TxSize>

where SM: ValidStateMachine, TxSize: TransferSize,

type TransmittedWord = <TxSize as TransferSize>::Type