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RegisterBlock

pic32_hal::pac::adc

Struct RegisterBlock 

Source 
pub struct RegisterBlock {
Show 36 fields
    pub con1: Reg<CON1_SPEC>,
    pub con1clr: Reg<CON1CLR_SPEC>,
    pub con1set: Reg<CON1SET_SPEC>,
    pub con1inv: Reg<CON1INV_SPEC>,
    pub con2: Reg<CON2_SPEC>,
    pub con2clr: Reg<CON2CLR_SPEC>,
    pub con2set: Reg<CON2SET_SPEC>,
    pub con2inv: Reg<CON2INV_SPEC>,
    pub con3: Reg<CON3_SPEC>,
    pub con3clr: Reg<CON3CLR_SPEC>,
    pub con3set: Reg<CON3SET_SPEC>,
    pub con3inv: Reg<CON3INV_SPEC>,
    pub chs: Reg<CHS_SPEC>,
    pub chsclr: Reg<CHSCLR_SPEC>,
    pub chsset: Reg<CHSSET_SPEC>,
    pub chsinv: Reg<CHSINV_SPEC>,
    pub cssl: Reg<CSSL_SPEC>,
    pub csslclr: Reg<CSSLCLR_SPEC>,
    pub csslset: Reg<CSSLSET_SPEC>,
    pub csslinv: Reg<CSSLINV_SPEC>,
    pub buf0: Reg<BUF0_SPEC>,
    pub buf1: Reg<BUF1_SPEC>,
    pub buf2: Reg<BUF2_SPEC>,
    pub buf3: Reg<BUF3_SPEC>,
    pub buf4: Reg<BUF4_SPEC>,
    pub buf5: Reg<BUF5_SPEC>,
    pub buf6: Reg<BUF6_SPEC>,
    pub buf7: Reg<BUF7_SPEC>,
    pub buf8: Reg<BUF8_SPEC>,
    pub buf9: Reg<BUF9_SPEC>,
    pub bufa: Reg<BUFA_SPEC>,
    pub bufb: Reg<BUFB_SPEC>,
    pub bufc: Reg<BUFC_SPEC>,
    pub bufd: Reg<BUFD_SPEC>,
    pub bufe: Reg<BUFE_SPEC>,
    pub buff: Reg<BUFF_SPEC>,
    /* private fields */

}
Expand description

Register block

Fields§

§con1: Reg<CON1_SPEC>

0x00 - AD1CON1 register

§con1clr: Reg<CON1CLR_SPEC>

0x04 - AD1CON1CLR register

§con1set: Reg<CON1SET_SPEC>

0x08 - AD1CON1SET register

§con1inv: Reg<CON1INV_SPEC>

0x0c - AD1CON1INV register

§con2: Reg<CON2_SPEC>

0x10 - AD1CON2 register

§con2clr: Reg<CON2CLR_SPEC>

0x14 - AD1CON2CLR register

§con2set: Reg<CON2SET_SPEC>

0x18 - AD1CON2SET register

§con2inv: Reg<CON2INV_SPEC>

0x1c - AD1CON2INV register

§con3: Reg<CON3_SPEC>

0x20 - AD1CON3 register

§con3clr: Reg<CON3CLR_SPEC>

0x24 - AD1CON3CLR register

§con3set: Reg<CON3SET_SPEC>

0x28 - AD1CON3SET register

§con3inv: Reg<CON3INV_SPEC>

0x2c - AD1CON3INV register

§chs: Reg<CHS_SPEC>

0x40 - AD1CHS register

§chsclr: Reg<CHSCLR_SPEC>

0x44 - AD1CHSCLR register

§chsset: Reg<CHSSET_SPEC>

0x48 - AD1CHSSET register

§chsinv: Reg<CHSINV_SPEC>

0x4c - AD1CHSINV register

§cssl: Reg<CSSL_SPEC>

0x50 - AD1CSSL register

§csslclr: Reg<CSSLCLR_SPEC>

0x54 - AD1CSSLCLR register

§csslset: Reg<CSSLSET_SPEC>

0x58 - AD1CSSLSET register

§csslinv: Reg<CSSLINV_SPEC>

0x5c - AD1CSSLINV register

§buf0: Reg<BUF0_SPEC>

0x70 - ADC1BUF0 register

§buf1: Reg<BUF1_SPEC>

0x80 - ADC1BUF1 register

§buf2: Reg<BUF2_SPEC>

0x90 - ADC1BUF2 register

§buf3: Reg<BUF3_SPEC>

0xa0 - ADC1BUF3 register

§buf4: Reg<BUF4_SPEC>

0xb0 - ADC1BUF4 register

§buf5: Reg<BUF5_SPEC>

0xc0 - ADC1BUF5 register

§buf6: Reg<BUF6_SPEC>

0xd0 - ADC1BUF6 register

§buf7: Reg<BUF7_SPEC>

0xe0 - ADC1BUF7 register

§buf8: Reg<BUF8_SPEC>

0xf0 - ADC1BUF8 register

§buf9: Reg<BUF9_SPEC>

0x100 - ADC1BUF9 register

§bufa: Reg<BUFA_SPEC>

0x110 - ADC1BUFA register

§bufb: Reg<BUFB_SPEC>

0x120 - ADC1BUFB register

§bufc: Reg<BUFC_SPEC>

0x130 - ADC1BUFC register

§bufd: Reg<BUFD_SPEC>

0x140 - ADC1BUFD register

§bufe: Reg<BUFE_SPEC>

0x150 - ADC1BUFE register

§buff: Reg<BUFF_SPEC>

0x160 - ADC1BUFF register

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