Enum InterruptSource 

#[repr(u8)]
pub enum InterruptSource {
    CORE_TIMER = 0,
    CORE_SOFTWARE_0 = 1,
    CORE_SOFTWARE_1 = 2,
    EXTERNAL_0 = 3,
    TIMER_1 = 4,
    INPUT_CAPTURE_ERROR_1 = 5,
    INPUT_CAPTURE_1 = 6,
    OUTPUT_COMPARE_1 = 7,
    EXTERNAL_1 = 8,
    TIMER_2 = 9,
    INPUT_CAPTURE_ERROR_2 = 10,
    INPUT_CAPTURE_2 = 11,
    OUTPUT_COMPARE_2 = 12,
    EXTERNAL_2 = 13,
    TIMER_3 = 14,
    INPUT_CAPTURE_ERROR_3 = 15,
    INPUT_CAPTURE_3 = 16,
    OUTPUT_COMPARE_3 = 17,
    EXTERNAL_3 = 18,
    TIMER_4 = 19,
    INPUT_CAPTURE_ERROR_4 = 20,
    INPUT_CAPTURE_4 = 21,
    OUTPUT_COMPARE_4 = 22,
    EXTERNAL_4 = 23,
    TIMER_5 = 24,
    INPUT_CAPTURE_ERROR_5 = 25,
    INPUT_CAPTURE_5 = 26,
    OUTPUT_COMPARE_5 = 27,
    ADC = 28,
    FAIL_SAFE_MONITOR = 29,
    RTCC = 30,
    FLASH_CONTROL = 31,
    COMPARATOR_1 = 32,
    COMPARATOR_2 = 33,
    COMPARATOR_3 = 34,
    USB = 35,
    SPI1_ERR = 36,
    SPI1_RX = 37,
    SPI1_TX = 38,
    UART1_ERR = 39,
    UART1_RX = 40,
    UART1_TX = 41,
    I2C1_BUS = 42,
    I2C1_SLAVE = 43,
    I2C1_MASTER = 44,
    CHANGE_NOTICE_A = 45,
    CHANGE_NOTICE_B = 46,
    CHANGE_NOTICE_C = 47,
    PMP = 48,
    PMP_ERROR = 49,
    SPI2_ERR = 50,
    SPI2_RX = 51,
    SPI2_TX = 52,
    UART2_ERR = 53,
    UART2_RX = 54,
    UART2_TX = 55,
    I2C2_BUS = 56,
    I2C2_SLAVE = 57,
    I2C2_MASTER = 58,
    CTMU = 59,
    DMA0 = 60,
    DMA1 = 61,
    DMA2 = 62,
    DMA3 = 63,
}

Interrupt source (from PAC)

Multiple interrupt sources can share a single interrupt vector. Enumeration of all the interrupt sources

Variants

CORE_TIMER = 0

Core Timer

CORE_SOFTWARE_0 = 1

Core Software 0

CORE_SOFTWARE_1 = 2

Core Software 1

EXTERNAL_0 = 3

Ext INT 0

TIMER_1 = 4

Timer 1

INPUT_CAPTURE_ERROR_1 = 5

Input Capature 1 Error

INPUT_CAPTURE_1 = 6

Input Capture 1

OUTPUT_COMPARE_1 = 7

Output Compare 1

EXTERNAL_1 = 8

Ext INT 1

TIMER_2 = 9

Timer 2

INPUT_CAPTURE_ERROR_2 = 10

Input Capture 2 Error

INPUT_CAPTURE_2 = 11

Input Capture 2

OUTPUT_COMPARE_2 = 12

Output Compare 2

EXTERNAL_2 = 13

External INT 2

TIMER_3 = 14

Timer 3

INPUT_CAPTURE_ERROR_3 = 15

Input Capture 3 Error

INPUT_CAPTURE_3 = 16

Input Capture 3

OUTPUT_COMPARE_3 = 17

Output Compare 3

EXTERNAL_3 = 18

Ext INT 3

TIMER_4 = 19

Timer 4

INPUT_CAPTURE_ERROR_4 = 20

Input Capture 4 Error

INPUT_CAPTURE_4 = 21

Input Capture 4

OUTPUT_COMPARE_4 = 22

Output Compare 4

EXTERNAL_4 = 23

Ext INT 4

TIMER_5 = 24

Timer 5

INPUT_CAPTURE_ERROR_5 = 25

Input Capture 5 Error

INPUT_CAPTURE_5 = 26

Input Capture 5

OUTPUT_COMPARE_5 = 27

Output Compare 5

ADC = 28

ADC1 Convert Done

FAIL_SAFE_MONITOR = 29

Fail Safe Clock Monitor

RTCC = 30

Real Time Clock Calendar

FLASH_CONTROL = 31

COMPARATOR_1 = 32

Comparator 1

COMPARATOR_2 = 33

Comparator 2

COMPARATOR_3 = 34

Comparator 3

USB = 35

USB

SPI1_ERR = 36

SPI1 Fault

SPI1_RX = 37

SPI1 Receive Done

SPI1_TX = 38

SPI1 Transmit Done

UART1_ERR = 39

UART1 Error

UART1_RX = 40

UART1 Receiver

UART1_TX = 41

UART1 Trasmitter

I2C1_BUS = 42

I2C1 Bus Collision Event

I2C1_SLAVE = 43

I2C1 Slave Event

I2C1_MASTER = 44

I2C1 Master Event

CHANGE_NOTICE_A = 45

Part A Change Notice

CHANGE_NOTICE_B = 46

Part B Change Notice

CHANGE_NOTICE_C = 47

Part C Change Notice

PMP = 48

Parallel Master Port

PMP_ERROR = 49

PMP Error

SPI2_ERR = 50

SPI2 Error

SPI2_RX = 51

SPI2 Receiver

SPI2_TX = 52

SPI2 Trasmitter

UART2_ERR = 53

UART2 Error

UART2_RX = 54

UART2 Receiver

UART2_TX = 55

UART2 Trasmitter

I2C2_BUS = 56

I2C2 Bus Collision Event

I2C2_SLAVE = 57

I2C2 Slave Event

I2C2_MASTER = 58

I2C2 Master Event

CTMU = 59

CTMU Event

DMA0 = 60

DMA1 = 61

DMA2 = 62

DMA3 = 63

Trait Implementations

impl Clone for InterruptSource

fn clone(&self) -> InterruptSource

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Copy for InterruptSource

impl Debug for InterruptSource

fn fmt(&self, f: &mut Formatter<'_>) -> Result<(), Error>

Formats the value using the given formatter.