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RegisterBlock

pic32_hal::pac::usb

Struct RegisterBlock 

Source 
pub struct RegisterBlock {
Show 126 fields
    pub u1otgir: Reg<U1OTGIR_SPEC>,
    pub u1otgirclr: Reg<U1OTGIRCLR_SPEC>,
    pub u1otgie: Reg<U1OTGIE_SPEC>,
    pub u1otgieclr: Reg<U1OTGIECLR_SPEC>,
    pub u1otgieset: Reg<U1OTGIESET_SPEC>,
    pub u1otgieinv: Reg<U1OTGIEINV_SPEC>,
    pub u1otgstat: Reg<U1OTGSTAT_SPEC>,
    pub u1otgcon: Reg<U1OTGCON_SPEC>,
    pub u1otgconclr: Reg<U1OTGCONCLR_SPEC>,
    pub u1otgconset: Reg<U1OTGCONSET_SPEC>,
    pub u1otgconinv: Reg<U1OTGCONINV_SPEC>,
    pub u1pwrc: Reg<U1PWRC_SPEC>,
    pub u1pwrcclr: Reg<U1PWRCCLR_SPEC>,
    pub u1pwrcset: Reg<U1PWRCSET_SPEC>,
    pub u1pwrcinv: Reg<U1PWRCINV_SPEC>,
    pub u1ir: Reg<U1IR_SPEC>,
    pub u1irclr: Reg<U1IRCLR_SPEC>,
    pub u1ie: Reg<U1IE_SPEC>,
    pub u1ieclr: Reg<U1IECLR_SPEC>,
    pub u1ieset: Reg<U1IESET_SPEC>,
    pub u1ieinv: Reg<U1IEINV_SPEC>,
    pub u1eir: Reg<U1EIR_SPEC>,
    pub u1eirclr: Reg<U1EIRCLR_SPEC>,
    pub u1eie: Reg<U1EIE_SPEC>,
    pub u1eieclr: Reg<U1EIECLR_SPEC>,
    pub u1eieset: Reg<U1EIESET_SPEC>,
    pub u1eieinv: Reg<U1EIEINV_SPEC>,
    pub u1stat: Reg<U1STAT_SPEC>,
    pub u1con: Reg<U1CON_SPEC>,
    pub u1conclr: Reg<U1CONCLR_SPEC>,
    pub u1conset: Reg<U1CONSET_SPEC>,
    pub u1coninv: Reg<U1CONINV_SPEC>,
    pub u1addr: Reg<U1ADDR_SPEC>,
    pub u1addrclr: Reg<U1ADDRCLR_SPEC>,
    pub u1addrset: Reg<U1ADDRSET_SPEC>,
    pub u1addrinv: Reg<U1ADDRINV_SPEC>,
    pub u1bdtp1: Reg<U1BDTP1_SPEC>,
    pub u1bdtp1clr: Reg<U1BDTP1CLR_SPEC>,
    pub u1bdtp1set: Reg<U1BDTP1SET_SPEC>,
    pub u1bdtp1inv: Reg<U1BDTP1INV_SPEC>,
    pub u1frml: Reg<U1FRML_SPEC>,
    pub u1frmh: Reg<U1FRMH_SPEC>,
    pub u1tok: Reg<U1TOK_SPEC>,
    pub u1tokclr: Reg<U1TOKCLR_SPEC>,
    pub u1tokset: Reg<U1TOKSET_SPEC>,
    pub u1tokinv: Reg<U1TOKINV_SPEC>,
    pub u1sof: Reg<U1SOF_SPEC>,
    pub u1sofclr: Reg<U1SOFCLR_SPEC>,
    pub u1sofset: Reg<U1SOFSET_SPEC>,
    pub u1sofinv: Reg<U1SOFINV_SPEC>,
    pub u1bdtp2: Reg<U1BDTP2_SPEC>,
    pub u1bdtp2clr: Reg<U1BDTP2CLR_SPEC>,
    pub u1bdtp2set: Reg<U1BDTP2SET_SPEC>,
    pub u1bdtp2inv: Reg<U1BDTP2INV_SPEC>,
    pub u1bdtp3: Reg<U1BDTP3_SPEC>,
    pub u1bdtp3clr: Reg<U1BDTP3CLR_SPEC>,
    pub u1bdtp3set: Reg<U1BDTP3SET_SPEC>,
    pub u1bdtp3inv: Reg<U1BDTP3INV_SPEC>,
    pub u1cnfg1: Reg<U1CNFG1_SPEC>,
    pub u1cnfg1clr: Reg<U1CNFG1CLR_SPEC>,
    pub u1cnfg1set: Reg<U1CNFG1SET_SPEC>,
    pub u1cnfg1inv: Reg<U1CNFG1INV_SPEC>,
    pub u1ep0: Reg<U1EP0_SPEC>,
    pub u1ep0clr: Reg<U1EP0CLR_SPEC>,
    pub u1ep0set: Reg<U1EP0SET_SPEC>,
    pub u1ep0inv: Reg<U1EP0INV_SPEC>,
    pub u1ep1: Reg<U1EP1_SPEC>,
    pub u1ep1clr: Reg<U1EP1CLR_SPEC>,
    pub u1ep1set: Reg<U1EP1SET_SPEC>,
    pub u1ep1inv: Reg<U1EP1INV_SPEC>,
    pub u1ep2: Reg<U1EP2_SPEC>,
    pub u1ep2clr: Reg<U1EP2CLR_SPEC>,
    pub u1ep2set: Reg<U1EP2SET_SPEC>,
    pub u1ep2inv: Reg<U1EP2INV_SPEC>,
    pub u1ep3: Reg<U1EP3_SPEC>,
    pub u1ep3clr: Reg<U1EP3CLR_SPEC>,
    pub u1ep3set: Reg<U1EP3SET_SPEC>,
    pub u1ep3inv: Reg<U1EP3INV_SPEC>,
    pub u1ep4: Reg<U1EP4_SPEC>,
    pub u1ep4clr: Reg<U1EP4CLR_SPEC>,
    pub u1ep4set: Reg<U1EP4SET_SPEC>,
    pub u1ep4inv: Reg<U1EP4INV_SPEC>,
    pub u1ep5: Reg<U1EP5_SPEC>,
    pub u1ep5clr: Reg<U1EP5CLR_SPEC>,
    pub u1ep5set: Reg<U1EP5SET_SPEC>,
    pub u1ep5inv: Reg<U1EP5INV_SPEC>,
    pub u1ep6: Reg<U1EP6_SPEC>,
    pub u1ep6clr: Reg<U1EP6CLR_SPEC>,
    pub u1ep6set: Reg<U1EP6SET_SPEC>,
    pub u1ep6inv: Reg<U1EP6INV_SPEC>,
    pub u1ep7: Reg<U1EP7_SPEC>,
    pub u1ep7clr: Reg<U1EP7CLR_SPEC>,
    pub u1ep7set: Reg<U1EP7SET_SPEC>,
    pub u1ep7inv: Reg<U1EP7INV_SPEC>,
    pub u1ep8: Reg<U1EP8_SPEC>,
    pub u1ep8clr: Reg<U1EP8CLR_SPEC>,
    pub u1ep8set: Reg<U1EP8SET_SPEC>,
    pub u1ep8inv: Reg<U1EP8INV_SPEC>,
    pub u1ep9: Reg<U1EP9_SPEC>,
    pub u1ep9clr: Reg<U1EP9CLR_SPEC>,
    pub u1ep9set: Reg<U1EP9SET_SPEC>,
    pub u1ep9inv: Reg<U1EP9INV_SPEC>,
    pub u1ep10: Reg<U1EP10_SPEC>,
    pub u1ep10clr: Reg<U1EP10CLR_SPEC>,
    pub u1ep10set: Reg<U1EP10SET_SPEC>,
    pub u1ep10inv: Reg<U1EP10INV_SPEC>,
    pub u1ep11: Reg<U1EP11_SPEC>,
    pub u1ep11clr: Reg<U1EP11CLR_SPEC>,
    pub u1ep11set: Reg<U1EP11SET_SPEC>,
    pub u1ep11inv: Reg<U1EP11INV_SPEC>,
    pub u1ep12: Reg<U1EP12_SPEC>,
    pub u1ep12clr: Reg<U1EP12CLR_SPEC>,
    pub u1ep12set: Reg<U1EP12SET_SPEC>,
    pub u1ep12inv: Reg<U1EP12INV_SPEC>,
    pub u1ep13: Reg<U1EP13_SPEC>,
    pub u1ep13clr: Reg<U1EP13CLR_SPEC>,
    pub u1ep13set: Reg<U1EP13SET_SPEC>,
    pub u1ep13inv: Reg<U1EP13INV_SPEC>,
    pub u1ep14: Reg<U1EP14_SPEC>,
    pub u1ep14clr: Reg<U1EP14CLR_SPEC>,
    pub u1ep14set: Reg<U1EP14SET_SPEC>,
    pub u1ep14inv: Reg<U1EP14INV_SPEC>,
    pub u1ep15: Reg<U1EP15_SPEC>,
    pub u1ep15clr: Reg<U1EP15CLR_SPEC>,
    pub u1ep15set: Reg<U1EP15SET_SPEC>,
    pub u1ep15inv: Reg<U1EP15INV_SPEC>,
    /* private fields */

}
Expand description

Register block

Fields§

§u1otgir: Reg<U1OTGIR_SPEC>

0x00 - U1OTGIR register

§u1otgirclr: Reg<U1OTGIRCLR_SPEC>

0x04 - U1OTGIRCLR register

§u1otgie: Reg<U1OTGIE_SPEC>

0x10 - U1OTGIE register

§u1otgieclr: Reg<U1OTGIECLR_SPEC>

0x14 - U1OTGIECLR register

§u1otgieset: Reg<U1OTGIESET_SPEC>

0x18 - U1OTGIESET register

§u1otgieinv: Reg<U1OTGIEINV_SPEC>

0x1c - U1OTGIEINV register

§u1otgstat: Reg<U1OTGSTAT_SPEC>

0x20 - U1OTGSTAT register

§u1otgcon: Reg<U1OTGCON_SPEC>

0x30 - U1OTGCON register

§u1otgconclr: Reg<U1OTGCONCLR_SPEC>

0x34 - U1OTGCONCLR register

§u1otgconset: Reg<U1OTGCONSET_SPEC>

0x38 - U1OTGCONSET register

§u1otgconinv: Reg<U1OTGCONINV_SPEC>

0x3c - U1OTGCONINV register

§u1pwrc: Reg<U1PWRC_SPEC>

0x40 - U1PWRC register

§u1pwrcclr: Reg<U1PWRCCLR_SPEC>

0x44 - U1PWRCCLR register

§u1pwrcset: Reg<U1PWRCSET_SPEC>

0x48 - U1PWRCSET register

§u1pwrcinv: Reg<U1PWRCINV_SPEC>

0x4c - U1PWRCINV register

§u1ir: Reg<U1IR_SPEC>

0x1c0 - U1IR register

§u1irclr: Reg<U1IRCLR_SPEC>

0x1c4 - U1IRCLR register

§u1ie: Reg<U1IE_SPEC>

0x1d0 - U1IE register

§u1ieclr: Reg<U1IECLR_SPEC>

0x1d4 - U1IECLR register

§u1ieset: Reg<U1IESET_SPEC>

0x1d8 - U1IESET register

§u1ieinv: Reg<U1IEINV_SPEC>

0x1dc - U1IEINV register

§u1eir: Reg<U1EIR_SPEC>

0x1e0 - U1EIR register

§u1eirclr: Reg<U1EIRCLR_SPEC>

0x1e4 - U1EIRCLR register

§u1eie: Reg<U1EIE_SPEC>

0x1f0 - U1EIE register

§u1eieclr: Reg<U1EIECLR_SPEC>

0x1f4 - U1EIECLR register

§u1eieset: Reg<U1EIESET_SPEC>

0x1f8 - U1EIESET register

§u1eieinv: Reg<U1EIEINV_SPEC>

0x1fc - U1EIEINV register

§u1stat: Reg<U1STAT_SPEC>

0x200 - U1STAT register

§u1con: Reg<U1CON_SPEC>

0x210 - U1CON register

§u1conclr: Reg<U1CONCLR_SPEC>

0x214 - U1CONCLR register

§u1conset: Reg<U1CONSET_SPEC>

0x218 - U1CONSET register

§u1coninv: Reg<U1CONINV_SPEC>

0x21c - U1CONINV register

§u1addr: Reg<U1ADDR_SPEC>

0x220 - U1ADDR register

§u1addrclr: Reg<U1ADDRCLR_SPEC>

0x224 - U1ADDRCLR register

§u1addrset: Reg<U1ADDRSET_SPEC>

0x228 - U1ADDRSET register

§u1addrinv: Reg<U1ADDRINV_SPEC>

0x22c - U1ADDRINV register

§u1bdtp1: Reg<U1BDTP1_SPEC>

0x230 - U1BDTP1 register

§u1bdtp1clr: Reg<U1BDTP1CLR_SPEC>

0x234 - U1BDTP1CLR register

§u1bdtp1set: Reg<U1BDTP1SET_SPEC>

0x238 - U1BDTP1SET register

§u1bdtp1inv: Reg<U1BDTP1INV_SPEC>

0x23c - U1BDTP1INV register

§u1frml: Reg<U1FRML_SPEC>

0x240 - U1FRML register

§u1frmh: Reg<U1FRMH_SPEC>

0x250 - U1FRMH register

§u1tok: Reg<U1TOK_SPEC>

0x260 - U1TOK register

§u1tokclr: Reg<U1TOKCLR_SPEC>

0x264 - U1TOKCLR register

§u1tokset: Reg<U1TOKSET_SPEC>

0x268 - U1TOKSET register

§u1tokinv: Reg<U1TOKINV_SPEC>

0x26c - U1TOKINV register

§u1sof: Reg<U1SOF_SPEC>

0x270 - U1SOF register

§u1sofclr: Reg<U1SOFCLR_SPEC>

0x274 - U1SOFCLR register

§u1sofset: Reg<U1SOFSET_SPEC>

0x278 - U1SOFSET register

§u1sofinv: Reg<U1SOFINV_SPEC>

0x27c - U1SOFINV register

§u1bdtp2: Reg<U1BDTP2_SPEC>

0x280 - U1BDTP2 register

§u1bdtp2clr: Reg<U1BDTP2CLR_SPEC>

0x284 - U1BDTP2CLR register

§u1bdtp2set: Reg<U1BDTP2SET_SPEC>

0x288 - U1BDTP2SET register

§u1bdtp2inv: Reg<U1BDTP2INV_SPEC>

0x28c - U1BDTP2INV register

§u1bdtp3: Reg<U1BDTP3_SPEC>

0x290 - U1BDTP3 register

§u1bdtp3clr: Reg<U1BDTP3CLR_SPEC>

0x294 - U1BDTP3CLR register

§u1bdtp3set: Reg<U1BDTP3SET_SPEC>

0x298 - U1BDTP3SET register

§u1bdtp3inv: Reg<U1BDTP3INV_SPEC>

0x29c - U1BDTP3INV register

§u1cnfg1: Reg<U1CNFG1_SPEC>

0x2a0 - U1CNFG1 register

§u1cnfg1clr: Reg<U1CNFG1CLR_SPEC>

0x2a4 - U1CNFG1CLR register

§u1cnfg1set: Reg<U1CNFG1SET_SPEC>

0x2a8 - U1CNFG1SET register

§u1cnfg1inv: Reg<U1CNFG1INV_SPEC>

0x2ac - U1CNFG1INV register

§u1ep0: Reg<U1EP0_SPEC>

0x2c0 - U1EP0 register

§u1ep0clr: Reg<U1EP0CLR_SPEC>

0x2c4 - U1EP0CLR register

§u1ep0set: Reg<U1EP0SET_SPEC>

0x2c8 - U1EP0SET register

§u1ep0inv: Reg<U1EP0INV_SPEC>

0x2cc - U1EP0INV register

§u1ep1: Reg<U1EP1_SPEC>

0x2d0 - U1EP1 register

§u1ep1clr: Reg<U1EP1CLR_SPEC>

0x2d4 - U1EP1CLR register

§u1ep1set: Reg<U1EP1SET_SPEC>

0x2d8 - U1EP1SET register

§u1ep1inv: Reg<U1EP1INV_SPEC>

0x2dc - U1EP1INV register

§u1ep2: Reg<U1EP2_SPEC>

0x2e0 - U1EP2 register

§u1ep2clr: Reg<U1EP2CLR_SPEC>

0x2e4 - U1EP2CLR register

§u1ep2set: Reg<U1EP2SET_SPEC>

0x2e8 - U1EP2SET register

§u1ep2inv: Reg<U1EP2INV_SPEC>

0x2ec - U1EP2INV register

§u1ep3: Reg<U1EP3_SPEC>

0x2f0 - U1EP3 register

§u1ep3clr: Reg<U1EP3CLR_SPEC>

0x2f4 - U1EP3CLR register

§u1ep3set: Reg<U1EP3SET_SPEC>

0x2f8 - U1EP3SET register

§u1ep3inv: Reg<U1EP3INV_SPEC>

0x2fc - U1EP3INV register

§u1ep4: Reg<U1EP4_SPEC>

0x300 - U1EP4 register

§u1ep4clr: Reg<U1EP4CLR_SPEC>

0x304 - U1EP4CLR register

§u1ep4set: Reg<U1EP4SET_SPEC>

0x308 - U1EP4SET register

§u1ep4inv: Reg<U1EP4INV_SPEC>

0x30c - U1EP4INV register

§u1ep5: Reg<U1EP5_SPEC>

0x310 - U1EP5 register

§u1ep5clr: Reg<U1EP5CLR_SPEC>

0x314 - U1EP5CLR register

§u1ep5set: Reg<U1EP5SET_SPEC>

0x318 - U1EP5SET register

§u1ep5inv: Reg<U1EP5INV_SPEC>

0x31c - U1EP5INV register

§u1ep6: Reg<U1EP6_SPEC>

0x320 - U1EP6 register

§u1ep6clr: Reg<U1EP6CLR_SPEC>

0x324 - U1EP6CLR register

§u1ep6set: Reg<U1EP6SET_SPEC>

0x328 - U1EP6SET register

§u1ep6inv: Reg<U1EP6INV_SPEC>

0x32c - U1EP6INV register

§u1ep7: Reg<U1EP7_SPEC>

0x330 - U1EP7 register

§u1ep7clr: Reg<U1EP7CLR_SPEC>

0x334 - U1EP7CLR register

§u1ep7set: Reg<U1EP7SET_SPEC>

0x338 - U1EP7SET register

§u1ep7inv: Reg<U1EP7INV_SPEC>

0x33c - U1EP7INV register

§u1ep8: Reg<U1EP8_SPEC>

0x340 - U1EP8 register

§u1ep8clr: Reg<U1EP8CLR_SPEC>

0x344 - U1EP8CLR register

§u1ep8set: Reg<U1EP8SET_SPEC>

0x348 - U1EP8SET register

§u1ep8inv: Reg<U1EP8INV_SPEC>

0x34c - U1EP8INV register

§u1ep9: Reg<U1EP9_SPEC>

0x350 - U1EP9 register

§u1ep9clr: Reg<U1EP9CLR_SPEC>

0x354 - U1EP9CLR register

§u1ep9set: Reg<U1EP9SET_SPEC>

0x358 - U1EP9SET register

§u1ep9inv: Reg<U1EP9INV_SPEC>

0x35c - U1EP9INV register

§u1ep10: Reg<U1EP10_SPEC>

0x360 - U1EP10 register

§u1ep10clr: Reg<U1EP10CLR_SPEC>

0x364 - U1EP10CLR register

§u1ep10set: Reg<U1EP10SET_SPEC>

0x368 - U1EP10SET register

§u1ep10inv: Reg<U1EP10INV_SPEC>

0x36c - U1EP10INV register

§u1ep11: Reg<U1EP11_SPEC>

0x370 - U1EP11 register

§u1ep11clr: Reg<U1EP11CLR_SPEC>

0x374 - U1EP11CLR register

§u1ep11set: Reg<U1EP11SET_SPEC>

0x378 - U1EP11SET register

§u1ep11inv: Reg<U1EP11INV_SPEC>

0x37c - U1EP11INV register

§u1ep12: Reg<U1EP12_SPEC>

0x380 - U1EP12 register

§u1ep12clr: Reg<U1EP12CLR_SPEC>

0x384 - U1EP12CLR register

§u1ep12set: Reg<U1EP12SET_SPEC>

0x388 - U1EP12SET register

§u1ep12inv: Reg<U1EP12INV_SPEC>

0x38c - U1EP12INV register

§u1ep13: Reg<U1EP13_SPEC>

0x390 - U1EP13 register

§u1ep13clr: Reg<U1EP13CLR_SPEC>

0x394 - U1EP13CLR register

§u1ep13set: Reg<U1EP13SET_SPEC>

0x398 - U1EP13SET register

§u1ep13inv: Reg<U1EP13INV_SPEC>

0x39c - U1EP13INV register

§u1ep14: Reg<U1EP14_SPEC>

0x3a0 - U1EP14 register

§u1ep14clr: Reg<U1EP14CLR_SPEC>

0x3a4 - U1EP14CLR register

§u1ep14set: Reg<U1EP14SET_SPEC>

0x3a8 - U1EP14SET register

§u1ep14inv: Reg<U1EP14INV_SPEC>

0x3ac - U1EP14INV register

§u1ep15: Reg<U1EP15_SPEC>

0x3b0 - U1EP15 register

§u1ep15clr: Reg<U1EP15CLR_SPEC>

0x3b4 - U1EP15CLR register

§u1ep15set: Reg<U1EP15SET_SPEC>

0x3b8 - U1EP15SET register

§u1ep15inv: Reg<U1EP15INV_SPEC>

0x3bc - U1EP15INV register

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