Enum CacheResult 

#[repr(u32)]
pub enum CacheResult {
    ACCESS = 0,
    MISS = 1,
}

What sort of cache result we’re interested in observing.

ACCESS counts the total number of operations performed on the cache, whereas MISS counts only those requests that the cache could not satisfy. Treating MISS as a fraction of ACCESS gives you the cache’s miss rate.

This is used used in the Cache type as part of the identification of a cache event. Each variant here corresponds to a particular PERF_COUNT_HW_CACHE_RESULT_... constant supported by the perf_event_open system call.

Variants

ACCESS = 0

Cache was accessed.

MISS = 1

Cache access was a miss.

Trait Implementations

impl Clone for CacheResult

fn clone(&self) -> CacheResult

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for CacheResult

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl PartialEq for CacheResult

fn eq(&self, other: &CacheResult) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for CacheResult

impl Eq for CacheResult

impl StructuralPartialEq for CacheResult