Enum Hardware

pub enum Hardware {
    CpuCycle,
    BusCycle,
    RefCpuCycle,
    Cache(Type, Op, OpResult),
    CacheMiss,
    CacheAccess,
    BranchMiss,
    BranchInstr,
    BackendStalledCycle,
    FrontendStalledCycle,
    Instr,
}

Generalized hardware CPU events.

Not all of these are available on all platforms.

Variants

CpuCycle

Total CPU cycles, affected by CPU frequency scaling.

BusCycle

Bus cycles, which can be different from total cycles.

RefCpuCycle

Reference CPU cycles, not affected by CPU frequency scaling.

Cache(Type, Op, OpResult)

Hardware CPU cache event.

CacheMiss

Cache misses.

Usually this indicates Last Level Cache misses; this is intended to be used in conjunction with the CacheAccess event to calculate cache miss rates (cache miss / cache access).

CacheAccess

Cache accesses.

Usually this indicates Last Level Cache accesses but this may vary depending on your CPU. This may include prefetches and coherency messages; again this depends on the design of your CPU.

BranchMiss

Mispredicted branch instructions.

BranchInstr

Branch instructions retired.

BackendStalledCycle

Stalled cycles during issue.

FrontendStalledCycle

Stalled cycles during retirement.

Instr

Retired instructions.

Be careful, these can be affected by various issues, most notably hardware interrupt counts.

Trait Implementations

impl Clone for Hardware

fn clone(&self) -> Hardware

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Hardware

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl TryFrom<&Hardware> for Event

type Error = Error

The type returned in the event of a conversion error.

fn try_from(value: &Hardware) -> Result<Self, Self::Error>

Performs the conversion.

impl TryFrom<Hardware> for Event

type Error = Error

The type returned in the event of a conversion error.

fn try_from(value: Hardware) -> Result<Self, Self::Error>

Performs the conversion.