Struct PciToPciBridgeHeader

pub struct PciToPciBridgeHeader {

    pub base_addr: [u32; 2],
    pub secondary_latency_timer: u8,
    pub subordinate_bus_number: u8,
    pub secondary_bus_number: u8,
    pub primary_bus_number: u8,
    pub secondary_status: u16,
    pub io_limit: u8,
    pub io_base: u8,
    pub memory_limit: u16,
    pub memory_base: u16,
    pub prefetchable_memory_limit: u16,
    pub prefetchable_memory_base: u16,
    pub prefetchable_base_upper_32_bits: u32,
    pub prefetchable_limit_upper_32_bits: u32,
    pub io_limit_upper_16_bits: u16,
    pub io_base_upper_16_bits: u16,
    pub capability_pointer: u16,
    pub expansion_rom_base_addr: u32,
    pub bridge_control: u16,
    pub interrupt_pin: u8,
    pub interrupt_line: u8,
}

The header for PCI to PCI bus bridges.

All fields are the raw values of every non-reserved register part in the configuration space.

The format of the header in PCI configuration space is the following.

+----------+---------+-------------+--------------+----------------+----------------+
| Register | Offset  |  Bits 31-24 | Bits 23-16   | Bits 15-8      | Bits 7-0       |
+----------+---------+-------------+--------------+----------------+----------------+
|   0x4    |   0x10  |                Base address #0 (BAR0)                        |
|   0x5    |   0x14  |                Base address #1 (BAR1)                        |
|   0x6    |   0x18  | S.Lat Timer | Subord. Bus  | Secondary Bus  | Primary Bus    |
|   0x7    |   0x1C  |     Secondondary Status    |    I/O Limit   |   I/O Base     |
|   0x8    |   0x20  |        Memory Limit        |            Memory Base          |
|   0x9    |   0x24  | Prefetchable Memory Limit  |    Prefetchable Memory Base     |
|   0xA    |   0x28  |            Prefetchable Base Upper 32 Bits                   |
|   0xB    |   0x2C  |            Prefetchable Limit Upper 32 Bits                  |
|   0xC    |   0x30  |   I/O Limit Upper 16 Bits  |     I/O Base Upper 16 Bits      |
|   0xD    |   0x34  |            Reserved        |      Capability Pointer         |
|   0xE    |   0x38  |               Expansion ROM base address                     |
|   0xF    |   0x3C  |       Bridge Control       | Interrupt PIN  | Interrupt Line |
+----------+---------+-------------+--------------+----------------+----------------+

Fields

base_addr: [u32; 2]

secondary_latency_timer: u8

subordinate_bus_number: u8

secondary_bus_number: u8

primary_bus_number: u8

secondary_status: u16

io_limit: u8

io_base: u8

memory_limit: u16

memory_base: u16

prefetchable_memory_limit: u16

prefetchable_memory_base: u16

prefetchable_base_upper_32_bits: u32

prefetchable_limit_upper_32_bits: u32

io_limit_upper_16_bits: u16

io_base_upper_16_bits: u16

capability_pointer: u16

expansion_rom_base_addr: u32

bridge_control: u16

interrupt_pin: u8

interrupt_line: u8

Implementations

impl PciToPciBridgeHeader

pub const LENGTH: usize = 64usize

pub const ID: u8 = 1u8

Trait Implementations

impl Clone for PciToPciBridgeHeader

fn clone(&self) -> PciToPciBridgeHeader

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for PciToPciBridgeHeader

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.