pub trait PciRegion:
Debug
+ Send
+ Sync
+ Sealed {
// Required methods
fn len(&self) -> u64;
fn permissions(&self) -> Permissions;
fn as_ptr(&self) -> Option<*const u8>;
fn as_mut_ptr(&self) -> Option<*mut u8>;
fn read_bytes(&self, offset: u64, buffer: &mut [u8]) -> Result<()>;
fn read_u8(&self, offset: u64) -> Result<u8>;
fn write_u8(&self, offset: u64, value: u8) -> Result<()>;
fn read_le_u16(&self, offset: u64) -> Result<u16>;
fn write_le_u16(&self, offset: u64, value: u16) -> Result<()>;
fn read_le_u32(&self, offset: u64) -> Result<u32>;
fn write_le_u32(&self, offset: u64, value: u32) -> Result<()>;
}
Expand description
A region of PCI Configuration Space, or a BAR, or the Expansion ROM, or VGA Space, or some other device region, or maybe something else, as long it is safe to read and write to it concurrently with no data races.
The region does not necessarily have RAM semantics, i.e., values can change suddenly, writes might not actually write what is being written, reads can have side effects, etc.
Offsets are u64
, not usize
, so you can operate on 64-bit PciRegion
s even when
compiling for 32-bit.
This trait is sealed for forward-compatibility reasons, and thus cannot be implemented by users of the crate.
Required Methods§
Sourcefn permissions(&self) -> Permissions
fn permissions(&self) -> Permissions
Whether the region may be read, written, or both.
Sourcefn as_ptr(&self) -> Option<*const u8>
fn as_ptr(&self) -> Option<*const u8>
Returns a const
pointer to the beginning of the PciRegion
.
If the region is not mapped into memory, this returns None
.
Sourcefn as_mut_ptr(&self) -> Option<*mut u8>
fn as_mut_ptr(&self) -> Option<*mut u8>
Returns a mut
pointer to the beginning of the PciRegion
.
If the region is not writeable or not mapped into memory, this returns None
.
Sourcefn read_bytes(&self, offset: u64, buffer: &mut [u8]) -> Result<()>
fn read_bytes(&self, offset: u64, buffer: &mut [u8]) -> Result<()>
Read from a contiguous range of the region into a byte buffer.
There is no guarantee that the access will be atomic in any sense, or terribly efficient.
Sourcefn read_u8(&self, offset: u64) -> Result<u8>
fn read_u8(&self, offset: u64) -> Result<u8>
Read an u8
at the given byte offset from the beginning of the PciRegion
.
This will fail if offset + 1 > self.len()
.
Sourcefn write_u8(&self, offset: u64, value: u8) -> Result<()>
fn write_u8(&self, offset: u64, value: u8) -> Result<()>
Write an u8
at the given byte offset from the beginning of the PciRegion
.
This will fail if offset + 1 > self.len()
.
Sourcefn read_le_u16(&self, offset: u64) -> Result<u16>
fn read_le_u16(&self, offset: u64) -> Result<u16>
Read a little-endian u16
at the given byte offset from the beginning of the PciRegion
.
The read value will be converted from little-endian to the native endianness before being returned.
This will fail if offset + 2 > self.len()
, or if the region requires aligned accesses and
offset
is not 2-byte aligned.
Sourcefn write_le_u16(&self, offset: u64, value: u16) -> Result<()>
fn write_le_u16(&self, offset: u64, value: u16) -> Result<()>
Write a little-endian u16
at the given byte offset from the beginning of the
PciRegion
.
The value will be converted from the native endianness to little-endian before being written.
This will fail if offset + 2 > self.len()
, or if the region requires aligned accesses and
offset
is not 2-byte aligned.
Sourcefn read_le_u32(&self, offset: u64) -> Result<u32>
fn read_le_u32(&self, offset: u64) -> Result<u32>
Read a little-endian u32
at the given byte offset from the beginning of the PciRegion
.
The read value will be converted from little-endian to the native endianness before being returned.
This will fail if offset + 4 > self.len()
, or if the region requires aligned accesses and
offset
is not 4-byte aligned.
Sourcefn write_le_u32(&self, offset: u64, value: u32) -> Result<()>
fn write_le_u32(&self, offset: u64, value: u32) -> Result<()>
Write a little-endian u32
at the given byte offset from the beginning of the
PciRegion
.
The value will be converted from the native endianness to little-endian before being written.
This will fail if offset + 4 > self.len()
, or if the region requires aligned accesses and
offset
is not 4-byte aligned.
Trait Implementations§
Source§impl<'a> AsPciSubregion<'a> for &'a dyn PciRegion
impl<'a> AsPciSubregion<'a> for &'a dyn PciRegion
Source§fn as_subregion(&self) -> PciSubregion<'a>
fn as_subregion(&self) -> PciSubregion<'a>
PciSubregion
corresponding to self
.Source§fn subregion(&self, range: impl RangeBounds<u64>) -> PciSubregion<'a>
fn subregion(&self, range: impl RangeBounds<u64>) -> PciSubregion<'a>
PciSubregion
corresponding to a range of self
.