pub trait PciRegion: Debug + Send + Sync + Sealed {
    fn len(&self) -> u64;
    fn permissions(&self) -> Permissions;
    fn as_ptr(&self) -> Option<*const u8>;
    fn as_mut_ptr(&self) -> Option<*mut u8>;
    fn read_bytes(&self, offset: u64, buffer: &mut [u8]) -> Result<()>;
    fn read_u8(&self, offset: u64) -> Result<u8>;
    fn write_u8(&self, offset: u64, value: u8) -> Result<()>;
    fn read_le_u16(&self, offset: u64) -> Result<u16>;
    fn write_le_u16(&self, offset: u64, value: u16) -> Result<()>;
    fn read_le_u32(&self, offset: u64) -> Result<u32>;
    fn write_le_u32(&self, offset: u64, value: u32) -> Result<()>;
}
Expand description

A region of PCI Configuration Space, or a BAR, or the Expansion ROM, or VGA Space, or some other device region, or maybe something else, as long it is safe to read and write to it concurrently with no data races.

The region does not necessarily have RAM semantics, i.e., values can change suddenly, writes might not actually write what is being written, reads can have side effects, etc.

Offsets are u64, not usize, so you can operate on 64-bit PciRegions even when compiling for 32-bit.

This trait is sealed for forward-compatibility reasons, and thus cannot be implemented by users of the crate.

Required Methods

The length of the region in bytes.

Whether the region may be read, written, or both.

Returns a const pointer to the beginning of the PciRegion.

If the region is not mapped into memory, this returns None.

Returns a mut pointer to the beginning of the PciRegion.

If the region is not writeable or not mapped into memory, this returns None.

Read from a contiguous range of the region into a byte buffer.

There is no guarantee that the access will be atomic in any sense, or terribly efficient.

Read an u8 at the given byte offset from the beginning of the PciRegion.

This will fail if offset + 1 > self.len().

Write an u8 at the given byte offset from the beginning of the PciRegion.

This will fail if offset + 1 > self.len().

Read a little-endian u16 at the given byte offset from the beginning of the PciRegion.

The read value will be converted from little-endian to the native endianness before being returned.

This will fail if offset + 2 > self.len(), or if the region requires aligned accesses and offset is not 2-byte aligned.

Write a little-endian u16 at the given byte offset from the beginning of the PciRegion.

The value will be converted from the native endianness to little-endian before being written.

This will fail if offset + 2 > self.len(), or if the region requires aligned accesses and offset is not 2-byte aligned.

Read a little-endian u32 at the given byte offset from the beginning of the PciRegion.

The read value will be converted from little-endian to the native endianness before being returned.

This will fail if offset + 4 > self.len(), or if the region requires aligned accesses and offset is not 4-byte aligned.

Write a little-endian u32 at the given byte offset from the beginning of the PciRegion.

The value will be converted from the native endianness to little-endian before being written.

This will fail if offset + 4 > self.len(), or if the region requires aligned accesses and offset is not 4-byte aligned.

Trait Implementations

Returns a PciSubregion corresponding to self.

Returns a PciSubregion corresponding to a range of self.

Implementors