Crate page_table_multiarch 

page_table_multiarch

This crate provides generic, unified, architecture-independent, and OS-free page table structures for various hardware architectures.

The core structs are PageTable64<M, PTE, H> (for 64-bit) and PageTable32<M, PTE, H> (for 32-bit). OS-functions and architecture-dependent types are provided by generic parameters:

• M: The architecture-dependent metadata, requires to implement the PagingMetaData trait.
• PTE: The architecture-dependent page table entry, requires to implement the GenericPTE trait.
• H: OS-functions such as physical memory allocation, requires to implement the PagingHandler trait.

Currently supported architectures and page table structures:

• x86: x86_64::X64PageTable
• ARM (64-bit): aarch64::A64PageTable
• ARM (32-bit): arm::A32PageTable
• RISC-V: riscv::Sv39PageTable, riscv::Sv48PageTable
• LoongArch64: loongarch64:LA64PageTable

Examples (x86_64)

use memory_addr::{MemoryAddr, PhysAddr, VirtAddr};
use page_table_multiarch::x86_64::{X64PageTable};
use page_table_multiarch::{MappingFlags, PagingHandler, PageSize};

use core::alloc::Layout;

extern crate alloc;

struct PagingHandlerImpl;

impl PagingHandler for PagingHandlerImpl {
    fn alloc_frame() -> Option<PhysAddr> {
        let layout = Layout::from_size_align(0x1000, 0x1000).unwrap();
        let ptr = unsafe { alloc::alloc::alloc(layout) };
        Some(PhysAddr::from(ptr as usize))
    }

    fn alloc_frames(num_pages: usize, align: usize) -> Option<PhysAddr> {
        let layout = Layout::from_size_align(num_pages * 0x1000, align).unwrap();
        let ptr = unsafe { alloc::alloc::alloc(layout) };
        Some(PhysAddr::from(ptr as usize))
    }

    fn dealloc_frame(paddr: PhysAddr) {
        let layout = Layout::from_size_align(0x1000, 0x1000).unwrap();
        let ptr = paddr.as_usize() as *mut u8;
        unsafe { alloc::alloc::dealloc(ptr, layout) };
    }
    
    fn dealloc_frames(paddr: PhysAddr, num_pages: usize) {
        let layout = Layout::from_size_align(num_pages * 0x1000, 0x1000).unwrap();
        let ptr = paddr.as_usize() as *mut u8;
        unsafe { alloc::alloc::dealloc(ptr, layout) };
    }

    fn phys_to_virt(paddr: PhysAddr) -> VirtAddr {
        VirtAddr::from(paddr.as_usize())
    }
}

let vaddr = VirtAddr::from(0xdead_beef_000);
let paddr = PhysAddr::from(0x2000);
let flags = MappingFlags::READ | MappingFlags::WRITE;
let mut pt = X64PageTable::<PagingHandlerImpl>::try_new().unwrap();

assert!(pt.root_paddr().is_aligned_4k());
assert!(pt.cursor().map(vaddr, paddr, PageSize::Size4K, flags).is_ok());
assert_eq!(pt.query(vaddr), Ok((paddr, flags, PageSize::Size4K)));

Re-exports

pub use page_table_entry::GenericPTE;

pub use page_table_entry::MappingFlags;

Modules

aarch64AArch64

AArch64 specific page table structures.

armARM

ARMv7-A specific page table structures.

loongarch64LoongArch LA64

LoongArch64 specific page table structures.

riscvRISC-V RV32 or RISC-V RV64

RISC-V specific page table structures.

x86_64x86-64

x86 specific page table structures.

Structs

PageTable3232-bit or docsrs

A generic page table struct for 32-bit ARM platform (ARMv7-A).

PageTable6464-bit or docsrs

A generic page table struct for 64-bit platform.

PageTable32Cursor32-bit or docsrs

A cursor created by PageTable32::cursor to modify the page table.

PageTable64Cursor64-bit or docsrs

A cursor created by PageTable64::cursor to modify the page table.

Enums

PageSize

The page sizes supported by the hardware page table.

PagingError

The error type for page table operation failures.

Traits

PagingHandler

The low-level OS-dependent helpers that must be provided for PageTable64.

PagingMetaData

The architecture-dependent metadata that must be provided for PageTable64.

Type Aliases

PagingResult

The specialized Result type for page table operations.