Enum VerilogType 

pub enum VerilogType {
    Wire(u32),
    Reg(u32),
    Logic(u32),
    Integer,
    Real,
}

Verilog / SystemVerilog data types.

Variants

Wire(u32)

wire [width-1:0] — combinational net

Reg(u32)

reg [width-1:0] — clocked register (Verilog 2001)

Logic(u32)

logic [width-1:0] — SystemVerilog unified net/variable

Integer

integer — 32-bit signed integer

Real

real — 64-bit IEEE-754 double

Trait Implementations

impl Clone for VerilogType

fn clone(&self) -> VerilogType

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for VerilogType

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Display for VerilogType

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl PartialEq for VerilogType

fn eq(&self, other: &VerilogType) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl StructuralPartialEq for VerilogType