Struct VerilogModule 

pub struct VerilogModule {
    pub name: String,
    pub ports: Vec<VerilogPort>,
    pub params: Vec<(String, u64)>,
    pub body: Vec<String>,
}

A complete Verilog / SystemVerilog module definition.

Fields

name: String

Module name (identifier)

ports: Vec<VerilogPort>

Port list

params: Vec<(String, u64)>

parameter declarations: (name, default_value)

body: Vec<String>

Body statements (already-formatted strings)

Implementations

impl VerilogModule

pub fn new(name: impl Into<String>) -> Self

Construct a new empty module.

pub fn add_port(&mut self, port: VerilogPort)

Add a port.

pub fn add_param(&mut self, name: impl Into<String>, default: u64)

Add a parameter with a default value.

pub fn add_stmt(&mut self, stmt: impl Into<String>)

Append a body statement.

Trait Implementations

impl Clone for VerilogModule

fn clone(&self) -> VerilogModule

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for VerilogModule

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.