Struct RiscVBackend 

pub struct RiscVBackend {
    pub is_64bit: bool,
}

RISC-V code-generation backend.

Supports both RV32I (is_64bit = false) and RV64I (is_64bit = true).

Fields

is_64bit: bool

Implementations

impl RiscVBackend

pub fn new(is_64bit: bool) -> Self

pub fn emit_instr(&self, instr: &RiscVInstr) -> String

Emit a single instruction as a text line (GNU assembler syntax).

pub fn emit_function(&self, func: &RiscVFunction) -> String

Emit a complete function (with .globl / .type directives and label).

pub fn prologue(&self, frame_size: u32) -> Vec<RiscVInstr>

Standard RISC-V function prologue.

Saves ra and s0 (frame pointer), sets up a stack frame of frame_size bytes (rounded up to 16-byte alignment).

pub fn epilogue(&self) -> Vec<RiscVInstr>

Standard RISC-V function epilogue (restores ra/s0, deallocates frame).

pub fn calling_convention_args() -> Vec<RiscVReg>

Argument registers per the RISC-V calling convention (a0 .. a7).

pub fn caller_saved() -> Vec<RiscVReg>

Caller-saved (temporary) registers: t0 .. t6.

pub fn callee_saved() -> Vec<RiscVReg>

Callee-saved registers: s0 .. s11.

Trait Implementations

impl Clone for RiscVBackend

fn clone(&self) -> RiscVBackend

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for RiscVBackend

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.