Module simd_buffer 

SIMD-aligned buffer management for high-performance raster operations

This module provides buffers with guaranteed alignment for efficient SIMD operations. It ensures that data is properly aligned for AVX-512 (64 bytes), AVX2 (32 bytes), or SSE2/NEON (16 bytes) instructions.

Features

• Configurable Alignment: Support for 16, 32, and 64-byte alignment
• Zero-Copy Views: Create strided views without copying data
• Tiled Access: Cache-friendly tiled iteration for large rasters
• Type-Safe: Generic over element types with proper trait bounds

Example

use oxigdal_core::simd_buffer::AlignedBuffer;
use oxigdal_core::error::Result;

// Create a 64-byte aligned buffer for f32 data
let mut buffer = AlignedBuffer::<f32>::new(1000, 64)?;

// Fill with data
for (i, val) in buffer.as_mut_slice().iter_mut().enumerate() {
    *val = i as f32;
}

// Access as slice
let sum: f32 = buffer.as_slice().iter().sum();
assert_eq!(sum, 499500.0);

Cache-Friendly Tiling

For large rasters, tiled iteration improves cache locality:

use oxigdal_core::simd_buffer::TiledBuffer;
use oxigdal_core::error::Result;

let buffer: TiledBuffer<f32> = TiledBuffer::new(1024, 1024, 64, 64)?;

for tile in buffer.tiles() {
    // Process each 64x64 tile independently
    // Better cache locality and SIMD-friendly
}

Structs

AlignedBuffer

A buffer with guaranteed SIMD-friendly alignment

StridedIterator

Iterator for strided buffer access

StridedView

A strided view into a buffer for accessing every nth element

Tile

A tile from a tiled buffer

TileIterator

Iterator over tiles in a tiled buffer

TiledBuffer

A tiled buffer for cache-friendly access patterns