Expand description
OxiCUDA Level Zero backend — GPU compute via Intel oneAPI/Level Zero.
§Platform Support
| Platform | Status |
|---|---|
| Linux (Intel GPU) | Full support via libze_loader.so |
| Windows (Intel GPU) | Full support via ze_loader.dll |
| macOS | Not supported (UnsupportedPlatform) |
Re-exports§
pub use backend::LevelZeroBackend;pub use error::LevelZeroError;pub use error::LevelZeroResult;
Modules§
- backend
LevelZeroBackend— the main entry point for the oxicuda-levelzero crate.- command_
list - Host-side Level Zero command-list recording and dispatch planning.
- device
- Level Zero device wrapper.
- error
- Error types for the
oxicuda-levelzerobackend. - memory
- Level Zero memory manager — allocates, copies, and frees device memory buffers using the Level Zero API with host-staging for transfers.
- module_
cache - Host-side module-binary cache and EU-occupancy heuristics.
- multi_
tile - Multi-tile / multi-device dispatch for Intel Level Zero GPUs.
- spirv
- SPIR-V compute kernel generators for the Level Zero backend.
- spirv_
esimd - ESIMD /
SPV_INTEL_subgroupsSPIR-V kernel generators. - spirv_
nn - SPIR-V compute kernel generators for neural-network operations.
- spirv_
subgroup - Sub-group optimized SPIR-V kernel generators for Intel GPUs.
- spirv_
xmx - Intel Xe Matrix Extensions (XMX) SPIR-V kernel generators.
- usm
- Unified Shared Memory (USM) allocation logic for Intel Level Zero.