Module spirv_esimd 

ESIMD / SPV_INTEL_subgroups SPIR-V kernel generators.

Intel GPUs expose Explicit SIMD (ESIMD) block memory operations through the SPV_INTEL_subgroups extension: OpSubgroupBlockReadINTEL / OpSubgroupBlockWriteINTEL move a contiguous block of data per sub-group in a single hardware message, which is critical for high-throughput tile loads on Xe-HPC GEMM. The same extension underpins the DPAS (Dot-Product Accumulate Systolic) path used for INT8 / BF16 systolic GEMM on Xe-HPG.

This module emits the SPIR-V module words for those kernels and is fully CPU-testable: the tests assert on the emitted magic/header, the declared SPV_INTEL_subgroups extension string, the SubgroupBufferBlockIOINTEL capability, and the presence of the block-read/-write opcodes. Actually dispatching the kernel needs a physical Intel GPU and is out of scope here.

Structs

DpasTileConfig

Tile configuration for a DPAS (systolic) GEMM kernel.

Enums

Fp8Format

The two IEEE-style 8-bit float encodings used for low-precision inference.

Functions

dpas_gemm_spirv

Generate an OpenCL SPIR-V GEMM kernel that uses SPV_INTEL_subgroups block reads to feed a per-lane DPAS-style accumulation.

esimd_block_copy_spirv

Generate an OpenCL SPIR-V kernel that copies count floats using OpSubgroupBlockReadINTEL / OpSubgroupBlockWriteINTEL.

gemm_fp8_coop_matrix_spirv

Generate a SPIR-V 1.6 cooperative-matrix module declaring an FP8 GEMM tile.