Enum CUdevice_attribute 

#[non_exhaustive]
#[repr(i32)]
pub enum CUdevice_attribute {
    MaxThreadsPerBlock = 1,
    MaxBlockDimX = 2,
    MaxBlockDimY = 3,
    MaxBlockDimZ = 4,
    MaxGridDimX = 5,
    MaxGridDimY = 6,
    MaxGridDimZ = 7,
    MaxSharedMemoryPerBlock = 8,
    TotalConstantMemory = 9,
    WarpSize = 10,
    MaxPitch = 11,
    MaxRegistersPerBlock = 12,
    ClockRate = 13,
    TextureAlignment = 14,
    GpuOverlap = 15,
    MultiprocessorCount = 16,
    KernelExecTimeout = 17,
    Integrated = 18,
    CanMapHostMemory = 19,
    ComputeMode = 20,
    MaxTexture1DWidth = 21,
    MaxTexture2DWidth = 22,
    MaxTexture2DHeight = 23,
    MaxTexture3DWidth = 24,
    MaxTexture3DHeight = 25,
    MaxTexture3DDepth = 26,
    MaxTexture2DLayeredWidth = 27,
    MaxTexture2DLayeredHeight = 28,
    MaxTexture2DLayeredLayers = 29,
    SurfaceAlignment = 30,
    ConcurrentKernels = 31,
    EccEnabled = 32,
    PciBusId = 33,
    PciDeviceId = 34,
    TccDriver = 35,
    MemoryClockRate = 36,
    GlobalMemoryBusWidth = 37,
    L2CacheSize = 38,
    MaxThreadsPerMultiprocessor = 39,
    AsyncEngineCount = 40,
    UnifiedAddressing = 41,
    MaxTexture1DLayeredWidth = 42,
    MaxTexture1DLayeredLayers = 43,
    MaxTexture2DGatherWidth = 44,
    MaxTexture2DGatherHeight = 45,
    MaxTexture3DWidthAlt = 47,
    MaxTexture3DHeightAlt = 48,
    MaxTexture3DDepthAlt = 49,
    PciDomainId = 50,
    TexturePitchAlignment = 51,
    MaxTexture1DMipmappedWidth2 = 52,
    MaxTextureCubemapWidth = 54,
    MaxTextureCubemapLayeredWidth = 55,
    MaxTextureCubemapLayeredLayers = 56,
    MaxSurface1DWidth = 57,
    MaxSurface2DWidth = 58,
    MaxSurface2DHeight = 59,
    MaxSurface3DWidth = 60,
    MaxSurface3DHeight = 61,
    MaxSurface3DDepth = 62,
    MaxSurfaceCubemapWidth = 63,
    MaxSurface1DLayeredWidth = 64,
    MaxSurface1DLayeredLayers = 65,
    MaxSurface2DLayeredWidth = 66,
    MaxSurface2DLayeredHeight = 67,
    MaxSurface2DLayeredLayers = 68,
    MaxSurfaceCubemapLayeredWidth = 69,
    MaxSurfaceCubemapLayeredLayers = 70,
    MaxTexture1DLinearWidth = 71,
    MaxTexture2DLinearWidth = 72,
    MaxTexture2DLinearHeight = 73,
    MaxTexture2DLinearPitch = 74,
    ComputeCapabilityMajor = 75,
    ComputeCapabilityMinor = 76,
    MaxTexture2DMipmappedWidth = 77,
    MaxTexture2DMipmappedHeight = 78,
    MaxTexture1DMipmappedWidth = 79,
    StreamPrioritiesSupported = 80,
    MaxSharedMemoryPerMultiprocessor = 81,
    MaxRegistersPerMultiprocessor = 82,
    ManagedMemory = 83,
    IsMultiGpuBoard = 84,
    MultiGpuBoardGroupId = 85,
    HostNativeAtomicSupported = 86,
    SingleToDoublePrecisionPerfRatio = 87,
    PageableMemoryAccess = 88,
    ConcurrentManagedAccess = 89,
    ComputePreemptionSupported = 90,
    CanUseHostPointerForRegisteredMem = 91,
    Reserved92 = 92,
    Reserved93 = 93,
    Reserved94 = 94,
    CooperativeLaunch = 95,
    CooperativeMultiDeviceLaunch = 96,
    MaxSharedMemoryPerBlockOptin = 97,
    CanFlushRemoteWrites = 98,
    HostRegisterSupported = 99,
    PageableMemoryAccessUsesHostPageTables = 100,
    DirectManagedMemAccessFromHost = 101,
    VirtualMemoryManagementSupported = 102,
    HandleTypePosixFileDescriptorSupported = 103,
    HandleTypeWin32HandleSupported = 104,
    HandleTypeWin32KmtHandleSupported = 105,
    MaxBlocksPerMultiprocessor = 106,
    GenericCompressionSupported = 107,
    MaxPersistingL2CacheSize = 108,
    MaxAccessPolicyWindowSize = 109,
    GpuDirectRdmaWithCudaVmmSupported = 110,
    AccessPolicyMaxWindowSize = 111,
    ReservedSharedMemoryPerBlock = 112,
    TimelineSemaphoreInteropSupported = 113,
    MemoryPoolsSupported = 115,
    GpuDirectRdmaSupported = 116,
    GpuDirectRdmaFlushWritesOptions = 117,
    GpuDirectRdmaWritesOrdering = 118,
    MemoryPoolSupportedHandleTypes = 119,
    ClusterLaunch = 120,
    DeferredMappingCudaArraySupported = 121,
    IpcEventSupported = 122,
    MemSyncDomainCount = 123,
    TensorMapAccessSupported = 124,
    UnifiedFunctionPointers = 125,
    NumaConfig = 127,
    NumaId = 128,
    MaxTimelineSemaphoreInteropSupported = 129,
    MemSyncDomainSupported = 130,
    GpuDirectRdmaFabricSupported = 131,
    MulticastSupported = 132,
    MpsEnabled = 133,
    HostNumaId = 134,
}

Device attribute identifiers passed to cuDeviceGetAttribute.

Variants (Non-exhaustive)

Non-exhaustive enums could have additional variants added in future. Therefore, when matching against variants of non-exhaustive enums, an extra wildcard arm must be added to account for any future variants.

MaxThreadsPerBlock = 1

Maximum number of threads per block.

MaxBlockDimX = 2

Maximum x-dimension of a block.

MaxBlockDimY = 3

Maximum y-dimension of a block.

MaxBlockDimZ = 4

Maximum z-dimension of a block.

MaxGridDimX = 5

Maximum x-dimension of a grid.

MaxGridDimY = 6

Maximum y-dimension of a grid.

MaxGridDimZ = 7

Maximum z-dimension of a grid.

MaxSharedMemoryPerBlock = 8

Maximum shared memory available per block (bytes).

TotalConstantMemory = 9

Total amount of constant memory on the device (bytes).

WarpSize = 10

Warp size in threads.

MaxPitch = 11

Maximum pitch allowed by memory copies (bytes).

MaxRegistersPerBlock = 12

Maximum number of 32-bit registers per block.

ClockRate = 13

Peak clock frequency in kHz.

TextureAlignment = 14

Alignment requirement for textures.

GpuOverlap = 15

Device can possibly copy memory and execute a kernel concurrently.

MultiprocessorCount = 16

Number of multiprocessors on the device.

KernelExecTimeout = 17

Whether there is a run-time limit on kernels.

Integrated = 18

Device is integrated (shares host memory).

CanMapHostMemory = 19

Device can map host memory with cuMemHostAlloc / cuMemHostRegister.

ComputeMode = 20

Compute mode: default, exclusive, prohibited, etc.

MaxTexture1DWidth = 21

Maximum 1D texture width.

MaxTexture2DWidth = 22

Maximum 2D texture width.

MaxTexture2DHeight = 23

Maximum 2D texture height.

MaxTexture3DWidth = 24

Maximum 3D texture width.

MaxTexture3DHeight = 25

Maximum 3D texture height.

MaxTexture3DDepth = 26

Maximum 3D texture depth.

MaxTexture2DLayeredWidth = 27

Maximum 2D layered texture width.

MaxTexture2DLayeredHeight = 28

Maximum 2D layered texture height.

MaxTexture2DLayeredLayers = 29

Maximum layers in a 2D layered texture.

SurfaceAlignment = 30

Alignment requirement for surfaces.

ConcurrentKernels = 31

Device can execute multiple kernels concurrently.

EccEnabled = 32

Device supports ECC memory.

PciBusId = 33

PCI bus ID of the device.

PciDeviceId = 34

PCI device ID of the device.

TccDriver = 35

Device is using TCC (Tesla Compute Cluster) driver model.

MemoryClockRate = 36

Peak memory clock frequency in kHz.

GlobalMemoryBusWidth = 37

Global memory bus width in bits.

L2CacheSize = 38

Size of L2 cache in bytes.

MaxThreadsPerMultiprocessor = 39

Maximum resident threads per multiprocessor.

AsyncEngineCount = 40

Number of asynchronous engines.

UnifiedAddressing = 41

Device shares a unified address space with the host.

MaxTexture1DLayeredWidth = 42

Maximum 1D layered texture width.

MaxTexture1DLayeredLayers = 43

Maximum layers in a 1D layered texture.

MaxTexture2DGatherWidth = 44

Maximum 2D texture width if CUDA 2D memory allocation is bound.

MaxTexture2DGatherHeight = 45

Maximum 2D texture height if CUDA 2D memory allocation is bound.

MaxTexture3DWidthAlt = 47

Alternate maximum 3D texture width.

MaxTexture3DHeightAlt = 48

Alternate maximum 3D texture height.

MaxTexture3DDepthAlt = 49

Alternate maximum 3D texture depth.

PciDomainId = 50

PCI domain ID.

TexturePitchAlignment = 51

Texture pitch alignment.

MaxTexture1DMipmappedWidth2 = 52

Maximum 1D mipmapped texture width.

MaxTextureCubemapWidth = 54

Maximum width for a cubemap texture.

MaxTextureCubemapLayeredWidth = 55

Maximum width for a cubemap layered texture.

MaxTextureCubemapLayeredLayers = 56

Maximum layers in a cubemap layered texture.

MaxSurface1DWidth = 57

Maximum 1D surface width.

MaxSurface2DWidth = 58

Maximum 2D surface width.

MaxSurface2DHeight = 59

Maximum 2D surface height.

MaxSurface3DWidth = 60

Maximum 3D surface width.

MaxSurface3DHeight = 61

Maximum 3D surface height.

MaxSurface3DDepth = 62

Maximum 3D surface depth.

MaxSurfaceCubemapWidth = 63

Maximum cubemap surface width.

MaxSurface1DLayeredWidth = 64

Maximum 1D layered surface width.

MaxSurface1DLayeredLayers = 65

Maximum layers in a 1D layered surface.

MaxSurface2DLayeredWidth = 66

Maximum 2D layered surface width.

MaxSurface2DLayeredHeight = 67

Maximum 2D layered surface height.

MaxSurface2DLayeredLayers = 68

Maximum layers in a 2D layered surface.

MaxSurfaceCubemapLayeredWidth = 69

Maximum cubemap layered surface width.

MaxSurfaceCubemapLayeredLayers = 70

Maximum layers in a cubemap layered surface.

MaxTexture1DLinearWidth = 71

Maximum 1D linear texture width (deprecated).

MaxTexture2DLinearWidth = 72

Maximum 2D linear texture width.

MaxTexture2DLinearHeight = 73

Maximum 2D linear texture height.

MaxTexture2DLinearPitch = 74

Maximum 2D linear texture pitch (bytes).

ComputeCapabilityMajor = 75

Major compute capability version number.

ComputeCapabilityMinor = 76

Minor compute capability version number.

MaxTexture2DMipmappedWidth = 77

Maximum mipmapped 2D texture width.

MaxTexture2DMipmappedHeight = 78

Maximum mipmapped 2D texture height.

MaxTexture1DMipmappedWidth = 79

Maximum mipmapped 1D texture width.

StreamPrioritiesSupported = 80

Device supports stream priorities.

MaxSharedMemoryPerMultiprocessor = 81

Maximum shared memory per multiprocessor (bytes).

MaxRegistersPerMultiprocessor = 82

Maximum registers per multiprocessor.

ManagedMemory = 83

Device supports managed memory.

IsMultiGpuBoard = 84

Device is on a multi-GPU board.

MultiGpuBoardGroupId = 85

Unique identifier for the multi-GPU board group.

HostNativeAtomicSupported = 86

Host-visible native-atomic support for float operations.

SingleToDoublePrecisionPerfRatio = 87

Ratio of single-to-double precision performance.

PageableMemoryAccess = 88

Device supports pageable memory access.

ConcurrentManagedAccess = 89

Device can access host registered memory at the same virtual address.

ComputePreemptionSupported = 90

Device supports compute preemption.

CanUseHostPointerForRegisteredMem = 91

Device can access host memory via pageable accesses.

Reserved92 = 92

Reserved attribute (CUDA internal, value 92).

Reserved93 = 93

Reserved attribute (CUDA internal, value 93).

Reserved94 = 94

Reserved attribute (CUDA internal, value 94).

CooperativeLaunch = 95

Device supports cooperative kernel launches.

CooperativeMultiDeviceLaunch = 96

Device supports cooperative kernel launches across multiple GPUs.

MaxSharedMemoryPerBlockOptin = 97

Maximum optin shared memory per block.

CanFlushRemoteWrites = 98

Device supports flushing of outstanding remote writes.

HostRegisterSupported = 99

Device supports host-side memory-register functions.

PageableMemoryAccessUsesHostPageTables = 100

Device supports pageable memory access using host page tables.

DirectManagedMemAccessFromHost = 101

Device supports direct access to managed memory on the host.

VirtualMemoryManagementSupported = 102

Device supports virtual memory management APIs.

HandleTypePosixFileDescriptorSupported = 103

Device supports handle-type POSIX file descriptors for IPC.

HandleTypeWin32HandleSupported = 104

Device supports handle-type Win32 handles for IPC.

HandleTypeWin32KmtHandleSupported = 105

Device supports handle-type Win32 KMT handles for IPC.

MaxBlocksPerMultiprocessor = 106

Maximum blocks per multiprocessor.

GenericCompressionSupported = 107

Device supports generic compression for memory.

MaxPersistingL2CacheSize = 108

Maximum persisting L2 cache size (bytes).

MaxAccessPolicyWindowSize = 109

Maximum access-policy window size for L2 cache.

GpuDirectRdmaWithCudaVmmSupported = 110

Device supports RDMA APIs via cuMemRangeGetAttribute.

AccessPolicyMaxWindowSize = 111

Free memory / total memory on the device accessible via cuMemGetInfo.

ReservedSharedMemoryPerBlock = 112

Reserved range of shared memory per SM (bytes).

TimelineSemaphoreInteropSupported = 113

Device supports timeline semaphore interop.

MemoryPoolsSupported = 115

Device supports memory pools (cudaMallocAsync).

GpuDirectRdmaSupported = 116

GPU direct RDMA is supported.

GpuDirectRdmaFlushWritesOptions = 117

GPU direct RDMA flush-writes order.

GpuDirectRdmaWritesOrdering = 118

GPU direct RDMA writes ordering.

MemoryPoolSupportedHandleTypes = 119

Memory pool supported handle types.

ClusterLaunch = 120

Device supports cluster launch.

DeferredMappingCudaArraySupported = 121

Deferred mapping CUDA array supported.

IpcEventSupported = 122

Device supports IPC event handles.

MemSyncDomainCount = 123

Device supports mem-sync domain count.

TensorMapAccessSupported = 124

Device supports tensor-map access to data.

UnifiedFunctionPointers = 125

Unified function pointers supported.

NumaConfig = 127

NUMA config.

NumaId = 128

NUMA id.

MaxTimelineSemaphoreInteropSupported = 129

Multicast supported. Device supports getting the minimum required per-block shared memory for a cooperative launch via the extended attributes.

MemSyncDomainSupported = 130

Device supports memory sync domain operations.

GpuDirectRdmaFabricSupported = 131

Device supports GPU-Direct Fabric.

MulticastSupported = 132

Device supports multicast.

MpsEnabled = 133

Device supports MPS features.

HostNumaId = 134

Host-NUMA identifier.

Trait Implementations

impl Clone for CUdevice_attribute

fn clone(&self) -> CUdevice_attribute

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for CUdevice_attribute

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Hash for CUdevice_attribute

fn hash<__H: Hasher>(&self, state: &mut __H)

Feeds this value into the given Hasher.

fn hash_slice<H>(data: &[Self], state: &mut H)

where H: Hasher, Self: Sized,

Feeds a slice of this type into the given Hasher.

impl PartialEq for CUdevice_attribute

fn eq(&self, other: &CUdevice_attribute) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for CUdevice_attribute

impl Eq for CUdevice_attribute

impl StructuralPartialEq for CUdevice_attribute