pub struct TPUConfig {
pub tpu_version: TPUVersion,
pub num_cores: usize,
pub enable_xla: bool,
pub xla_optimization_level: XLAOptimizationLevel,
pub mixed_precision: bool,
pub batch_size_per_core: usize,
pub enable_pod_coordination: bool,
pub pod_topology: PodTopology,
pub memory_optimization: TPUMemoryOptimization,
pub gradient_compression: bool,
pub prefetch_depth: usize,
pub experimental_features: bool,
}Expand description
TPU configuration for optimization
Fields§
§tpu_version: TPUVersionTPU version (v2, v3, v4, v5e)
num_cores: usizeNumber of TPU cores
enable_xla: boolEnable XLA compilation
xla_optimization_level: XLAOptimizationLevelXLA optimization level
mixed_precision: boolEnable mixed precision on TPU
batch_size_per_core: usizeBatch size per core
enable_pod_coordination: boolEnable TPU pod coordination
pod_topology: PodTopologyPod topology
memory_optimization: TPUMemoryOptimizationMemory optimization strategy
gradient_compression: boolEnable gradient compression for TPU communication
prefetch_depth: usizePrefetch depth for input pipeline
experimental_features: boolEnable experimental features
Trait Implementations§
Auto Trait Implementations§
impl Freeze for TPUConfig
impl RefUnwindSafe for TPUConfig
impl Send for TPUConfig
impl Sync for TPUConfig
impl Unpin for TPUConfig
impl UnsafeUnpin for TPUConfig
impl UnwindSafe for TPUConfig
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fn from_subset(element: &SS) -> SP
The inclusion map: converts
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