Struct SmResourceLimits 

pub struct SmResourceLimits {
    pub compute_capability: (u32, u32),
    pub warp_size: u32,
    pub max_threads_per_block: u32,
    pub max_threads_per_sm: u32,
    pub max_warps_per_sm: u32,
    pub max_blocks_per_sm: u32,
    pub registers_per_sm: u32,
    pub register_alloc_granularity: u32,
    pub shared_mem_per_sm_bytes: usize,
}

Architectural per-SM resource limits for a streaming multiprocessor.

Instances are normally created with one of the named compute-capability constructors (SmResourceLimits::sm_70 … SmResourceLimits::sm_90) or derived from a device report via SmResourceLimits::from_compute_capability / SmResourceLimits::from_device_capabilities.

Fields

compute_capability: (u32, u32)

CUDA compute capability (major, minor) that this model represents.

warp_size: u32

Threads per warp (32 on every NVIDIA architecture to date).

max_threads_per_block: u32

Maximum threads that may be launched in a single thread block.

max_threads_per_sm: u32

Maximum number of resident threads per SM (max_warps_per_sm * warp_size).

max_warps_per_sm: u32

Maximum number of resident warps per SM.

max_blocks_per_sm: u32

Maximum number of resident thread blocks per SM (hard architectural cap).

registers_per_sm: u32

Number of 32-bit registers in the SM register file.

register_alloc_granularity: u32

Granularity (in 32-bit registers) at which a block’s register usage is rounded up.

shared_mem_per_sm_bytes: usize

Bytes of shared memory available per SM.

Implementations

impl SmResourceLimits

pub const fn sm_70() -> Self

Volta — compute capability 7.0 (e.g. Tesla V100).

Documented per-SM limits (CUDA C Programming Guide, “Technical Specifications per Compute Capability”):

• 64 resident warps / 2048 resident threads per SM
• 32 resident thread blocks per SM
• 65536 32-bit registers per SM, allocated with 256-register granularity
• 96 KiB (98304 bytes) of shared memory per SM
• 1024 threads per block, 32 threads per warp

pub const fn sm_75() -> Self

Turing — compute capability 7.5 (e.g. RTX 2080, T4).

Turing halves the resident warp/thread budget relative to Volta:

• 32 resident warps / 1024 resident threads per SM
• 16 resident thread blocks per SM
• 65536 32-bit registers per SM, 256-register granularity
• 64 KiB (65536 bytes) of shared memory per SM
• 1024 threads per block, 32 threads per warp

pub const fn sm_80() -> Self

Ampere A100 — compute capability 8.0 (datacenter GA100).

• 64 resident warps / 2048 resident threads per SM
• 32 resident thread blocks per SM
• 65536 32-bit registers per SM, 256-register granularity
• 164 KiB (167936 bytes) of shared memory per SM (opt-in maximum)
• 1024 threads per block, 32 threads per warp

pub const fn sm_86() -> Self

Ampere GA10x — compute capability 8.6 (consumer Ampere, e.g. RTX 3080).

GA10x lowers the resident block/warp budget relative to A100:

• 48 resident warps / 1536 resident threads per SM
• 16 resident thread blocks per SM
• 65536 32-bit registers per SM, 256-register granularity
• 100 KiB (102400 bytes) of shared memory per SM (opt-in maximum)
• 1024 threads per block, 32 threads per warp

pub const fn sm_90() -> Self

Hopper — compute capability 9.0 (datacenter H100/GH100).

• 64 resident warps / 2048 resident threads per SM
• 32 resident thread blocks per SM
• 65536 32-bit registers per SM, 256-register granularity
• 228 KiB (233472 bytes) of shared memory per SM (opt-in maximum)
• 1024 threads per block, 32 threads per warp

pub fn from_compute_capability( compute_capability: (u32, u32), ) -> Result<Self, GpuOptimError>

Build limits from a CUDA compute capability (major, minor).

Exact matches map to the corresponding constructor. Capabilities that belong to a known architecture family but are not modelled individually are mapped to the nearest modelled architecture (documented below). Any other capability — including the (0, 0) reported by non-CUDA devices — yields an honest GpuOptimError::UnsupportedOperation rather than a fabricated guess.

Nearest-architecture mappings:

• 7.2 (Volta Xavier) → Self::sm_70
• 8.7 (Ampere Orin) → Self::sm_86
• 8.9 (Ada Lovelace) → Self::sm_86 (closest documented per-SM budget)

pub fn from_device_capabilities( capabilities: &DeviceCapabilities, ) -> Result<Self, GpuOptimError>

Derive limits from a crate::backends::DeviceCapabilities report.

All per-SM architectural constants are taken from the model keyed on the device’s compute_capability; the per-block thread cap is overridden with the device-reported max_threads_per_block when that value is non-zero. Non-CUDA devices (which report a (0, 0) capability) produce an error, because the SM occupancy model does not apply to them.

Trait Implementations

impl Clone for SmResourceLimits

fn clone(&self) -> SmResourceLimits

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Copy for SmResourceLimits

impl Debug for SmResourceLimits

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Eq for SmResourceLimits

impl PartialEq for SmResourceLimits

fn eq(&self, other: &SmResourceLimits) -> bool

Equality operator ==.

fn ne(&self, other: &Rhs) -> bool

Inequality operator !=.

impl StructuralPartialEq for SmResourceLimits