Struct TileConfig 

pub struct TileConfig {
    pub block_m: usize,
    pub block_n: usize,
    pub block_k: usize,
    pub thread_m: usize,
    pub thread_n: usize,
}

Tile configuration for the tiled GEMM algorithm

These parameters control the blocking strategy at different memory levels. Optimal values depend on the target hardware’s cache hierarchy.

Fields

block_m: usize

Block tile size for M dimension (shared memory / L1 cache level)

block_n: usize

Block tile size for N dimension

block_k: usize

Block tile size for K dimension (loop tiling)

thread_m: usize

Register tile size for M dimension (per thread/lane)

thread_n: usize

Register tile size for N dimension (per thread/lane)

Implementations

impl TileConfig

pub const CUDA: Self

CUDA-optimized configuration (Ampere/Ada architecture)

• 128×128 block tiles fit well in shared memory
• 8×8 register tiles maximize occupancy
• BLOCK_K=8 balances memory bandwidth vs compute

pub const WGPU: Self

WebGPU-optimized configuration

• 64×64 block tiles for broader device compatibility
• 4×4 register tiles reduce register pressure

pub const CPU_AVX: Self

CPU AVX2/AVX-512 optimized configuration

• 48×8 tiles fit in L1 cache (32KB)
• 6×8 register tiles fill 12-16 YMM/ZMM registers

pub const CPU_NEON: Self

CPU NEON (ARM) optimized configuration

pub const SIMPLE: Self

Simple configuration for testing/fallback

pub const fn threads_per_block(&self) -> usize

Number of threads per block (for GPU backends)

pub fn validate(&self) -> Result<()>

Validate tile configuration consistency

Trait Implementations

impl Clone for TileConfig

fn clone(&self) -> TileConfig

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for TileConfig

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for TileConfig

fn default() -> Self

Returns the “default value” for a type.

impl Copy for TileConfig