#[repr(u8)]
pub enum VOUT_A {
_1V8,
_2V1,
_2V4,
_2V7,
_3V0,
_3V3,
DEFAULT,
}
Expand description
Output voltage from of REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - VEXDIF.
Value on reset: 7
Variants
_1V8
0: 1.8 V
_2V1
1: 2.1 V
_2V4
2: 2.4 V
_2V7
3: 2.7 V
_3V0
4: 3.0 V
_3V3
5: 3.3 V
DEFAULT
7: Default voltage: 1.8 V
Trait Implementations
impl Copy for VOUT_A
impl StructuralPartialEq for VOUT_A
Auto Trait Implementations
impl RefUnwindSafe for VOUT_A
impl Send for VOUT_A
impl Sync for VOUT_A
impl Unpin for VOUT_A
impl UnwindSafe for VOUT_A
Blanket Implementations
sourceimpl<T> BorrowMut<T> for Twhere
T: ?Sized,
impl<T> BorrowMut<T> for Twhere
T: ?Sized,
const: unstable · sourcefn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
Mutably borrows from an owned value. Read more