Struct nrf52840_hal::pac::egu0::intenset::W

pub struct W(/* private fields */);

Register INTENSET writer

Implementations

impl W

pub fn triggered0( &mut self ) -> BitWriterRaw<'_, u32, INTENSET_SPEC, TRIGGERED0_AW, BitM, 0>

Bit 0 - Write ‘1’ to enable interrupt for TRIGGERED[0] event

pub fn triggered1( &mut self ) -> BitWriterRaw<'_, u32, INTENSET_SPEC, TRIGGERED1_AW, BitM, 1>

Bit 1 - Write ‘1’ to enable interrupt for TRIGGERED[1] event

pub fn triggered2( &mut self ) -> BitWriterRaw<'_, u32, INTENSET_SPEC, TRIGGERED2_AW, BitM, 2>

Bit 2 - Write ‘1’ to enable interrupt for TRIGGERED[2] event

pub fn triggered3( &mut self ) -> BitWriterRaw<'_, u32, INTENSET_SPEC, TRIGGERED3_AW, BitM, 3>

Bit 3 - Write ‘1’ to enable interrupt for TRIGGERED[3] event

pub fn triggered4( &mut self ) -> BitWriterRaw<'_, u32, INTENSET_SPEC, TRIGGERED4_AW, BitM, 4>

Bit 4 - Write ‘1’ to enable interrupt for TRIGGERED[4] event

pub fn triggered5( &mut self ) -> BitWriterRaw<'_, u32, INTENSET_SPEC, TRIGGERED5_AW, BitM, 5>

Bit 5 - Write ‘1’ to enable interrupt for TRIGGERED[5] event

pub fn triggered6( &mut self ) -> BitWriterRaw<'_, u32, INTENSET_SPEC, TRIGGERED6_AW, BitM, 6>

Bit 6 - Write ‘1’ to enable interrupt for TRIGGERED[6] event

pub fn triggered7( &mut self ) -> BitWriterRaw<'_, u32, INTENSET_SPEC, TRIGGERED7_AW, BitM, 7>

Bit 7 - Write ‘1’ to enable interrupt for TRIGGERED[7] event

pub fn triggered8( &mut self ) -> BitWriterRaw<'_, u32, INTENSET_SPEC, TRIGGERED8_AW, BitM, 8>

Bit 8 - Write ‘1’ to enable interrupt for TRIGGERED[8] event

pub fn triggered9( &mut self ) -> BitWriterRaw<'_, u32, INTENSET_SPEC, TRIGGERED9_AW, BitM, 9>

Bit 9 - Write ‘1’ to enable interrupt for TRIGGERED[9] event

pub fn triggered10( &mut self ) -> BitWriterRaw<'_, u32, INTENSET_SPEC, TRIGGERED10_AW, BitM, 10>

Bit 10 - Write ‘1’ to enable interrupt for TRIGGERED[10] event

pub fn triggered11( &mut self ) -> BitWriterRaw<'_, u32, INTENSET_SPEC, TRIGGERED11_AW, BitM, 11>

Bit 11 - Write ‘1’ to enable interrupt for TRIGGERED[11] event

pub fn triggered12( &mut self ) -> BitWriterRaw<'_, u32, INTENSET_SPEC, TRIGGERED12_AW, BitM, 12>

Bit 12 - Write ‘1’ to enable interrupt for TRIGGERED[12] event

pub fn triggered13( &mut self ) -> BitWriterRaw<'_, u32, INTENSET_SPEC, TRIGGERED13_AW, BitM, 13>

Bit 13 - Write ‘1’ to enable interrupt for TRIGGERED[13] event

pub fn triggered14( &mut self ) -> BitWriterRaw<'_, u32, INTENSET_SPEC, TRIGGERED14_AW, BitM, 14>

Bit 14 - Write ‘1’ to enable interrupt for TRIGGERED[14] event

pub fn triggered15( &mut self ) -> BitWriterRaw<'_, u32, INTENSET_SPEC, TRIGGERED15_AW, BitM, 15>

Bit 15 - Write ‘1’ to enable interrupt for TRIGGERED[15] event

pub unsafe fn bits(&mut self, bits: u32) -> &mut W

Writes raw bits to the register.

Methods from Deref<Target = W<INTENSET_SPEC>>

pub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>

Writes raw bits to the register.

Trait Implementations

impl Deref for W

type Target = W<INTENSET_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &<W as Deref>::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut <W as Deref>::Target

Mutably dereferences the value.

impl From<W<INTENSET_SPEC>> for W

fn from(writer: W<INTENSET_SPEC>) -> W

Converts to this type from the input type.