[−][src]Struct nrf52840_hal::pac::generic::W

pub struct W<U, REG> { /* fields omitted */ }

Register writer

Used as an argument to the closures in the write and modify methods of the register

Implementations

`impl<U, REG> W<U, REG>`[src]

`pub unsafe fn bits(&mut self, bits: U) -> &mut W<U, REG>`[src]

Writes raw bits to the register

`impl W<u32, Reg<u32, _NRFFW>>`[src]

`pub fn nrffw(&mut self) -> NRFFW_W`[src]

Bits 0:31 - Reserved for Nordic firmware design

`impl W<u32, Reg<u32, _NRFHW>>`[src]

`pub fn nrfhw(&mut self) -> NRFHW_W`[src]

Bits 0:31 - Reserved for Nordic hardware design

`impl W<u32, Reg<u32, _CUSTOMER>>`[src]

`pub fn customer(&mut self) -> CUSTOMER_W`[src]

Bits 0:31 - Reserved for customer

`impl W<u32, Reg<u32, _PSELRESET>>`[src]

`pub fn pin(&mut self) -> PIN_W`[src]

Bits 0:4 - Pin number of PORT onto which nRESET is exposed

`pub fn port(&mut self) -> PORT_W`[src]

Bit 5 - Port number onto which nRESET is exposed

`pub fn connect(&mut self) -> CONNECT_W`[src]

Bit 31 - Connection

`impl W<u32, Reg<u32, _APPROTECT>>`[src]

`pub fn pall(&mut self) -> PALL_W`[src]

Bits 0:7 - Enable or disable access port protection.

`impl W<u32, Reg<u32, _NFCPINS>>`[src]

`pub fn protect(&mut self) -> PROTECT_W`[src]

Bit 0 - Setting of pins dedicated to NFC functionality

`impl W<u32, Reg<u32, _DEBUGCTRL>>`[src]

`pub fn cpuniden(&mut self) -> CPUNIDEN_W`[src]

`pub fn lfclkstarted(&mut self) -> LFCLKSTARTED_W`[src]

Bit 1 - Write '1' to enable interrupt for LFCLKSTARTED event

`pub fn done(&mut self) -> DONE_W`[src]

Bit 3 - Write '1' to enable interrupt for DONE event

`pub fn ctto(&mut self) -> CTTO_W`[src]

Bit 4 - Write '1' to enable interrupt for CTTO event

`pub fn ctstarted(&mut self) -> CTSTARTED_W`[src]

Bit 10 - Write '1' to enable interrupt for CTSTARTED event

`pub fn ctstopped(&mut self) -> CTSTOPPED_W`[src]

Bit 11 - Write '1' to enable interrupt for CTSTOPPED event

`impl W<u32, Reg<u32, _INTENCLR>>`[src]

`pub fn hfclkstarted(&mut self) -> HFCLKSTARTED_W`[src]

Bit 0 - Write '1' to disable interrupt for HFCLKSTARTED event

`pub fn lfclkstarted(&mut self) -> LFCLKSTARTED_W`[src]

Bit 1 - Write '1' to disable interrupt for LFCLKSTARTED event

`pub fn done(&mut self) -> DONE_W`[src]

Bit 3 - Write '1' to disable interrupt for DONE event

`pub fn ctto(&mut self) -> CTTO_W`[src]

Bit 4 - Write '1' to disable interrupt for CTTO event

`pub fn ctstarted(&mut self) -> CTSTARTED_W`[src]

Bit 10 - Write '1' to disable interrupt for CTSTARTED event

`pub fn ctstopped(&mut self) -> CTSTOPPED_W`[src]

Bit 11 - Write '1' to disable interrupt for CTSTOPPED event

`impl W<u32, Reg<u32, _LFCLKSRC>>`[src]

`pub fn src(&mut self) -> SRC_W`[src]

Bits 0:1 - Clock source

`pub fn bypass(&mut self) -> BYPASS_W`[src]

Bit 16 - Enable or disable bypass of LFCLK crystal oscillator with external clock source

`pub fn external(&mut self) -> EXTERNAL_W`[src]

Bit 17 - Enable or disable external source for LFCLK

`impl W<u32, Reg<u32, _HFXODEBOUNCE>>`[src]

`pub fn hfxodebounce(&mut self) -> HFXODEBOUNCE_W`[src]

Bits 0:7 - HFXO debounce time. Debounce time = HFXODEBOUNCE * 16 us.

`impl W<u32, Reg<u32, _CTIV>>`[src]

`pub fn ctiv(&mut self) -> CTIV_W`[src]

Bits 0:6 - Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds.

`impl W<u32, Reg<u32, _TRACECONFIG>>`[src]

`pub fn traceportspeed(&mut self) -> TRACEPORTSPEED_W`[src]

Bits 0:1 - Speed of trace port clock. Note that the TRACECLK pin will output this clock divided by two.

`pub fn tracemux(&mut self) -> TRACEMUX_W`[src]

Bits 16:17 - Pin multiplexing of trace signals. See pin assignment chapter for more details.

`impl W<u32, Reg<u32, _LFRCMODE>>`[src]

`pub fn mode(&mut self) -> MODE_W`[src]

Bit 0 - Set LFRC mode

`pub fn status(&mut self) -> STATUS_W`[src]

Bit 16 - Active LFRC mode. This field is read only.

`impl W<u32, Reg<u32, _POWER>>`[src]

`pub fn s0power(&mut self) -> S0POWER_W`[src]

Bit 0 - Keep RAM section S0 on or off in System ON mode.

`pub fn s1power(&mut self) -> S1POWER_W`[src]

Bit 1 - Keep RAM section S1 on or off in System ON mode.

`pub fn s2power(&mut self) -> S2POWER_W`[src]

Bit 2 - Keep RAM section S2 on or off in System ON mode.

`pub fn s3power(&mut self) -> S3POWER_W`[src]

Bit 3 - Keep RAM section S3 on or off in System ON mode.

`pub fn s4power(&mut self) -> S4POWER_W`[src]

Bit 4 - Keep RAM section S4 on or off in System ON mode.

`pub fn s5power(&mut self) -> S5POWER_W`[src]

Bit 5 - Keep RAM section S5 on or off in System ON mode.

`pub fn s6power(&mut self) -> S6POWER_W`[src]

Bit 6 - Keep RAM section S6 on or off in System ON mode.

`pub fn s7power(&mut self) -> S7POWER_W`[src]

Bit 7 - Keep RAM section S7 on or off in System ON mode.

`pub fn s8power(&mut self) -> S8POWER_W`[src]

Bit 8 - Keep RAM section S8 on or off in System ON mode.

`pub fn s9power(&mut self) -> S9POWER_W`[src]

Bit 9 - Keep RAM section S9 on or off in System ON mode.

`pub fn s10power(&mut self) -> S10POWER_W`[src]

Bit 10 - Keep RAM section S10 on or off in System ON mode.

`pub fn s11power(&mut self) -> S11POWER_W`[src]

Bit 11 - Keep RAM section S11 on or off in System ON mode.

`pub fn s12power(&mut self) -> S12POWER_W`[src]

Bit 12 - Keep RAM section S12 on or off in System ON mode.

`pub fn s13power(&mut self) -> S13POWER_W`[src]

Bit 13 - Keep RAM section S13 on or off in System ON mode.

`pub fn s14power(&mut self) -> S14POWER_W`[src]

Bit 14 - Keep RAM section S14 on or off in System ON mode.

`pub fn s15power(&mut self) -> S15POWER_W`[src]

Bit 15 - Keep RAM section S15 on or off in System ON mode.

`pub fn s0retention(&mut self) -> S0RETENTION_W`[src]

Bit 16 - Keep retention on RAM section S0 when RAM section is off

`pub fn s1retention(&mut self) -> S1RETENTION_W`[src]

Bit 17 - Keep retention on RAM section S1 when RAM section is off

`pub fn s2retention(&mut self) -> S2RETENTION_W`[src]

Bit 18 - Keep retention on RAM section S2 when RAM section is off

`pub fn s3retention(&mut self) -> S3RETENTION_W`[src]

Bit 19 - Keep retention on RAM section S3 when RAM section is off

`pub fn s4retention(&mut self) -> S4RETENTION_W`[src]

Bit 20 - Keep retention on RAM section S4 when RAM section is off

`pub fn s5retention(&mut self) -> S5RETENTION_W`[src]

Bit 21 - Keep retention on RAM section S5 when RAM section is off

`pub fn s6retention(&mut self) -> S6RETENTION_W`[src]

Bit 22 - Keep retention on RAM section S6 when RAM section is off

`pub fn s7retention(&mut self) -> S7RETENTION_W`[src]

Bit 23 - Keep retention on RAM section S7 when RAM section is off

`pub fn s8retention(&mut self) -> S8RETENTION_W`[src]

Bit 24 - Keep retention on RAM section S8 when RAM section is off

`pub fn s9retention(&mut self) -> S9RETENTION_W`[src]

Bit 25 - Keep retention on RAM section S9 when RAM section is off

`pub fn s10retention(&mut self) -> S10RETENTION_W`[src]

Bit 26 - Keep retention on RAM section S10 when RAM section is off

`pub fn s11retention(&mut self) -> S11RETENTION_W`[src]

Bit 27 - Keep retention on RAM section S11 when RAM section is off

`pub fn s12retention(&mut self) -> S12RETENTION_W`[src]

Bit 28 - Keep retention on RAM section S12 when RAM section is off

`pub fn s13retention(&mut self) -> S13RETENTION_W`[src]

Bit 29 - Keep retention on RAM section S13 when RAM section is off

`pub fn s14retention(&mut self) -> S14RETENTION_W`[src]

Bit 30 - Keep retention on RAM section S14 when RAM section is off

`pub fn s15retention(&mut self) -> S15RETENTION_W`[src]

Bit 31 - Keep retention on RAM section S15 when RAM section is off

`impl W<u32, Reg<u32, _POWERSET>>`[src]

`pub fn s0power(&mut self) -> S0POWER_W`[src]

Bit 0 - Keep RAM section S0 of RAMn on or off in System ON mode

`pub fn s1power(&mut self) -> S1POWER_W`[src]

Bit 1 - Keep RAM section S1 of RAMn on or off in System ON mode

`pub fn s2power(&mut self) -> S2POWER_W`[src]

Bit 2 - Keep RAM section S2 of RAMn on or off in System ON mode

`pub fn s3power(&mut self) -> S3POWER_W`[src]

Bit 3 - Keep RAM section S3 of RAMn on or off in System ON mode

`pub fn s4power(&mut self) -> S4POWER_W`[src]

Bit 4 - Keep RAM section S4 of RAMn on or off in System ON mode

`pub fn s5power(&mut self) -> S5POWER_W`[src]

Bit 5 - Keep RAM section S5 of RAMn on or off in System ON mode

`pub fn s6power(&mut self) -> S6POWER_W`[src]

Bit 6 - Keep RAM section S6 of RAMn on or off in System ON mode

`pub fn s7power(&mut self) -> S7POWER_W`[src]

Bit 7 - Keep RAM section S7 of RAMn on or off in System ON mode

`pub fn s8power(&mut self) -> S8POWER_W`[src]

Bit 8 - Keep RAM section S8 of RAMn on or off in System ON mode

`pub fn s9power(&mut self) -> S9POWER_W`[src]

Bit 9 - Keep RAM section S9 of RAMn on or off in System ON mode

`pub fn s10power(&mut self) -> S10POWER_W`[src]

Bit 10 - Keep RAM section S10 of RAMn on or off in System ON mode

`pub fn s11power(&mut self) -> S11POWER_W`[src]

Bit 11 - Keep RAM section S11 of RAMn on or off in System ON mode

`pub fn s12power(&mut self) -> S12POWER_W`[src]

Bit 12 - Keep RAM section S12 of RAMn on or off in System ON mode

`pub fn s13power(&mut self) -> S13POWER_W`[src]

Bit 13 - Keep RAM section S13 of RAMn on or off in System ON mode

`pub fn s14power(&mut self) -> S14POWER_W`[src]

Bit 14 - Keep RAM section S14 of RAMn on or off in System ON mode

`pub fn s15power(&mut self) -> S15POWER_W`[src]

Bit 15 - Keep RAM section S15 of RAMn on or off in System ON mode

`pub fn s0retention(&mut self) -> S0RETENTION_W`[src]

Bit 16 - Keep retention on RAM section S0 when RAM section is switched off

`pub fn s1retention(&mut self) -> S1RETENTION_W`[src]

Bit 17 - Keep retention on RAM section S1 when RAM section is switched off

`pub fn s2retention(&mut self) -> S2RETENTION_W`[src]

Bit 18 - Keep retention on RAM section S2 when RAM section is switched off

`pub fn s3retention(&mut self) -> S3RETENTION_W`[src]

Bit 19 - Keep retention on RAM section S3 when RAM section is switched off

`pub fn s4retention(&mut self) -> S4RETENTION_W`[src]

Bit 20 - Keep retention on RAM section S4 when RAM section is switched off

`pub fn s5retention(&mut self) -> S5RETENTION_W`[src]

Bit 21 - Keep retention on RAM section S5 when RAM section is switched off

`pub fn s6retention(&mut self) -> S6RETENTION_W`[src]

Bit 22 - Keep retention on RAM section S6 when RAM section is switched off

`pub fn s7retention(&mut self) -> S7RETENTION_W`[src]

Bit 23 - Keep retention on RAM section S7 when RAM section is switched off

`pub fn s8retention(&mut self) -> S8RETENTION_W`[src]

Bit 24 - Keep retention on RAM section S8 when RAM section is switched off

`pub fn s9retention(&mut self) -> S9RETENTION_W`[src]

Bit 25 - Keep retention on RAM section S9 when RAM section is switched off

`pub fn s10retention(&mut self) -> S10RETENTION_W`[src]

Bit 26 - Keep retention on RAM section S10 when RAM section is switched off

`pub fn s11retention(&mut self) -> S11RETENTION_W`[src]

Bit 27 - Keep retention on RAM section S11 when RAM section is switched off

`pub fn s12retention(&mut self) -> S12RETENTION_W`[src]

Bit 28 - Keep retention on RAM section S12 when RAM section is switched off

`pub fn s13retention(&mut self) -> S13RETENTION_W`[src]

Bit 29 - Keep retention on RAM section S13 when RAM section is switched off

`pub fn s14retention(&mut self) -> S14RETENTION_W`[src]

Bit 30 - Keep retention on RAM section S14 when RAM section is switched off

`pub fn s15retention(&mut self) -> S15RETENTION_W`[src]

Bit 31 - Keep retention on RAM section S15 when RAM section is switched off

`impl W<u32, Reg<u32, _POWERCLR>>`[src]

`pub fn s0power(&mut self) -> S0POWER_W`[src]

Bit 0 - Keep RAM section S0 of RAMn on or off in System ON mode

`pub fn s1power(&mut self) -> S1POWER_W`[src]

Bit 1 - Keep RAM section S1 of RAMn on or off in System ON mode

`pub fn s2power(&mut self) -> S2POWER_W`[src]

Bit 2 - Keep RAM section S2 of RAMn on or off in System ON mode

`pub fn s3power(&mut self) -> S3POWER_W`[src]

Bit 3 - Keep RAM section S3 of RAMn on or off in System ON mode

`pub fn s4power(&mut self) -> S4POWER_W`[src]

Bit 4 - Keep RAM section S4 of RAMn on or off in System ON mode

`pub fn s5power(&mut self) -> S5POWER_W`[src]

Bit 5 - Keep RAM section S5 of RAMn on or off in System ON mode

`pub fn s6power(&mut self) -> S6POWER_W`[src]

Bit 6 - Keep RAM section S6 of RAMn on or off in System ON mode

`pub fn s7power(&mut self) -> S7POWER_W`[src]

Bit 7 - Keep RAM section S7 of RAMn on or off in System ON mode

`pub fn s8power(&mut self) -> S8POWER_W`[src]

Bit 8 - Keep RAM section S8 of RAMn on or off in System ON mode

`pub fn s9power(&mut self) -> S9POWER_W`[src]

Bit 9 - Keep RAM section S9 of RAMn on or off in System ON mode

`pub fn s10power(&mut self) -> S10POWER_W`[src]

Bit 10 - Keep RAM section S10 of RAMn on or off in System ON mode

`pub fn s11power(&mut self) -> S11POWER_W`[src]

Bit 11 - Keep RAM section S11 of RAMn on or off in System ON mode

`pub fn s12power(&mut self) -> S12POWER_W`[src]

Bit 12 - Keep RAM section S12 of RAMn on or off in System ON mode

`pub fn s13power(&mut self) -> S13POWER_W`[src]

Bit 13 - Keep RAM section S13 of RAMn on or off in System ON mode

`pub fn s14power(&mut self) -> S14POWER_W`[src]

Bit 14 - Keep RAM section S14 of RAMn on or off in System ON mode

`pub fn s15power(&mut self) -> S15POWER_W`[src]

Bit 15 - Keep RAM section S15 of RAMn on or off in System ON mode

`pub fn s0retention(&mut self) -> S0RETENTION_W`[src]

Bit 16 - Keep retention on RAM section S0 when RAM section is switched off

`pub fn s1retention(&mut self) -> S1RETENTION_W`[src]

Bit 17 - Keep retention on RAM section S1 when RAM section is switched off

`pub fn s2retention(&mut self) -> S2RETENTION_W`[src]

Bit 18 - Keep retention on RAM section S2 when RAM section is switched off

`pub fn s3retention(&mut self) -> S3RETENTION_W`[src]

Bit 19 - Keep retention on RAM section S3 when RAM section is switched off

`pub fn s4retention(&mut self) -> S4RETENTION_W`[src]

Bit 20 - Keep retention on RAM section S4 when RAM section is switched off

`pub fn s5retention(&mut self) -> S5RETENTION_W`[src]

Bit 21 - Keep retention on RAM section S5 when RAM section is switched off

`pub fn s6retention(&mut self) -> S6RETENTION_W`[src]

Bit 22 - Keep retention on RAM section S6 when RAM section is switched off

`pub fn s7retention(&mut self) -> S7RETENTION_W`[src]

Bit 23 - Keep retention on RAM section S7 when RAM section is switched off

`pub fn s8retention(&mut self) -> S8RETENTION_W`[src]

Bit 24 - Keep retention on RAM section S8 when RAM section is switched off

`pub fn s9retention(&mut self) -> S9RETENTION_W`[src]

Bit 25 - Keep retention on RAM section S9 when RAM section is switched off

`pub fn s10retention(&mut self) -> S10RETENTION_W`[src]

Bit 26 - Keep retention on RAM section S10 when RAM section is switched off

`pub fn s11retention(&mut self) -> S11RETENTION_W`[src]

Bit 27 - Keep retention on RAM section S11 when RAM section is switched off

`pub fn s12retention(&mut self) -> S12RETENTION_W`[src]

Bit 28 - Keep retention on RAM section S12 when RAM section is switched off

`pub fn s13retention(&mut self) -> S13RETENTION_W`[src]

Bit 29 - Keep retention on RAM section S13 when RAM section is switched off

`pub fn s14retention(&mut self) -> S14RETENTION_W`[src]

`pub fn sleepenter(&mut self) -> SLEEPENTER_W`[src]

Bit 5 - Write '1' to enable interrupt for SLEEPENTER event

`pub fn sleepexit(&mut self) -> SLEEPEXIT_W`[src]

Bit 6 - Write '1' to enable interrupt for SLEEPEXIT event

`pub fn usbdetected(&mut self) -> USBDETECTED_W`[src]

Bit 7 - Write '1' to enable interrupt for USBDETECTED event

`pub fn usbremoved(&mut self) -> USBREMOVED_W`[src]

Bit 8 - Write '1' to enable interrupt for USBREMOVED event

`pub fn usbpwrrdy(&mut self) -> USBPWRRDY_W`[src]

Bit 9 - Write '1' to enable interrupt for USBPWRRDY event

`impl W<u32, Reg<u32, _INTENCLR>>`[src]

`pub fn pofwarn(&mut self) -> POFWARN_W`[src]

Bit 2 - Write '1' to disable interrupt for POFWARN event

`pub fn sleepenter(&mut self) -> SLEEPENTER_W`[src]

Bit 5 - Write '1' to disable interrupt for SLEEPENTER event

`pub fn sleepexit(&mut self) -> SLEEPEXIT_W`[src]

Bit 6 - Write '1' to disable interrupt for SLEEPEXIT event

`pub fn usbdetected(&mut self) -> USBDETECTED_W`[src]

Bit 7 - Write '1' to disable interrupt for USBDETECTED event

`pub fn usbremoved(&mut self) -> USBREMOVED_W`[src]

Bit 8 - Write '1' to disable interrupt for USBREMOVED event

`pub fn usbpwrrdy(&mut self) -> USBPWRRDY_W`[src]

Bit 9 - Write '1' to disable interrupt for USBPWRRDY event

`impl W<u32, Reg<u32, _RESETREAS>>`[src]

`pub fn resetpin(&mut self) -> RESETPIN_W`[src]

Bit 0 - Reset from pin-reset detected

`pub fn dog(&mut self) -> DOG_W`[src]

Bit 1 - Reset from watchdog detected

`pub fn sreq(&mut self) -> SREQ_W`[src]

Bit 2 - Reset from soft reset detected

`pub fn lockup(&mut self) -> LOCKUP_W`[src]

Bit 3 - Reset from CPU lock-up detected

`pub fn off(&mut self) -> OFF_W`[src]

Bit 16 - Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO

`pub fn lpcomp(&mut self) -> LPCOMP_W`[src]

Bit 17 - Reset due to wake up from System OFF mode when wakeup is triggered from ANADETECT signal from LPCOMP

`pub fn dif(&mut self) -> DIF_W`[src]

Bit 18 - Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode

`pub fn nfc(&mut self) -> NFC_W`[src]

Bit 19 - Reset due to wake up from System OFF mode by NFC field detect

`pub fn vbus(&mut self) -> VBUS_W`[src]

Bit 20 - Reset due to wake up from System OFF mode by VBUS rising into valid range

`impl W<u32, Reg<u32, _SYSTEMOFF>>`[src]

`pub fn systemoff(&mut self) -> SYSTEMOFF_W`[src]

Bit 0 - Enable System OFF mode

`impl W<u32, Reg<u32, _POFCON>>`[src]

`pub fn pof(&mut self) -> POF_W`[src]

Bit 0 - Enable or disable power failure warning

`pub fn threshold(&mut self) -> THRESHOLD_W`[src]

`impl W<u32, Reg<u32, _SHORTS>>`[src]

`pub fn ready_start(&mut self) -> READY_START_W`[src]

Bit 0 - Shortcut between READY event and START task

`pub fn end_disable(&mut self) -> END_DISABLE_W`[src]

Bit 1 - Shortcut between END event and DISABLE task

`pub fn disabled_txen(&mut self) -> DISABLED_TXEN_W`[src]

Bit 2 - Shortcut between DISABLED event and TXEN task

`pub fn disabled_rxen(&mut self) -> DISABLED_RXEN_W`[src]

Bit 3 - Shortcut between DISABLED event and RXEN task

`pub fn address_rssistart(&mut self) -> ADDRESS_RSSISTART_W`[src]

Bit 4 - Shortcut between ADDRESS event and RSSISTART task

`pub fn end_start(&mut self) -> END_START_W`[src]

Bit 5 - Shortcut between END event and START task

`pub fn address_bcstart(&mut self) -> ADDRESS_BCSTART_W`[src]

Bit 6 - Shortcut between ADDRESS event and BCSTART task

`pub fn disabled_rssistop(&mut self) -> DISABLED_RSSISTOP_W`[src]

Bit 8 - Shortcut between DISABLED event and RSSISTOP task

`pub fn rxready_ccastart(&mut self) -> RXREADY_CCASTART_W`[src]

Bit 11 - Shortcut between RXREADY event and CCASTART task

`pub fn ccaidle_txen(&mut self) -> CCAIDLE_TXEN_W`[src]

Bit 12 - Shortcut between CCAIDLE event and TXEN task

`pub fn ccabusy_disable(&mut self) -> CCABUSY_DISABLE_W`[src]

Bit 13 - Shortcut between CCABUSY event and DISABLE task

`pub fn framestart_bcstart(&mut self) -> FRAMESTART_BCSTART_W`[src]

Bit 14 - Shortcut between FRAMESTART event and BCSTART task

`pub fn ready_edstart(&mut self) -> READY_EDSTART_W`[src]

Bit 15 - Shortcut between READY event and EDSTART task

`pub fn edend_disable(&mut self) -> EDEND_DISABLE_W`[src]

Bit 16 - Shortcut between EDEND event and DISABLE task

`pub fn ccaidle_stop(&mut self) -> CCAIDLE_STOP_W`[src]

Bit 17 - Shortcut between CCAIDLE event and STOP task

`pub fn txready_start(&mut self) -> TXREADY_START_W`[src]

Bit 18 - Shortcut between TXREADY event and START task

`pub fn rxready_start(&mut self) -> RXREADY_START_W`[src]

Bit 19 - Shortcut between RXREADY event and START task

`pub fn phyend_disable(&mut self) -> PHYEND_DISABLE_W`[src]

Bit 20 - Shortcut between PHYEND event and DISABLE task

`pub fn phyend_start(&mut self) -> PHYEND_START_W`[src]

Bit 21 - Shortcut between PHYEND event and START task

`impl W<u32, Reg<u32, _INTENSET>>`[src]

`pub fn ready(&mut self) -> READY_W`[src]

Bit 0 - Write '1' to enable interrupt for READY event

`pub fn address(&mut self) -> ADDRESS_W`[src]

Bit 1 - Write '1' to enable interrupt for ADDRESS event

`pub fn payload(&mut self) -> PAYLOAD_W`[src]

Bit 2 - Write '1' to enable interrupt for PAYLOAD event

`pub fn end(&mut self) -> END_W`[src]

Bit 3 - Write '1' to enable interrupt for END event

`pub fn disabled(&mut self) -> DISABLED_W`[src]

Bit 4 - Write '1' to enable interrupt for DISABLED event

`pub fn devmatch(&mut self) -> DEVMATCH_W`[src]

Bit 5 - Write '1' to enable interrupt for DEVMATCH event

`pub fn devmiss(&mut self) -> DEVMISS_W`[src]

Bit 6 - Write '1' to enable interrupt for DEVMISS event

`pub fn rssiend(&mut self) -> RSSIEND_W`[src]

Bit 7 - Write '1' to enable interrupt for RSSIEND event

`pub fn bcmatch(&mut self) -> BCMATCH_W`[src]

Bit 10 - Write '1' to enable interrupt for BCMATCH event

`pub fn crcok(&mut self) -> CRCOK_W`[src]

Bit 12 - Write '1' to enable interrupt for CRCOK event

`pub fn crcerror(&mut self) -> CRCERROR_W`[src]

Bit 13 - Write '1' to enable interrupt for CRCERROR event

`pub fn framestart(&mut self) -> FRAMESTART_W`[src]

Bit 14 - Write '1' to enable interrupt for FRAMESTART event

`pub fn edend(&mut self) -> EDEND_W`[src]

Bit 15 - Write '1' to enable interrupt for EDEND event

`pub fn edstopped(&mut self) -> EDSTOPPED_W`[src]

Bit 16 - Write '1' to enable interrupt for EDSTOPPED event

`pub fn ccaidle(&mut self) -> CCAIDLE_W`[src]

Bit 17 - Write '1' to enable interrupt for CCAIDLE event

`pub fn ccabusy(&mut self) -> CCABUSY_W`[src]

Bit 18 - Write '1' to enable interrupt for CCABUSY event

`pub fn ccastopped(&mut self) -> CCASTOPPED_W`[src]

Bit 19 - Write '1' to enable interrupt for CCASTOPPED event

`pub fn rateboost(&mut self) -> RATEBOOST_W`[src]

Bit 20 - Write '1' to enable interrupt for RATEBOOST event

`pub fn txready(&mut self) -> TXREADY_W`[src]

Bit 21 - Write '1' to enable interrupt for TXREADY event

`pub fn rxready(&mut self) -> RXREADY_W`[src]

Bit 22 - Write '1' to enable interrupt for RXREADY event

`pub fn mhrmatch(&mut self) -> MHRMATCH_W`[src]

Bit 23 - Write '1' to enable interrupt for MHRMATCH event

`pub fn phyend(&mut self) -> PHYEND_W`[src]

Bit 27 - Write '1' to enable interrupt for PHYEND event

`impl W<u32, Reg<u32, _INTENCLR>>`[src]

`pub fn ready(&mut self) -> READY_W`[src]

Bit 0 - Write '1' to disable interrupt for READY event

`pub fn address(&mut self) -> ADDRESS_W`[src]

Bit 1 - Write '1' to disable interrupt for ADDRESS event

`pub fn payload(&mut self) -> PAYLOAD_W`[src]

Bit 2 - Write '1' to disable interrupt for PAYLOAD event

`pub fn end(&mut self) -> END_W`[src]

Bit 3 - Write '1' to disable interrupt for END event

`pub fn disabled(&mut self) -> DISABLED_W`[src]

Bit 4 - Write '1' to disable interrupt for DISABLED event

`pub fn devmatch(&mut self) -> DEVMATCH_W`[src]

Bit 5 - Write '1' to disable interrupt for DEVMATCH event

`pub fn devmiss(&mut self) -> DEVMISS_W`[src]

Bit 6 - Write '1' to disable interrupt for DEVMISS event

`pub fn rssiend(&mut self) -> RSSIEND_W`[src]

Bit 7 - Write '1' to disable interrupt for RSSIEND event

`pub fn bcmatch(&mut self) -> BCMATCH_W`[src]

Bit 10 - Write '1' to disable interrupt for BCMATCH event

`pub fn crcok(&mut self) -> CRCOK_W`[src]

Bit 12 - Write '1' to disable interrupt for CRCOK event

`pub fn crcerror(&mut self) -> CRCERROR_W`[src]

Bit 13 - Write '1' to disable interrupt for CRCERROR event

`pub fn framestart(&mut self) -> FRAMESTART_W`[src]

Bit 14 - Write '1' to disable interrupt for FRAMESTART event

`pub fn edend(&mut self) -> EDEND_W`[src]

Bit 15 - Write '1' to disable interrupt for EDEND event

`pub fn edstopped(&mut self) -> EDSTOPPED_W`[src]

Bit 16 - Write '1' to disable interrupt for EDSTOPPED event

`pub fn ccaidle(&mut self) -> CCAIDLE_W`[src]

Bit 17 - Write '1' to disable interrupt for CCAIDLE event

`pub fn ccabusy(&mut self) -> CCABUSY_W`[src]

Bit 18 - Write '1' to disable interrupt for CCABUSY event

`pub fn ccastopped(&mut self) -> CCASTOPPED_W`[src]

Bit 19 - Write '1' to disable interrupt for CCASTOPPED event

`pub fn rateboost(&mut self) -> RATEBOOST_W`[src]

Bit 20 - Write '1' to disable interrupt for RATEBOOST event

`pub fn txready(&mut self) -> TXREADY_W`[src]

Bit 21 - Write '1' to disable interrupt for TXREADY event

`pub fn rxready(&mut self) -> RXREADY_W`[src]

Bit 22 - Write '1' to disable interrupt for RXREADY event

`pub fn mhrmatch(&mut self) -> MHRMATCH_W`[src]

Bit 23 - Write '1' to disable interrupt for MHRMATCH event

`pub fn phyend(&mut self) -> PHYEND_W`[src]

Bit 27 - Write '1' to disable interrupt for PHYEND event

`impl W<u32, Reg<u32, _PACKETPTR>>`[src]

`pub fn packetptr(&mut self) -> PACKETPTR_W`[src]

Bits 0:31 - Packet pointer

`impl W<u32, Reg<u32, _FREQUENCY>>`[src]

`pub fn frequency(&mut self) -> FREQUENCY_W`[src]

Bits 0:6 - Radio channel frequency

`pub fn map(&mut self) -> MAP_W`[src]

Bit 8 - Channel map selection.

`impl W<u32, Reg<u32, _TXPOWER>>`[src]

`pub fn txpower(&mut self) -> TXPOWER_W`[src]

Bits 0:7 - RADIO output power

`impl W<u32, Reg<u32, _MODE>>`[src]

`pub fn mode(&mut self) -> MODE_W`[src]

Bits 0:3 - Radio data rate and modulation setting. The radio supports frequency-shift keying (FSK) modulation.

`impl W<u32, Reg<u32, _PCNF0>>`[src]

`pub fn lflen(&mut self) -> LFLEN_W`[src]

Bits 0:3 - Length on air of LENGTH field in number of bits.

`pub fn s0len(&mut self) -> S0LEN_W`[src]

Bit 8 - Length on air of S0 field in number of bytes.

`pub fn s1len(&mut self) -> S1LEN_W`[src]

Bits 16:19 - Length on air of S1 field in number of bits.

`pub fn s1incl(&mut self) -> S1INCL_W`[src]

Bit 20 - Include or exclude S1 field in RAM

`pub fn cilen(&mut self) -> CILEN_W`[src]

Bits 22:23 - Length of code indicator - long range

`pub fn plen(&mut self) -> PLEN_W`[src]

Bits 24:25 - Length of preamble on air. Decision point: TASKS_START task

`pub fn crcinc(&mut self) -> CRCINC_W`[src]

Bit 26 - Indicates if LENGTH field contains CRC or not

`pub fn termlen(&mut self) -> TERMLEN_W`[src]

Bits 29:30 - Length of TERM field in Long Range operation

`impl W<u32, Reg<u32, _PCNF1>>`[src]

`pub fn maxlen(&mut self) -> MAXLEN_W`[src]

Bits 0:7 - Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN.

`pub fn statlen(&mut self) -> STATLEN_W`[src]

Bits 8:15 - Static length in number of bytes

`pub fn balen(&mut self) -> BALEN_W`[src]

Bits 16:18 - Base address length in number of bytes

`pub fn endian(&mut self) -> ENDIAN_W`[src]

Bit 24 - On air endianness of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD fields.

`pub fn whiteen(&mut self) -> WHITEEN_W`[src]

Bit 25 - Enable or disable packet whitening

`impl W<u32, Reg<u32, _BASE0>>`[src]

`pub fn base0(&mut self) -> BASE0_W`[src]

Bits 0:31 - Base address 0

`impl W<u32, Reg<u32, _BASE1>>`[src]

`pub fn base1(&mut self) -> BASE1_W`[src]

Bits 0:31 - Base address 1

`impl W<u32, Reg<u32, _PREFIX0>>`[src]

`pub fn ap0(&mut self) -> AP0_W`[src]

Bits 0:7 - Address prefix 0.

`pub fn ap1(&mut self) -> AP1_W`[src]

Bits 8:15 - Address prefix 1.

`pub fn ap2(&mut self) -> AP2_W`[src]

Bits 16:23 - Address prefix 2.

`pub fn ap3(&mut self) -> AP3_W`[src]

Bits 24:31 - Address prefix 3.

`impl W<u32, Reg<u32, _PREFIX1>>`[src]

`pub fn ap4(&mut self) -> AP4_W`[src]

Bits 0:7 - Address prefix 4.

`pub fn ap5(&mut self) -> AP5_W`[src]

Bits 8:15 - Address prefix 5.

`pub fn ap6(&mut self) -> AP6_W`[src]

Bits 16:23 - Address prefix 6.

`pub fn ap7(&mut self) -> AP7_W`[src]

Bits 24:31 - Address prefix 7.

`impl W<u32, Reg<u32, _TXADDRESS>>`[src]

`pub fn txaddress(&mut self) -> TXADDRESS_W`[src]

Bits 0:2 - Transmit address select

`impl W<u32, Reg<u32, _RXADDRESSES>>`[src]

`pub fn addr0(&mut self) -> ADDR0_W`[src]

Bit 0 - Enable or disable reception on logical address 0.

`pub fn addr1(&mut self) -> ADDR1_W`[src]

Bit 1 - Enable or disable reception on logical address 1.

`pub fn addr2(&mut self) -> ADDR2_W`[src]

Bit 2 - Enable or disable reception on logical address 2.

`pub fn addr3(&mut self) -> ADDR3_W`[src]

Bit 3 - Enable or disable reception on logical address 3.

`pub fn addr4(&mut self) -> ADDR4_W`[src]

Bit 4 - Enable or disable reception on logical address 4.

`pub fn addr5(&mut self) -> ADDR5_W`[src]

Bit 5 - Enable or disable reception on logical address 5.

`pub fn addr6(&mut self) -> ADDR6_W`[src]

Bit 6 - Enable or disable reception on logical address 6.

`pub fn addr7(&mut self) -> ADDR7_W`[src]

Bit 7 - Enable or disable reception on logical address 7.

`impl W<u32, Reg<u32, _CRCCNF>>`[src]

`pub fn len(&mut self) -> LEN_W`[src]

Bits 0:1 - CRC length in number of bytes.

`pub fn skipaddr(&mut self) -> SKIPADDR_W`[src]

Bits 8:9 - Include or exclude packet address field out of CRC calculation.

`impl W<u32, Reg<u32, _CRCPOLY>>`[src]

`pub fn crcpoly(&mut self) -> CRCPOLY_W`[src]

Bits 0:23 - CRC polynomial

`impl W<u32, Reg<u32, _CRCINIT>>`[src]

`pub fn crcinit(&mut self) -> CRCINIT_W`[src]

Bits 0:23 - CRC initial value

`impl W<u32, Reg<u32, _TIFS>>`[src]

`pub fn tifs(&mut self) -> TIFS_W`[src]

Bits 0:9 - Interframe spacing in us

`impl W<u32, Reg<u32, _DATAWHITEIV>>`[src]

`pub fn datawhiteiv(&mut self) -> DATAWHITEIV_W`[src]

Bits 0:6 - Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'.

`impl W<u32, Reg<u32, _BCC>>`[src]

`pub fn bcc(&mut self) -> BCC_W`[src]

Bits 0:31 - Bit counter compare

`impl W<u32, Reg<u32, _DAB>>`[src]

`pub fn dab(&mut self) -> DAB_W`[src]

Bits 0:31 - Device address base segment n

`impl W<u32, Reg<u32, _DAP>>`[src]

`pub fn dap(&mut self) -> DAP_W`[src]

Bits 0:15 - Device address prefix n

`impl W<u32, Reg<u32, _DACNF>>`[src]

`pub fn ena0(&mut self) -> ENA0_W`[src]

Bit 0 - Enable or disable device address matching using device address 0

`pub fn ena1(&mut self) -> ENA1_W`[src]

Bit 1 - Enable or disable device address matching using device address 1

`pub fn ena2(&mut self) -> ENA2_W`[src]

Bit 2 - Enable or disable device address matching using device address 2

`pub fn ena3(&mut self) -> ENA3_W`[src]

Bit 3 - Enable or disable device address matching using device address 3

`pub fn ena4(&mut self) -> ENA4_W`[src]

Bit 4 - Enable or disable device address matching using device address 4

`pub fn ena5(&mut self) -> ENA5_W`[src]

Bit 5 - Enable or disable device address matching using device address 5

`pub fn ena6(&mut self) -> ENA6_W`[src]

Bit 6 - Enable or disable device address matching using device address 6

`pub fn ena7(&mut self) -> ENA7_W`[src]

Bit 7 - Enable or disable device address matching using device address 7

`pub fn txadd0(&mut self) -> TXADD0_W`[src]

Bit 8 - TxAdd for device address 0

`pub fn txadd1(&mut self) -> TXADD1_W`[src]

Bit 9 - TxAdd for device address 1

`pub fn txadd2(&mut self) -> TXADD2_W`[src]

Bit 10 - TxAdd for device address 2

`pub fn txadd3(&mut self) -> TXADD3_W`[src]

Bit 11 - TxAdd for device address 3

`pub fn txadd4(&mut self) -> TXADD4_W`[src]

Bit 12 - TxAdd for device address 4

`pub fn txadd5(&mut self) -> TXADD5_W`[src]

Bit 13 - TxAdd for device address 5

`pub fn txadd6(&mut self) -> TXADD6_W`[src]

Bit 14 - TxAdd for device address 6

`pub fn txadd7(&mut self) -> TXADD7_W`[src]

Bit 15 - TxAdd for device address 7

`impl W<u32, Reg<u32, _MODECNF0>>`[src]

`pub fn ru(&mut self) -> RU_W`[src]

Bit 0 - Radio ramp-up time

`pub fn dtx(&mut self) -> DTX_W`[src]

Bits 8:9 - Default TX value

`impl W<u32, Reg<u32, _SFD>>`[src]

`pub fn sfd(&mut self) -> SFD_W`[src]

Bits 0:7 - IEEE 802.15.4 start of frame delimiter

`impl W<u32, Reg<u32, _EDCNT>>`[src]

`pub fn edcnt(&mut self) -> EDCNT_W`[src]

Bits 0:20 - IEEE 802.15.4 energy detect loop count

`impl W<u32, Reg<u32, _EDSAMPLE>>`[src]

`pub fn edlvl(&mut self) -> EDLVL_W`[src]

Bits 0:7 - IEEE 802.15.4 energy detect level

`impl W<u32, Reg<u32, _CCACTRL>>`[src]

`pub fn ccamode(&mut self) -> CCAMODE_W`[src]

Bits 0:2 - CCA mode of operation

`pub fn ccaedthres(&mut self) -> CCAEDTHRES_W`[src]

Bits 8:15 - CCA energy busy threshold. Used in all the CCA modes except CarrierMode.

`pub fn ccacorrthres(&mut self) -> CCACORRTHRES_W`[src]

Bits 16:23 - CCA correlator busy threshold. Only relevant to CarrierMode, CarrierAndEdMode and CarrierOrEdMode.

`pub fn ccacorrcnt(&mut self) -> CCACORRCNT_W`[src]

Bits 24:31 - Limit for occurances above CCACORRTHRES. When not equal to zero the corrolator based signal detect is enabled.

`pub fn cts_startrx(&mut self) -> CTS_STARTRX_W`[src]

Bit 3 - Shortcut between CTS event and STARTRX task

`pub fn ncts_stoprx(&mut self) -> NCTS_STOPRX_W`[src]

Bit 4 - Shortcut between NCTS event and STOPRX task

`impl W<u32, Reg<u32, _INTENSET>>`[src]

`pub fn cts(&mut self) -> CTS_W`[src]

Bit 0 - Write '1' to enable interrupt for CTS event

`pub fn ncts(&mut self) -> NCTS_W`[src]

Bit 1 - Write '1' to enable interrupt for NCTS event

`pub fn rxdrdy(&mut self) -> RXDRDY_W`[src]

Bit 2 - Write '1' to enable interrupt for RXDRDY event

`pub fn txdrdy(&mut self) -> TXDRDY_W`[src]

Bit 7 - Write '1' to enable interrupt for TXDRDY event

`pub fn error(&mut self) -> ERROR_W`[src]

Bit 9 - Write '1' to enable interrupt for ERROR event

`pub fn rxto(&mut self) -> RXTO_W`[src]

Bit 17 - Write '1' to enable interrupt for RXTO event

`impl W<u32, Reg<u32, _INTENCLR>>`[src]

`pub fn cts(&mut self) -> CTS_W`[src]

Bit 0 - Write '1' to disable interrupt for CTS event

`pub fn ncts(&mut self) -> NCTS_W`[src]

Bit 1 - Write '1' to disable interrupt for NCTS event

`pub fn rxdrdy(&mut self) -> RXDRDY_W`[src]

Bit 2 - Write '1' to disable interrupt for RXDRDY event

`pub fn txdrdy(&mut self) -> TXDRDY_W`[src]

Bit 7 - Write '1' to disable interrupt for TXDRDY event

`pub fn error(&mut self) -> ERROR_W`[src]

Bit 9 - Write '1' to disable interrupt for ERROR event

`pub fn rxto(&mut self) -> RXTO_W`[src]

Bit 17 - Write '1' to disable interrupt for RXTO event

`impl W<u32, Reg<u32, _ERRORSRC>>`[src]

`pub fn overrun(&mut self) -> OVERRUN_W`[src]

Bit 0 - Overrun error

`pub fn parity(&mut self) -> PARITY_W`[src]

Bit 1 - Parity error

`pub fn framing(&mut self) -> FRAMING_W`[src]

Bit 2 - Framing error occurred

`pub fn break_(&mut self) -> BREAK_W`[src]

Bit 3 - Break condition

`impl W<u32, Reg<u32, _ENABLE>>`[src]

`pub fn enable(&mut self) -> ENABLE_W`[src]

Bits 0:3 - Enable or disable UART

`impl W<u32, Reg<u32, _TXD>>`[src]

`pub fn txd(&mut self) -> TXD_W`[src]

Bits 0:7 - TX data to be transferred

`impl W<u32, Reg<u32, _BAUDRATE>>`[src]

`pub fn baudrate(&mut self) -> BAUDRATE_W`[src]

Bits 0:31 - Baud rate

Bit 5 - Shortcut between ENDRX event and STARTRX task

`pub fn endrx_stoprx(&mut self) -> ENDRX_STOPRX_W`[src]

Bit 6 - Shortcut between ENDRX event and STOPRX task

`impl W<u32, Reg<u32, _INTEN>>`[src]

`pub fn cts(&mut self) -> CTS_W`[src]

Bit 0 - Enable or disable interrupt for CTS event

`pub fn ncts(&mut self) -> NCTS_W`[src]

Bit 1 - Enable or disable interrupt for NCTS event

`pub fn rxdrdy(&mut self) -> RXDRDY_W`[src]

Bit 2 - Enable or disable interrupt for RXDRDY event

`pub fn endrx(&mut self) -> ENDRX_W`[src]

Bit 4 - Enable or disable interrupt for ENDRX event

`pub fn txdrdy(&mut self) -> TXDRDY_W`[src]

Bit 7 - Enable or disable interrupt for TXDRDY event

`pub fn endtx(&mut self) -> ENDTX_W`[src]

Bit 8 - Enable or disable interrupt for ENDTX event

`pub fn error(&mut self) -> ERROR_W`[src]

Bit 9 - Enable or disable interrupt for ERROR event

`pub fn rxto(&mut self) -> RXTO_W`[src]

Bit 17 - Enable or disable interrupt for RXTO event

`pub fn rxstarted(&mut self) -> RXSTARTED_W`[src]

Bit 19 - Enable or disable interrupt for RXSTARTED event

`pub fn txstarted(&mut self) -> TXSTARTED_W`[src]

Bit 20 - Enable or disable interrupt for TXSTARTED event

`pub fn txstopped(&mut self) -> TXSTOPPED_W`[src]

Bit 22 - Enable or disable interrupt for TXSTOPPED event

`impl W<u32, Reg<u32, _INTENSET>>`[src]

`pub fn cts(&mut self) -> CTS_W`[src]

Bit 0 - Write '1' to enable interrupt for CTS event

`pub fn ncts(&mut self) -> NCTS_W`[src]

Bit 1 - Write '1' to enable interrupt for NCTS event

`pub fn rxdrdy(&mut self) -> RXDRDY_W`[src]

Bit 2 - Write '1' to enable interrupt for RXDRDY event

`pub fn endrx(&mut self) -> ENDRX_W`[src]

Bit 4 - Write '1' to enable interrupt for ENDRX event

`pub fn txdrdy(&mut self) -> TXDRDY_W`[src]

Bit 7 - Write '1' to enable interrupt for TXDRDY event

`pub fn endtx(&mut self) -> ENDTX_W`[src]

Bit 8 - Write '1' to enable interrupt for ENDTX event

`pub fn error(&mut self) -> ERROR_W`[src]

Bit 9 - Write '1' to enable interrupt for ERROR event

`pub fn rxto(&mut self) -> RXTO_W`[src]

Bit 17 - Write '1' to enable interrupt for RXTO event

`pub fn rxstarted(&mut self) -> RXSTARTED_W`[src]

Bit 19 - Write '1' to enable interrupt for RXSTARTED event

`pub fn txstarted(&mut self) -> TXSTARTED_W`[src]

Bit 20 - Write '1' to enable interrupt for TXSTARTED event

`pub fn txstopped(&mut self) -> TXSTOPPED_W`[src]

Bit 22 - Write '1' to enable interrupt for TXSTOPPED event

`impl W<u32, Reg<u32, _INTENCLR>>`[src]

`pub fn cts(&mut self) -> CTS_W`[src]

Bit 0 - Write '1' to disable interrupt for CTS event

`pub fn ncts(&mut self) -> NCTS_W`[src]

Bit 1 - Write '1' to disable interrupt for NCTS event

`pub fn rxdrdy(&mut self) -> RXDRDY_W`[src]

Bit 2 - Write '1' to disable interrupt for RXDRDY event

`pub fn endrx(&mut self) -> ENDRX_W`[src]

Bit 4 - Write '1' to disable interrupt for ENDRX event

`pub fn txdrdy(&mut self) -> TXDRDY_W`[src]

Bit 7 - Write '1' to disable interrupt for TXDRDY event

`pub fn endtx(&mut self) -> ENDTX_W`[src]

Bit 8 - Write '1' to disable interrupt for ENDTX event

`pub fn error(&mut self) -> ERROR_W`[src]

Bit 9 - Write '1' to disable interrupt for ERROR event

`pub fn rxto(&mut self) -> RXTO_W`[src]

Bit 17 - Write '1' to disable interrupt for RXTO event

`pub fn rxstarted(&mut self) -> RXSTARTED_W`[src]

Bit 19 - Write '1' to disable interrupt for RXSTARTED event

`pub fn txstarted(&mut self) -> TXSTARTED_W`[src]

Bit 20 - Write '1' to disable interrupt for TXSTARTED event

`pub fn txstopped(&mut self) -> TXSTOPPED_W`[src]

Bit 22 - Write '1' to disable interrupt for TXSTOPPED event

`impl W<u32, Reg<u32, _ERRORSRC>>`[src]

`pub fn overrun(&mut self) -> OVERRUN_W`[src]

Bit 0 - Overrun error

`pub fn parity(&mut self) -> PARITY_W`[src]

Bit 1 - Parity error

`pub fn framing(&mut self) -> FRAMING_W`[src]

Bit 2 - Framing error occurred

`pub fn break_(&mut self) -> BREAK_W`[src]

Bit 3 - Break condition

`impl W<u32, Reg<u32, _ENABLE>>`[src]

`pub fn enable(&mut self) -> ENABLE_W`[src]

Bits 0:3 - Enable or disable UARTE

`impl W<u32, Reg<u32, _BAUDRATE>>`[src]

`pub fn baudrate(&mut self) -> BAUDRATE_W`[src]

Bits 0:31 - Baud rate

`impl W<u32, Reg<u32, _CONFIG>>`[src]

`pub fn hwfc(&mut self) -> HWFC_W`[src]

Bit 0 - Hardware flow control

`pub fn parity(&mut self) -> PARITY_W`[src]

Bits 1:3 - Parity

`pub fn stop(&mut self) -> STOP_W`[src]

Bit 4 - Stop bits

`impl W<u32, Reg<u32, _SCK>>`[src]

`pub fn pin(&mut self) -> PIN_W`[src]

Bits 0:4 - Pin number

`pub fn port(&mut self) -> PORT_W`[src]

Bit 5 - Port number

`pub fn connect(&mut self) -> CONNECT_W`[src]

Bit 31 - Connection

`impl W<u32, Reg<u32, _MOSI>>`[src]

`pub fn pin(&mut self) -> PIN_W`[src]

Bits 0:4 - Pin number

`pub fn port(&mut self) -> PORT_W`[src]

Bit 5 - Port number

`pub fn connect(&mut self) -> CONNECT_W`[src]

Bit 31 - Connection

`impl W<u32, Reg<u32, _MISO>>`[src]

`pub fn pin(&mut self) -> PIN_W`[src]

Bits 0:4 - Pin number

`pub fn port(&mut self) -> PORT_W`[src]

Bit 5 - Port number

`pub fn connect(&mut self) -> CONNECT_W`[src]

Bit 31 - Connection

`impl W<u32, Reg<u32, _EVENTS_READY>>`[src]

`pub fn events_ready(&mut self) -> EVENTS_READY_W`[src]

Bit 0

`impl W<u32, Reg<u32, _INTENSET>>`[src]

`pub fn ready(&mut self) -> READY_W`[src]

Bit 2 - Write '1' to enable interrupt for READY event

`impl W<u32, Reg<u32, _INTENCLR>>`[src]

`pub fn ready(&mut self) -> READY_W`[src]

Bit 2 - Write '1' to disable interrupt for READY event

`impl W<u32, Reg<u32, _ENABLE>>`[src]

`pub fn enable(&mut self) -> ENABLE_W`[src]

Bits 0:3 - Enable or disable SPI

`impl W<u32, Reg<u32, _TXD>>`[src]

`pub fn txd(&mut self) -> TXD_W`[src]

Bits 0:7 - TX data to send. Double buffered

`impl W<u32, Reg<u32, _SHORTS>>`[src]

`pub fn end_start(&mut self) -> END_START_W`[src]

Bit 17 - Shortcut between END event and START task

`impl W<u32, Reg<u32, _INTENSET>>`[src]

`pub fn stopped(&mut self) -> STOPPED_W`[src]

Bit 1 - Write '1' to enable interrupt for STOPPED event

`pub fn endrx(&mut self) -> ENDRX_W`[src]

Bit 4 - Write '1' to enable interrupt for ENDRX event

`pub fn end(&mut self) -> END_W`[src]

Bit 6 - Write '1' to enable interrupt for END event

`pub fn endtx(&mut self) -> ENDTX_W`[src]

Bit 8 - Write '1' to enable interrupt for ENDTX event

`pub fn started(&mut self) -> STARTED_W`[src]

Bit 19 - Write '1' to enable interrupt for STARTED event

`impl W<u32, Reg<u32, _INTENCLR>>`[src]

`pub fn stopped(&mut self) -> STOPPED_W`[src]

Bit 1 - Write '1' to disable interrupt for STOPPED event

`pub fn endrx(&mut self) -> ENDRX_W`[src]

Bit 4 - Write '1' to disable interrupt for ENDRX event

`pub fn end(&mut self) -> END_W`[src]

Bit 6 - Write '1' to disable interrupt for END event

`pub fn endtx(&mut self) -> ENDTX_W`[src]

Bit 8 - Write '1' to disable interrupt for ENDTX event

`pub fn started(&mut self) -> STARTED_W`[src]

Bit 19 - Write '1' to disable interrupt for STARTED event

`impl W<u32, Reg<u32, _STALLSTAT>>`[src]

`pub fn tx(&mut self) -> TX_W`[src]

Bit 0 - Stall status for EasyDMA RAM reads

`pub fn rx(&mut self) -> RX_W`[src]

Bit 1 - Stall status for EasyDMA RAM writes

`impl W<u32, Reg<u32, _ENABLE>>`[src]

`pub fn enable(&mut self) -> ENABLE_W`[src]

Bits 0:3 - Enable or disable SPIM

`impl W<u32, Reg<u32, _FREQUENCY>>`[src]

`pub fn frequency(&mut self) -> FREQUENCY_W`[src]

Bits 0:31 - SPI master data rate

`impl W<u32, Reg<u32, _CONFIG>>`[src]

`pub fn order(&mut self) -> ORDER_W`[src]

Bit 0 - Bit order

`pub fn cpha(&mut self) -> CPHA_W`[src]

Bit 1 - Serial clock (SCK) phase

`pub fn cpol(&mut self) -> CPOL_W`[src]

Bit 2 - Serial clock (SCK) polarity

`impl W<u32, Reg<u32, _CSNPOL>>`[src]

`pub fn csnpol(&mut self) -> CSNPOL_W`[src]

Bit 0 - Polarity of CSN output

`impl W<u32, Reg<u32, _PSELDCX>>`[src]

`pub fn pin(&mut self) -> PIN_W`[src]

Bits 0:4 - Pin number

`pub fn port(&mut self) -> PORT_W`[src]

Bit 5 - Port number

`pub fn connect(&mut self) -> CONNECT_W`[src]

Bit 31 - Connection

`impl W<u32, Reg<u32, _DCXCNT>>`[src]

`pub fn dcxcnt(&mut self) -> DCXCNT_W`[src]

Bits 0:3 - This register specifies the number of command bytes preceding the data bytes. The PSEL.DCX line will be low during transmission of command bytes and high during transmission of data bytes. Value 0xF indicates that all bytes are command bytes.

Bit 4 - Write '1' to enable interrupt for ENDRX event

`pub fn acquired(&mut self) -> ACQUIRED_W`[src]

Bit 10 - Write '1' to enable interrupt for ACQUIRED event

`impl W<u32, Reg<u32, _INTENCLR>>`[src]

`pub fn end(&mut self) -> END_W`[src]

Bit 1 - Write '1' to disable interrupt for END event

`pub fn endrx(&mut self) -> ENDRX_W`[src]

Bit 4 - Write '1' to disable interrupt for ENDRX event

`pub fn acquired(&mut self) -> ACQUIRED_W`[src]

Bit 10 - Write '1' to disable interrupt for ACQUIRED event

`impl W<u32, Reg<u32, _STATUS>>`[src]

`pub fn overread(&mut self) -> OVERREAD_W`[src]

Bit 0 - TX buffer over-read detected, and prevented

`pub fn overflow(&mut self) -> OVERFLOW_W`[src]

Bit 1 - RX buffer overflow detected, and prevented

`impl W<u32, Reg<u32, _ENABLE>>`[src]

`pub fn enable(&mut self) -> ENABLE_W`[src]

Bits 0:3 - Enable or disable SPI slave

`impl W<u32, Reg<u32, _CONFIG>>`[src]

`pub fn order(&mut self) -> ORDER_W`[src]

Bit 0 - Bit order

`pub fn cpha(&mut self) -> CPHA_W`[src]

Bit 1 - Serial clock (SCK) phase

`pub fn cpol(&mut self) -> CPOL_W`[src]

Bit 2 - Serial clock (SCK) polarity

`impl W<u32, Reg<u32, _DEF>>`[src]

`pub fn def(&mut self) -> DEF_W`[src]

Bits 0:7 - Default character. Character clocked out in case of an ignored transaction.

`impl W<u32, Reg<u32, _ORC>>`[src]

`pub fn orc(&mut self) -> ORC_W`[src]

Bits 0:7 - Over-read character. Character clocked out after an over-read of the transmit buffer.

`impl W<u32, Reg<u32, _SCL>>`[src]

`pub fn pin(&mut self) -> PIN_W`[src]

Bits 0:4 - Pin number

`pub fn port(&mut self) -> PORT_W`[src]

Bit 5 - Port number

`pub fn connect(&mut self) -> CONNECT_W`[src]

Bit 31 - Connection

`impl W<u32, Reg<u32, _SDA>>`[src]

`pub fn pin(&mut self) -> PIN_W`[src]

Bits 0:4 - Pin number

`pub fn port(&mut self) -> PORT_W`[src]

`impl W<u32, Reg<u32, _SHORTS>>`[src]

`pub fn bb_suspend(&mut self) -> BB_SUSPEND_W`[src]

Bit 0 - Shortcut between BB event and SUSPEND task

`pub fn bb_stop(&mut self) -> BB_STOP_W`[src]

Bit 1 - Shortcut between BB event and STOP task

`impl W<u32, Reg<u32, _INTENSET>>`[src]

`pub fn stopped(&mut self) -> STOPPED_W`[src]

Bit 1 - Write '1' to enable interrupt for STOPPED event

`pub fn rxdready(&mut self) -> RXDREADY_W`[src]

Bit 2 - Write '1' to enable interrupt for RXDREADY event

`pub fn txdsent(&mut self) -> TXDSENT_W`[src]

Bit 7 - Write '1' to enable interrupt for TXDSENT event

`pub fn error(&mut self) -> ERROR_W`[src]

Bit 9 - Write '1' to enable interrupt for ERROR event

`pub fn bb(&mut self) -> BB_W`[src]

Bit 14 - Write '1' to enable interrupt for BB event

`pub fn suspended(&mut self) -> SUSPENDED_W`[src]

Bit 18 - Write '1' to enable interrupt for SUSPENDED event

`impl W<u32, Reg<u32, _INTENCLR>>`[src]

`pub fn stopped(&mut self) -> STOPPED_W`[src]

Bit 1 - Write '1' to disable interrupt for STOPPED event

`pub fn rxdready(&mut self) -> RXDREADY_W`[src]

Bit 2 - Write '1' to disable interrupt for RXDREADY event

`pub fn txdsent(&mut self) -> TXDSENT_W`[src]

Bit 7 - Write '1' to disable interrupt for TXDSENT event

`pub fn error(&mut self) -> ERROR_W`[src]

Bit 9 - Write '1' to disable interrupt for ERROR event

`pub fn bb(&mut self) -> BB_W`[src]

Bit 14 - Write '1' to disable interrupt for BB event

`pub fn suspended(&mut self) -> SUSPENDED_W`[src]

Bit 18 - Write '1' to disable interrupt for SUSPENDED event

`impl W<u32, Reg<u32, _ERRORSRC>>`[src]

`pub fn overrun(&mut self) -> OVERRUN_W`[src]

Bit 0 - Overrun error

`pub fn anack(&mut self) -> ANACK_W`[src]

Bit 1 - NACK received after sending the address (write '1' to clear)

`pub fn dnack(&mut self) -> DNACK_W`[src]

Bit 2 - NACK received after sending a data byte (write '1' to clear)

`impl W<u32, Reg<u32, _ENABLE>>`[src]

`pub fn enable(&mut self) -> ENABLE_W`[src]

Bits 0:3 - Enable or disable TWI

`impl W<u32, Reg<u32, _TXD>>`[src]

`pub fn txd(&mut self) -> TXD_W`[src]

Bits 0:7 - TXD register

`impl W<u32, Reg<u32, _FREQUENCY>>`[src]

`pub fn frequency(&mut self) -> FREQUENCY_W`[src]

Bits 0:31 - TWI master clock frequency

`impl W<u32, Reg<u32, _ADDRESS>>`[src]

`pub fn address(&mut self) -> ADDRESS_W`[src]

Bits 0:6 - Address used in the TWI transfer

`impl W<u32, Reg<u32, _SCL>>`[src]

`pub fn pin(&mut self) -> PIN_W`[src]

Bits 0:4 - Pin number

`pub fn port(&mut self) -> PORT_W`[src]

Bit 5 - Port number

`pub fn connect(&mut self) -> CONNECT_W`[src]

Bit 31 - Connection

`impl W<u32, Reg<u32, _SDA>>`[src]

`pub fn pin(&mut self) -> PIN_W`[src]

Bits 0:4 - Pin number

`pub fn port(&mut self) -> PORT_W`[src]

`pub fn lasttx_suspend(&mut self) -> LASTTX_SUSPEND_W`[src]

Bit 8 - Shortcut between LASTTX event and SUSPEND task

`pub fn lasttx_stop(&mut self) -> LASTTX_STOP_W`[src]

Bit 9 - Shortcut between LASTTX event and STOP task

`pub fn lastrx_starttx(&mut self) -> LASTRX_STARTTX_W`[src]

Bit 10 - Shortcut between LASTRX event and STARTTX task

`pub fn lastrx_suspend(&mut self) -> LASTRX_SUSPEND_W`[src]

Bit 11 - Shortcut between LASTRX event and SUSPEND task

`pub fn lastrx_stop(&mut self) -> LASTRX_STOP_W`[src]

Bit 12 - Shortcut between LASTRX event and STOP task

`impl W<u32, Reg<u32, _INTEN>>`[src]

`pub fn stopped(&mut self) -> STOPPED_W`[src]

Bit 1 - Enable or disable interrupt for STOPPED event

`pub fn error(&mut self) -> ERROR_W`[src]

Bit 9 - Enable or disable interrupt for ERROR event

`pub fn suspended(&mut self) -> SUSPENDED_W`[src]

Bit 18 - Enable or disable interrupt for SUSPENDED event

`pub fn rxstarted(&mut self) -> RXSTARTED_W`[src]

Bit 19 - Enable or disable interrupt for RXSTARTED event

`pub fn txstarted(&mut self) -> TXSTARTED_W`[src]

Bit 20 - Enable or disable interrupt for TXSTARTED event

`pub fn lastrx(&mut self) -> LASTRX_W`[src]

Bit 23 - Enable or disable interrupt for LASTRX event

`pub fn lasttx(&mut self) -> LASTTX_W`[src]

Bit 24 - Enable or disable interrupt for LASTTX event

`impl W<u32, Reg<u32, _INTENSET>>`[src]

`pub fn stopped(&mut self) -> STOPPED_W`[src]

Bit 1 - Write '1' to enable interrupt for STOPPED event

`pub fn error(&mut self) -> ERROR_W`[src]

Bit 9 - Write '1' to enable interrupt for ERROR event

`pub fn suspended(&mut self) -> SUSPENDED_W`[src]

Bit 18 - Write '1' to enable interrupt for SUSPENDED event

`pub fn rxstarted(&mut self) -> RXSTARTED_W`[src]

Bit 19 - Write '1' to enable interrupt for RXSTARTED event

`pub fn txstarted(&mut self) -> TXSTARTED_W`[src]

Bit 20 - Write '1' to enable interrupt for TXSTARTED event

`pub fn lastrx(&mut self) -> LASTRX_W`[src]

Bit 23 - Write '1' to enable interrupt for LASTRX event

`pub fn lasttx(&mut self) -> LASTTX_W`[src]

Bit 24 - Write '1' to enable interrupt for LASTTX event

`impl W<u32, Reg<u32, _INTENCLR>>`[src]

`pub fn stopped(&mut self) -> STOPPED_W`[src]

Bit 1 - Write '1' to disable interrupt for STOPPED event

`pub fn error(&mut self) -> ERROR_W`[src]

Bit 9 - Write '1' to disable interrupt for ERROR event

`pub fn suspended(&mut self) -> SUSPENDED_W`[src]

Bit 18 - Write '1' to disable interrupt for SUSPENDED event

`pub fn rxstarted(&mut self) -> RXSTARTED_W`[src]

Bit 19 - Write '1' to disable interrupt for RXSTARTED event

`pub fn txstarted(&mut self) -> TXSTARTED_W`[src]

Bit 20 - Write '1' to disable interrupt for TXSTARTED event

`pub fn lastrx(&mut self) -> LASTRX_W`[src]

Bit 23 - Write '1' to disable interrupt for LASTRX event

`pub fn lasttx(&mut self) -> LASTTX_W`[src]

Bit 24 - Write '1' to disable interrupt for LASTTX event

`impl W<u32, Reg<u32, _ERRORSRC>>`[src]

`pub fn overrun(&mut self) -> OVERRUN_W`[src]

Bit 0 - Overrun error

`pub fn anack(&mut self) -> ANACK_W`[src]

Bit 1 - NACK received after sending the address (write '1' to clear)

`pub fn dnack(&mut self) -> DNACK_W`[src]

Bit 2 - NACK received after sending a data byte (write '1' to clear)

`impl W<u32, Reg<u32, _ENABLE>>`[src]

`pub fn enable(&mut self) -> ENABLE_W`[src]

Bits 0:3 - Enable or disable TWIM

`impl W<u32, Reg<u32, _FREQUENCY>>`[src]

`pub fn frequency(&mut self) -> FREQUENCY_W`[src]

Bits 0:31 - TWI master clock frequency

`impl W<u32, Reg<u32, _ADDRESS>>`[src]

`pub fn address(&mut self) -> ADDRESS_W`[src]

Bits 0:6 - Address used in the TWI transfer

`impl W<u32, Reg<u32, _SCL>>`[src]

`pub fn pin(&mut self) -> PIN_W`[src]

Bits 0:4 - Pin number

`pub fn port(&mut self) -> PORT_W`[src]

Bit 5 - Port number

`pub fn connect(&mut self) -> CONNECT_W`[src]

Bit 31 - Connection

`impl W<u32, Reg<u32, _SDA>>`[src]

`pub fn pin(&mut self) -> PIN_W`[src]

Bits 0:4 - Pin number

`pub fn port(&mut self) -> PORT_W`[src]

`impl W<u32, Reg<u32, _SHORTS>>`[src]

`pub fn write_suspend(&mut self) -> WRITE_SUSPEND_W`[src]

Bit 13 - Shortcut between WRITE event and SUSPEND task

`pub fn read_suspend(&mut self) -> READ_SUSPEND_W`[src]

Bit 14 - Shortcut between READ event and SUSPEND task

`impl W<u32, Reg<u32, _INTEN>>`[src]

`pub fn stopped(&mut self) -> STOPPED_W`[src]

Bit 1 - Enable or disable interrupt for STOPPED event

`pub fn error(&mut self) -> ERROR_W`[src]

Bit 9 - Enable or disable interrupt for ERROR event

`pub fn rxstarted(&mut self) -> RXSTARTED_W`[src]

Bit 19 - Enable or disable interrupt for RXSTARTED event

`pub fn txstarted(&mut self) -> TXSTARTED_W`[src]

Bit 20 - Enable or disable interrupt for TXSTARTED event

`pub fn write(&mut self) -> WRITE_W`[src]

Bit 25 - Enable or disable interrupt for WRITE event

`pub fn read(&mut self) -> READ_W`[src]

Bit 26 - Enable or disable interrupt for READ event

`impl W<u32, Reg<u32, _INTENSET>>`[src]

`pub fn stopped(&mut self) -> STOPPED_W`[src]

Bit 1 - Write '1' to enable interrupt for STOPPED event

`pub fn error(&mut self) -> ERROR_W`[src]

Bit 9 - Write '1' to enable interrupt for ERROR event

`pub fn rxstarted(&mut self) -> RXSTARTED_W`[src]

Bit 19 - Write '1' to enable interrupt for RXSTARTED event

`pub fn txstarted(&mut self) -> TXSTARTED_W`[src]

Bit 20 - Write '1' to enable interrupt for TXSTARTED event

`pub fn write(&mut self) -> WRITE_W`[src]

Bit 25 - Write '1' to enable interrupt for WRITE event

`pub fn read(&mut self) -> READ_W`[src]

Bit 26 - Write '1' to enable interrupt for READ event

`impl W<u32, Reg<u32, _INTENCLR>>`[src]

`pub fn stopped(&mut self) -> STOPPED_W`[src]

Bit 1 - Write '1' to disable interrupt for STOPPED event

`pub fn error(&mut self) -> ERROR_W`[src]

Bit 9 - Write '1' to disable interrupt for ERROR event

`pub fn rxstarted(&mut self) -> RXSTARTED_W`[src]

Bit 19 - Write '1' to disable interrupt for RXSTARTED event

`pub fn txstarted(&mut self) -> TXSTARTED_W`[src]

Bit 20 - Write '1' to disable interrupt for TXSTARTED event

`pub fn write(&mut self) -> WRITE_W`[src]

Bit 25 - Write '1' to disable interrupt for WRITE event

`pub fn read(&mut self) -> READ_W`[src]

Bit 26 - Write '1' to disable interrupt for READ event

`impl W<u32, Reg<u32, _ERRORSRC>>`[src]

`pub fn overflow(&mut self) -> OVERFLOW_W`[src]

Bit 0 - RX buffer overflow detected, and prevented

`pub fn dnack(&mut self) -> DNACK_W`[src]

Bit 2 - NACK sent after receiving a data byte

`pub fn overread(&mut self) -> OVERREAD_W`[src]

Bit 3 - TX buffer over-read detected, and prevented

`impl W<u32, Reg<u32, _ENABLE>>`[src]

`pub fn enable(&mut self) -> ENABLE_W`[src]

Bits 0:3 - Enable or disable TWIS

`impl W<u32, Reg<u32, _ADDRESS>>`[src]

`pub fn address(&mut self) -> ADDRESS_W`[src]

Bits 0:6 - TWI slave address

`impl W<u32, Reg<u32, _CONFIG>>`[src]

`pub fn address0(&mut self) -> ADDRESS0_W`[src]

Bit 0 - Enable or disable address matching on ADDRESS[0]

`pub fn address1(&mut self) -> ADDRESS1_W`[src]

Bit 1 - Enable or disable address matching on ADDRESS[1]

`impl W<u32, Reg<u32, _ORC>>`[src]

`pub fn orc(&mut self) -> ORC_W`[src]

Bits 0:7 - Over-read character. Character sent out in case of an over-read of the transmit buffer.

`impl W<u32, Reg<u32, _RX>>`[src]

`pub fn crcerror(&mut self) -> CRCERROR_W`[src]

Bit 0 - No valid end of frame (EoF) detected

`pub fn paritystatus(&mut self) -> PARITYSTATUS_W`[src]

Bit 2 - Parity status of received frame

`pub fn overrun(&mut self) -> OVERRUN_W`[src]

Bit 3 - Overrun detected

`impl W<u32, Reg<u32, _FRAMECONFIG>>`[src]

`pub fn parity(&mut self) -> PARITY_W`[src]

Bit 0 - Indicates if parity is added to the frame

`pub fn discardmode(&mut self) -> DISCARDMODE_W`[src]

Bit 1 - Discarding unused bits at start or end of a frame

`pub fn sof(&mut self) -> SOF_W`[src]

Bit 2 - Adding SoF or not in TX frames

`pub fn crcmodetx(&mut self) -> CRCMODETX_W`[src]

Bit 4 - CRC mode for outgoing frames

`impl W<u32, Reg<u32, _AMOUNT>>`[src]

`pub fn txdatabits(&mut self) -> TXDATABITS_W`[src]

Bits 0:2 - Number of bits in the last or first byte read from RAM that shall be included in the frame (excluding parity bit).

`pub fn txdatabytes(&mut self) -> TXDATABYTES_W`[src]

Bits 3:11 - Number of complete bytes that shall be included in the frame, excluding CRC, parity and framing

`impl W<u32, Reg<u32, _FRAMECONFIG>>`[src]

`pub fn parity(&mut self) -> PARITY_W`[src]

Bit 0 - Indicates if parity expected in RX frame

`pub fn sof(&mut self) -> SOF_W`[src]

`pub fn fieldlost_sense(&mut self) -> FIELDLOST_SENSE_W`[src]

Bit 1 - Shortcut between FIELDLOST event and SENSE task

`pub fn txframeend_enablerxdata(&mut self) -> TXFRAMEEND_ENABLERXDATA_W`[src]

Bit 5 - Shortcut between TXFRAMEEND event and ENABLERXDATA task

`impl W<u32, Reg<u32, _INTEN>>`[src]

`pub fn ready(&mut self) -> READY_W`[src]

Bit 0 - Enable or disable interrupt for READY event

`pub fn fielddetected(&mut self) -> FIELDDETECTED_W`[src]

Bit 1 - Enable or disable interrupt for FIELDDETECTED event

`pub fn fieldlost(&mut self) -> FIELDLOST_W`[src]

Bit 2 - Enable or disable interrupt for FIELDLOST event

`pub fn txframestart(&mut self) -> TXFRAMESTART_W`[src]

Bit 3 - Enable or disable interrupt for TXFRAMESTART event

`pub fn txframeend(&mut self) -> TXFRAMEEND_W`[src]

Bit 4 - Enable or disable interrupt for TXFRAMEEND event

`pub fn rxframestart(&mut self) -> RXFRAMESTART_W`[src]

Bit 5 - Enable or disable interrupt for RXFRAMESTART event

`pub fn rxframeend(&mut self) -> RXFRAMEEND_W`[src]

Bit 6 - Enable or disable interrupt for RXFRAMEEND event

`pub fn error(&mut self) -> ERROR_W`[src]

Bit 7 - Enable or disable interrupt for ERROR event

`pub fn rxerror(&mut self) -> RXERROR_W`[src]

Bit 10 - Enable or disable interrupt for RXERROR event

`pub fn endrx(&mut self) -> ENDRX_W`[src]

Bit 11 - Enable or disable interrupt for ENDRX event

`pub fn endtx(&mut self) -> ENDTX_W`[src]

Bit 12 - Enable or disable interrupt for ENDTX event

`pub fn autocolresstarted(&mut self) -> AUTOCOLRESSTARTED_W`[src]

Bit 14 - Enable or disable interrupt for AUTOCOLRESSTARTED event

`pub fn collision(&mut self) -> COLLISION_W`[src]

Bit 18 - Enable or disable interrupt for COLLISION event

`pub fn selected(&mut self) -> SELECTED_W`[src]

Bit 19 - Enable or disable interrupt for SELECTED event

`pub fn started(&mut self) -> STARTED_W`[src]

Bit 20 - Enable or disable interrupt for STARTED event

`impl W<u32, Reg<u32, _INTENSET>>`[src]

`pub fn ready(&mut self) -> READY_W`[src]

Bit 0 - Write '1' to enable interrupt for READY event

`pub fn fielddetected(&mut self) -> FIELDDETECTED_W`[src]

Bit 1 - Write '1' to enable interrupt for FIELDDETECTED event

`pub fn fieldlost(&mut self) -> FIELDLOST_W`[src]

Bit 2 - Write '1' to enable interrupt for FIELDLOST event

`pub fn txframestart(&mut self) -> TXFRAMESTART_W`[src]

Bit 3 - Write '1' to enable interrupt for TXFRAMESTART event

`pub fn txframeend(&mut self) -> TXFRAMEEND_W`[src]

Bit 4 - Write '1' to enable interrupt for TXFRAMEEND event

`pub fn rxframestart(&mut self) -> RXFRAMESTART_W`[src]

Bit 5 - Write '1' to enable interrupt for RXFRAMESTART event

`pub fn rxframeend(&mut self) -> RXFRAMEEND_W`[src]

Bit 6 - Write '1' to enable interrupt for RXFRAMEEND event

`pub fn error(&mut self) -> ERROR_W`[src]

Bit 7 - Write '1' to enable interrupt for ERROR event

`pub fn rxerror(&mut self) -> RXERROR_W`[src]

Bit 10 - Write '1' to enable interrupt for RXERROR event

`pub fn endrx(&mut self) -> ENDRX_W`[src]

Bit 11 - Write '1' to enable interrupt for ENDRX event

`pub fn endtx(&mut self) -> ENDTX_W`[src]

Bit 12 - Write '1' to enable interrupt for ENDTX event

`pub fn autocolresstarted(&mut self) -> AUTOCOLRESSTARTED_W`[src]

Bit 14 - Write '1' to enable interrupt for AUTOCOLRESSTARTED event

`pub fn collision(&mut self) -> COLLISION_W`[src]

Bit 18 - Write '1' to enable interrupt for COLLISION event

`pub fn selected(&mut self) -> SELECTED_W`[src]

Bit 19 - Write '1' to enable interrupt for SELECTED event

`pub fn started(&mut self) -> STARTED_W`[src]

Bit 20 - Write '1' to enable interrupt for STARTED event

`impl W<u32, Reg<u32, _INTENCLR>>`[src]

`pub fn ready(&mut self) -> READY_W`[src]

Bit 0 - Write '1' to disable interrupt for READY event

`pub fn fielddetected(&mut self) -> FIELDDETECTED_W`[src]

Bit 1 - Write '1' to disable interrupt for FIELDDETECTED event

`pub fn fieldlost(&mut self) -> FIELDLOST_W`[src]

Bit 2 - Write '1' to disable interrupt for FIELDLOST event

`pub fn txframestart(&mut self) -> TXFRAMESTART_W`[src]

Bit 3 - Write '1' to disable interrupt for TXFRAMESTART event

`pub fn txframeend(&mut self) -> TXFRAMEEND_W`[src]

Bit 4 - Write '1' to disable interrupt for TXFRAMEEND event

`pub fn rxframestart(&mut self) -> RXFRAMESTART_W`[src]

Bit 5 - Write '1' to disable interrupt for RXFRAMESTART event

`pub fn rxframeend(&mut self) -> RXFRAMEEND_W`[src]

Bit 6 - Write '1' to disable interrupt for RXFRAMEEND event

`pub fn error(&mut self) -> ERROR_W`[src]

Bit 7 - Write '1' to disable interrupt for ERROR event

`pub fn rxerror(&mut self) -> RXERROR_W`[src]

Bit 10 - Write '1' to disable interrupt for RXERROR event

`pub fn endrx(&mut self) -> ENDRX_W`[src]

Bit 11 - Write '1' to disable interrupt for ENDRX event

`pub fn endtx(&mut self) -> ENDTX_W`[src]

Bit 12 - Write '1' to disable interrupt for ENDTX event

`pub fn autocolresstarted(&mut self) -> AUTOCOLRESSTARTED_W`[src]

Bit 14 - Write '1' to disable interrupt for AUTOCOLRESSTARTED event

`pub fn collision(&mut self) -> COLLISION_W`[src]

Bit 18 - Write '1' to disable interrupt for COLLISION event

`pub fn selected(&mut self) -> SELECTED_W`[src]

Bit 19 - Write '1' to disable interrupt for SELECTED event

`pub fn started(&mut self) -> STARTED_W`[src]

Bit 20 - Write '1' to disable interrupt for STARTED event

`impl W<u32, Reg<u32, _ERRORSTATUS>>`[src]

`pub fn framedelaytimeout(&mut self) -> FRAMEDELAYTIMEOUT_W`[src]

Bit 0 - No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX

`impl W<u32, Reg<u32, _FRAMEDELAYMIN>>`[src]

`pub fn framedelaymin(&mut self) -> FRAMEDELAYMIN_W`[src]

Bits 0:15 - Minimum frame delay in number of 13.56 MHz clocks

`impl W<u32, Reg<u32, _FRAMEDELAYMAX>>`[src]

`pub fn framedelaymax(&mut self) -> FRAMEDELAYMAX_W`[src]

Bits 0:19 - Maximum frame delay in number of 13.56 MHz clocks

`impl W<u32, Reg<u32, _FRAMEDELAYMODE>>`[src]

`pub fn framedelaymode(&mut self) -> FRAMEDELAYMODE_W`[src]

Bits 0:1 - Configuration register for the Frame Delay Timer

`impl W<u32, Reg<u32, _PACKETPTR>>`[src]

`pub fn ptr(&mut self) -> PTR_W`[src]

Bits 0:31 - Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte-aligned RAM address.

`impl W<u32, Reg<u32, _MAXLEN>>`[src]

`pub fn maxlen(&mut self) -> MAXLEN_W`[src]

Bits 0:8 - Size of the RAM buffer allocated to TXD and RXD data storage each

`impl W<u32, Reg<u32, _NFCID1_LAST>>`[src]

`pub fn nfcid1_z(&mut self) -> NFCID1_Z_W`[src]

Bits 0:7 - NFCID1 byte Z (very last byte sent)

`pub fn nfcid1_y(&mut self) -> NFCID1_Y_W`[src]

Bits 8:15 - NFCID1 byte Y

`pub fn nfcid1_x(&mut self) -> NFCID1_X_W`[src]

Bits 16:23 - NFCID1 byte X

`pub fn nfcid1_w(&mut self) -> NFCID1_W_W`[src]

Bits 24:31 - NFCID1 byte W

`impl W<u32, Reg<u32, _NFCID1_2ND_LAST>>`[src]

`pub fn nfcid1_v(&mut self) -> NFCID1_V_W`[src]

Bits 0:7 - NFCID1 byte V

`pub fn nfcid1_u(&mut self) -> NFCID1_U_W`[src]

Bits 8:15 - NFCID1 byte U

`pub fn nfcid1_t(&mut self) -> NFCID1_T_W`[src]

Bits 16:23 - NFCID1 byte T

`impl W<u32, Reg<u32, _NFCID1_3RD_LAST>>`[src]

`pub fn nfcid1_s(&mut self) -> NFCID1_S_W`[src]

Bits 0:7 - NFCID1 byte S

`pub fn nfcid1_r(&mut self) -> NFCID1_R_W`[src]

Bits 8:15 - NFCID1 byte R

`pub fn nfcid1_q(&mut self) -> NFCID1_Q_W`[src]

Bits 16:23 - NFCID1 byte Q

`impl W<u32, Reg<u32, _AUTOCOLRESCONFIG>>`[src]

`pub fn mode(&mut self) -> MODE_W`[src]

Bit 0 - Enables/disables auto collision resolution

`impl W<u32, Reg<u32, _SENSRES>>`[src]

`pub fn bitframesdd(&mut self) -> BITFRAMESDD_W`[src]

Bits 0:4 - Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification

`pub fn rfu5(&mut self) -> RFU5_W`[src]

Bit 5 - Reserved for future use. Shall be 0.

`pub fn nfcidsize(&mut self) -> NFCIDSIZE_W`[src]

Bits 6:7 - NFCID1 size. This value is used by the auto collision resolution engine.

`pub fn platfconfig(&mut self) -> PLATFCONFIG_W`[src]

Bits 8:11 - Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification

`pub fn rfu74(&mut self) -> RFU74_W`[src]

Bits 12:15 - Reserved for future use. Shall be 0.

`impl W<u32, Reg<u32, _SELRES>>`[src]

`pub fn rfu10(&mut self) -> RFU10_W`[src]

Bits 0:1 - Reserved for future use. Shall be 0.

`pub fn cascade(&mut self) -> CASCADE_W`[src]

Bit 2 - Cascade as defined by the b3 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification (controlled by hardware, shall be 0)

`pub fn rfu43(&mut self) -> RFU43_W`[src]

Bits 3:4 - Reserved for future use. Shall be 0.

`pub fn protocol(&mut self) -> PROTOCOL_W`[src]

`impl W<u32, Reg<u32, _INTENSET>>`[src]

`pub fn in0(&mut self) -> IN0_W`[src]

Bit 0 - Write '1' to enable interrupt for IN[0] event

`pub fn in1(&mut self) -> IN1_W`[src]

Bit 1 - Write '1' to enable interrupt for IN[1] event

`pub fn in2(&mut self) -> IN2_W`[src]

Bit 2 - Write '1' to enable interrupt for IN[2] event

`pub fn in3(&mut self) -> IN3_W`[src]

Bit 3 - Write '1' to enable interrupt for IN[3] event

`pub fn in4(&mut self) -> IN4_W`[src]

Bit 4 - Write '1' to enable interrupt for IN[4] event

`pub fn in5(&mut self) -> IN5_W`[src]

Bit 5 - Write '1' to enable interrupt for IN[5] event

`pub fn in6(&mut self) -> IN6_W`[src]

Bit 6 - Write '1' to enable interrupt for IN[6] event

`pub fn in7(&mut self) -> IN7_W`[src]

Bit 7 - Write '1' to enable interrupt for IN[7] event

`pub fn port(&mut self) -> PORT_W`[src]

Bit 31 - Write '1' to enable interrupt for PORT event

`impl W<u32, Reg<u32, _INTENCLR>>`[src]

`pub fn in0(&mut self) -> IN0_W`[src]

Bit 0 - Write '1' to disable interrupt for IN[0] event

`pub fn in1(&mut self) -> IN1_W`[src]

Bit 1 - Write '1' to disable interrupt for IN[1] event

`pub fn in2(&mut self) -> IN2_W`[src]

Bit 2 - Write '1' to disable interrupt for IN[2] event

`pub fn in3(&mut self) -> IN3_W`[src]

Bit 3 - Write '1' to disable interrupt for IN[3] event

`pub fn in4(&mut self) -> IN4_W`[src]

Bit 4 - Write '1' to disable interrupt for IN[4] event

`pub fn in5(&mut self) -> IN5_W`[src]

Bit 5 - Write '1' to disable interrupt for IN[5] event

`pub fn in6(&mut self) -> IN6_W`[src]

Bit 6 - Write '1' to disable interrupt for IN[6] event

`pub fn in7(&mut self) -> IN7_W`[src]

Bit 7 - Write '1' to disable interrupt for IN[7] event

`pub fn port(&mut self) -> PORT_W`[src]

Bit 31 - Write '1' to disable interrupt for PORT event

`impl W<u32, Reg<u32, _CONFIG>>`[src]

`pub fn mode(&mut self) -> MODE_W`[src]

Bits 0:1 - Mode

`pub fn psel(&mut self) -> PSEL_W`[src]

Bits 8:12 - GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event

`pub fn port(&mut self) -> PORT_W`[src]

Bit 13 - Port number

`pub fn polarity(&mut self) -> POLARITY_W`[src]

Bits 16:17 - When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event.

`pub fn outinit(&mut self) -> OUTINIT_W`[src]

Bit 20 - When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect.

`impl W<u32, Reg<u32, _LIMITH>>`[src]

`pub fn limith(&mut self) -> LIMITH_W`[src]

Bit 0

`impl W<u32, Reg<u32, _LIMITL>>`[src]

`pub fn limitl(&mut self) -> LIMITL_W`[src]

Bit 0

`impl W<u32, Reg<u32, _PSELP>>`[src]

`pub fn pselp(&mut self) -> PSELP_W`[src]

Bits 0:4 - Analog positive input channel

`impl W<u32, Reg<u32, _PSELN>>`[src]

`pub fn pseln(&mut self) -> PSELN_W`[src]

Bits 0:4 - Analog negative input, enables differential channel

`impl W<u32, Reg<u32, _CONFIG>>`[src]

`pub fn resp(&mut self) -> RESP_W`[src]

Bits 0:1 - Positive channel resistor control

`pub fn resn(&mut self) -> RESN_W`[src]

Bits 4:5 - Negative channel resistor control

`pub fn gain(&mut self) -> GAIN_W`[src]

Bits 8:10 - Gain control

`pub fn refsel(&mut self) -> REFSEL_W`[src]

Bit 12 - Reference control

`pub fn tacq(&mut self) -> TACQ_W`[src]

Bits 16:18 - Acquisition time, the time the SAADC uses to sample the input voltage

`pub fn mode(&mut self) -> MODE_W`[src]

Bit 20 - Enable differential mode

`pub fn burst(&mut self) -> BURST_W`[src]

Bit 24 - Enable burst mode

`impl W<u32, Reg<u32, _LIMIT>>`[src]

`pub fn low(&mut self) -> LOW_W`[src]

`pub fn end(&mut self) -> END_W`[src]

Bit 1 - Enable or disable interrupt for END event

`pub fn done(&mut self) -> DONE_W`[src]

Bit 2 - Enable or disable interrupt for DONE event

`pub fn resultdone(&mut self) -> RESULTDONE_W`[src]

Bit 3 - Enable or disable interrupt for RESULTDONE event

`pub fn calibratedone(&mut self) -> CALIBRATEDONE_W`[src]

Bit 4 - Enable or disable interrupt for CALIBRATEDONE event

`pub fn stopped(&mut self) -> STOPPED_W`[src]

Bit 5 - Enable or disable interrupt for STOPPED event

`pub fn ch0limith(&mut self) -> CH0LIMITH_W`[src]

Bit 6 - Enable or disable interrupt for CH[0].LIMITH event

`pub fn ch0limitl(&mut self) -> CH0LIMITL_W`[src]

Bit 7 - Enable or disable interrupt for CH[0].LIMITL event

`pub fn ch1limith(&mut self) -> CH1LIMITH_W`[src]

Bit 8 - Enable or disable interrupt for CH[1].LIMITH event

`pub fn ch1limitl(&mut self) -> CH1LIMITL_W`[src]

Bit 9 - Enable or disable interrupt for CH[1].LIMITL event

`pub fn ch2limith(&mut self) -> CH2LIMITH_W`[src]

Bit 10 - Enable or disable interrupt for CH[2].LIMITH event

`pub fn ch2limitl(&mut self) -> CH2LIMITL_W`[src]

Bit 11 - Enable or disable interrupt for CH[2].LIMITL event

`pub fn ch3limith(&mut self) -> CH3LIMITH_W`[src]

Bit 12 - Enable or disable interrupt for CH[3].LIMITH event

`pub fn ch3limitl(&mut self) -> CH3LIMITL_W`[src]

Bit 13 - Enable or disable interrupt for CH[3].LIMITL event

`pub fn ch4limith(&mut self) -> CH4LIMITH_W`[src]

Bit 14 - Enable or disable interrupt for CH[4].LIMITH event

`pub fn ch4limitl(&mut self) -> CH4LIMITL_W`[src]

Bit 15 - Enable or disable interrupt for CH[4].LIMITL event

`pub fn ch5limith(&mut self) -> CH5LIMITH_W`[src]

Bit 16 - Enable or disable interrupt for CH[5].LIMITH event

`pub fn ch5limitl(&mut self) -> CH5LIMITL_W`[src]

Bit 17 - Enable or disable interrupt for CH[5].LIMITL event

`pub fn ch6limith(&mut self) -> CH6LIMITH_W`[src]

Bit 18 - Enable or disable interrupt for CH[6].LIMITH event

`pub fn ch6limitl(&mut self) -> CH6LIMITL_W`[src]

Bit 19 - Enable or disable interrupt for CH[6].LIMITL event

`pub fn ch7limith(&mut self) -> CH7LIMITH_W`[src]

Bit 20 - Enable or disable interrupt for CH[7].LIMITH event

`pub fn ch7limitl(&mut self) -> CH7LIMITL_W`[src]

Bit 21 - Enable or disable interrupt for CH[7].LIMITL event

`impl W<u32, Reg<u32, _INTENSET>>`[src]

`pub fn started(&mut self) -> STARTED_W`[src]

Bit 0 - Write '1' to enable interrupt for STARTED event

`pub fn end(&mut self) -> END_W`[src]

Bit 1 - Write '1' to enable interrupt for END event

`pub fn done(&mut self) -> DONE_W`[src]

Bit 2 - Write '1' to enable interrupt for DONE event

`pub fn resultdone(&mut self) -> RESULTDONE_W`[src]

Bit 3 - Write '1' to enable interrupt for RESULTDONE event

`pub fn calibratedone(&mut self) -> CALIBRATEDONE_W`[src]

Bit 4 - Write '1' to enable interrupt for CALIBRATEDONE event

`pub fn stopped(&mut self) -> STOPPED_W`[src]

Bit 5 - Write '1' to enable interrupt for STOPPED event

`pub fn ch0limith(&mut self) -> CH0LIMITH_W`[src]

Bit 6 - Write '1' to enable interrupt for CH[0].LIMITH event

`pub fn ch0limitl(&mut self) -> CH0LIMITL_W`[src]

Bit 7 - Write '1' to enable interrupt for CH[0].LIMITL event

`pub fn ch1limith(&mut self) -> CH1LIMITH_W`[src]

Bit 8 - Write '1' to enable interrupt for CH[1].LIMITH event

`pub fn ch1limitl(&mut self) -> CH1LIMITL_W`[src]

Bit 9 - Write '1' to enable interrupt for CH[1].LIMITL event

`pub fn ch2limith(&mut self) -> CH2LIMITH_W`[src]

Bit 10 - Write '1' to enable interrupt for CH[2].LIMITH event

`pub fn ch2limitl(&mut self) -> CH2LIMITL_W`[src]

Bit 11 - Write '1' to enable interrupt for CH[2].LIMITL event

`pub fn ch3limith(&mut self) -> CH3LIMITH_W`[src]

Bit 12 - Write '1' to enable interrupt for CH[3].LIMITH event

`pub fn ch3limitl(&mut self) -> CH3LIMITL_W`[src]

Bit 13 - Write '1' to enable interrupt for CH[3].LIMITL event

`pub fn ch4limith(&mut self) -> CH4LIMITH_W`[src]

Bit 14 - Write '1' to enable interrupt for CH[4].LIMITH event

`pub fn ch4limitl(&mut self) -> CH4LIMITL_W`[src]

Bit 15 - Write '1' to enable interrupt for CH[4].LIMITL event

`pub fn ch5limith(&mut self) -> CH5LIMITH_W`[src]

Bit 16 - Write '1' to enable interrupt for CH[5].LIMITH event

`pub fn ch5limitl(&mut self) -> CH5LIMITL_W`[src]

Bit 17 - Write '1' to enable interrupt for CH[5].LIMITL event

`pub fn ch6limith(&mut self) -> CH6LIMITH_W`[src]

Bit 18 - Write '1' to enable interrupt for CH[6].LIMITH event

`pub fn ch6limitl(&mut self) -> CH6LIMITL_W`[src]

Bit 19 - Write '1' to enable interrupt for CH[6].LIMITL event

`pub fn ch7limith(&mut self) -> CH7LIMITH_W`[src]

Bit 20 - Write '1' to enable interrupt for CH[7].LIMITH event

`pub fn ch7limitl(&mut self) -> CH7LIMITL_W`[src]

Bit 21 - Write '1' to enable interrupt for CH[7].LIMITL event

`impl W<u32, Reg<u32, _INTENCLR>>`[src]

`pub fn started(&mut self) -> STARTED_W`[src]

Bit 0 - Write '1' to disable interrupt for STARTED event

`pub fn end(&mut self) -> END_W`[src]

Bit 1 - Write '1' to disable interrupt for END event

`pub fn done(&mut self) -> DONE_W`[src]

Bit 2 - Write '1' to disable interrupt for DONE event

`pub fn resultdone(&mut self) -> RESULTDONE_W`[src]

Bit 3 - Write '1' to disable interrupt for RESULTDONE event

`pub fn calibratedone(&mut self) -> CALIBRATEDONE_W`[src]

Bit 4 - Write '1' to disable interrupt for CALIBRATEDONE event

`pub fn stopped(&mut self) -> STOPPED_W`[src]

Bit 5 - Write '1' to disable interrupt for STOPPED event

`pub fn ch0limith(&mut self) -> CH0LIMITH_W`[src]

Bit 6 - Write '1' to disable interrupt for CH[0].LIMITH event

`pub fn ch0limitl(&mut self) -> CH0LIMITL_W`[src]

Bit 7 - Write '1' to disable interrupt for CH[0].LIMITL event

`pub fn ch1limith(&mut self) -> CH1LIMITH_W`[src]

Bit 8 - Write '1' to disable interrupt for CH[1].LIMITH event

`pub fn ch1limitl(&mut self) -> CH1LIMITL_W`[src]

Bit 9 - Write '1' to disable interrupt for CH[1].LIMITL event

`pub fn ch2limith(&mut self) -> CH2LIMITH_W`[src]

Bit 10 - Write '1' to disable interrupt for CH[2].LIMITH event

`pub fn ch2limitl(&mut self) -> CH2LIMITL_W`[src]

Bit 11 - Write '1' to disable interrupt for CH[2].LIMITL event

`pub fn ch3limith(&mut self) -> CH3LIMITH_W`[src]

Bit 12 - Write '1' to disable interrupt for CH[3].LIMITH event

`pub fn ch3limitl(&mut self) -> CH3LIMITL_W`[src]

Bit 13 - Write '1' to disable interrupt for CH[3].LIMITL event

`pub fn ch4limith(&mut self) -> CH4LIMITH_W`[src]

Bit 14 - Write '1' to disable interrupt for CH[4].LIMITH event

`pub fn ch4limitl(&mut self) -> CH4LIMITL_W`[src]

Bit 15 - Write '1' to disable interrupt for CH[4].LIMITL event

`pub fn ch5limith(&mut self) -> CH5LIMITH_W`[src]

Bit 16 - Write '1' to disable interrupt for CH[5].LIMITH event

`pub fn ch5limitl(&mut self) -> CH5LIMITL_W`[src]

Bit 17 - Write '1' to disable interrupt for CH[5].LIMITL event

`pub fn ch6limith(&mut self) -> CH6LIMITH_W`[src]

Bit 18 - Write '1' to disable interrupt for CH[6].LIMITH event

`pub fn ch6limitl(&mut self) -> CH6LIMITL_W`[src]

Bit 19 - Write '1' to disable interrupt for CH[6].LIMITL event

`pub fn ch7limith(&mut self) -> CH7LIMITH_W`[src]

Bit 20 - Write '1' to disable interrupt for CH[7].LIMITH event

`pub fn ch7limitl(&mut self) -> CH7LIMITL_W`[src]

Bit 21 - Write '1' to disable interrupt for CH[7].LIMITL event

`impl W<u32, Reg<u32, _ENABLE>>`[src]

`pub fn enable(&mut self) -> ENABLE_W`[src]

Bit 0 - Enable or disable SAADC

`impl W<u32, Reg<u32, _RESOLUTION>>`[src]

`pub fn val(&mut self) -> VAL_W`[src]

Bits 0:2 - Set the resolution

`impl W<u32, Reg<u32, _OVERSAMPLE>>`[src]

`pub fn oversample(&mut self) -> OVERSAMPLE_W`[src]

Bits 0:3 - Oversample control

`impl W<u32, Reg<u32, _SAMPLERATE>>`[src]

`pub fn cc(&mut self) -> CC_W`[src]

`impl W<u32, Reg<u32, _SHORTS>>`[src]

`pub fn compare0_clear(&mut self) -> COMPARE0_CLEAR_W`[src]

Bit 0 - Shortcut between COMPARE[0] event and CLEAR task

`pub fn compare1_clear(&mut self) -> COMPARE1_CLEAR_W`[src]

Bit 1 - Shortcut between COMPARE[1] event and CLEAR task

`pub fn compare2_clear(&mut self) -> COMPARE2_CLEAR_W`[src]

Bit 2 - Shortcut between COMPARE[2] event and CLEAR task

`pub fn compare3_clear(&mut self) -> COMPARE3_CLEAR_W`[src]

Bit 3 - Shortcut between COMPARE[3] event and CLEAR task

`pub fn compare0_stop(&mut self) -> COMPARE0_STOP_W`[src]

Bit 8 - Shortcut between COMPARE[0] event and STOP task

`pub fn compare1_stop(&mut self) -> COMPARE1_STOP_W`[src]

Bit 9 - Shortcut between COMPARE[1] event and STOP task

`pub fn compare2_stop(&mut self) -> COMPARE2_STOP_W`[src]

Bit 10 - Shortcut between COMPARE[2] event and STOP task

`pub fn compare3_stop(&mut self) -> COMPARE3_STOP_W`[src]

Bit 11 - Shortcut between COMPARE[3] event and STOP task

`impl W<u32, Reg<u32, _INTENSET>>`[src]

`pub fn compare0(&mut self) -> COMPARE0_W`[src]

Bit 16 - Write '1' to enable interrupt for COMPARE[0] event

`pub fn compare1(&mut self) -> COMPARE1_W`[src]

Bit 17 - Write '1' to enable interrupt for COMPARE[1] event

`pub fn compare2(&mut self) -> COMPARE2_W`[src]

Bit 18 - Write '1' to enable interrupt for COMPARE[2] event

`pub fn compare3(&mut self) -> COMPARE3_W`[src]

Bit 19 - Write '1' to enable interrupt for COMPARE[3] event

`impl W<u32, Reg<u32, _INTENCLR>>`[src]

`pub fn compare0(&mut self) -> COMPARE0_W`[src]

Bit 16 - Write '1' to disable interrupt for COMPARE[0] event

`pub fn compare1(&mut self) -> COMPARE1_W`[src]

Bit 17 - Write '1' to disable interrupt for COMPARE[1] event

`pub fn compare2(&mut self) -> COMPARE2_W`[src]

`impl W<u32, Reg<u32, _INTENSET>>`[src]

`pub fn tick(&mut self) -> TICK_W`[src]

Bit 0 - Write '1' to enable interrupt for TICK event

`pub fn ovrflw(&mut self) -> OVRFLW_W`[src]

Bit 1 - Write '1' to enable interrupt for OVRFLW event

`pub fn compare0(&mut self) -> COMPARE0_W`[src]

Bit 16 - Write '1' to enable interrupt for COMPARE[0] event

`pub fn compare1(&mut self) -> COMPARE1_W`[src]

Bit 17 - Write '1' to enable interrupt for COMPARE[1] event

`pub fn compare2(&mut self) -> COMPARE2_W`[src]

Bit 18 - Write '1' to enable interrupt for COMPARE[2] event

`pub fn compare3(&mut self) -> COMPARE3_W`[src]

Bit 19 - Write '1' to enable interrupt for COMPARE[3] event

`impl W<u32, Reg<u32, _INTENCLR>>`[src]

`pub fn tick(&mut self) -> TICK_W`[src]

Bit 0 - Write '1' to disable interrupt for TICK event

`pub fn ovrflw(&mut self) -> OVRFLW_W`[src]

Bit 1 - Write '1' to disable interrupt for OVRFLW event

`pub fn compare0(&mut self) -> COMPARE0_W`[src]

Bit 16 - Write '1' to disable interrupt for COMPARE[0] event

`pub fn compare1(&mut self) -> COMPARE1_W`[src]

Bit 17 - Write '1' to disable interrupt for COMPARE[1] event

`pub fn compare2(&mut self) -> COMPARE2_W`[src]

Bit 18 - Write '1' to disable interrupt for COMPARE[2] event

`pub fn compare3(&mut self) -> COMPARE3_W`[src]

Bit 19 - Write '1' to disable interrupt for COMPARE[3] event

`impl W<u32, Reg<u32, _EVTEN>>`[src]

`pub fn tick(&mut self) -> TICK_W`[src]

Bit 0 - Enable or disable event routing for TICK event

`pub fn ovrflw(&mut self) -> OVRFLW_W`[src]

Bit 1 - Enable or disable event routing for OVRFLW event

`pub fn compare0(&mut self) -> COMPARE0_W`[src]

Bit 16 - Enable or disable event routing for COMPARE[0] event

`pub fn compare1(&mut self) -> COMPARE1_W`[src]

Bit 17 - Enable or disable event routing for COMPARE[1] event

`pub fn compare2(&mut self) -> COMPARE2_W`[src]

Bit 18 - Enable or disable event routing for COMPARE[2] event

`pub fn compare3(&mut self) -> COMPARE3_W`[src]

Bit 19 - Enable or disable event routing for COMPARE[3] event

`impl W<u32, Reg<u32, _EVTENSET>>`[src]

`pub fn tick(&mut self) -> TICK_W`[src]

Bit 0 - Write '1' to enable event routing for TICK event

`pub fn ovrflw(&mut self) -> OVRFLW_W`[src]

Bit 1 - Write '1' to enable event routing for OVRFLW event

`pub fn compare0(&mut self) -> COMPARE0_W`[src]

Bit 16 - Write '1' to enable event routing for COMPARE[0] event

`pub fn compare1(&mut self) -> COMPARE1_W`[src]

Bit 17 - Write '1' to enable event routing for COMPARE[1] event

`pub fn compare2(&mut self) -> COMPARE2_W`[src]

Bit 18 - Write '1' to enable event routing for COMPARE[2] event

`pub fn compare3(&mut self) -> COMPARE3_W`[src]

Bit 19 - Write '1' to enable event routing for COMPARE[3] event

`impl W<u32, Reg<u32, _EVTENCLR>>`[src]

`pub fn tick(&mut self) -> TICK_W`[src]

Bit 0 - Write '1' to disable event routing for TICK event

`pub fn ovrflw(&mut self) -> OVRFLW_W`[src]

Bit 1 - Write '1' to disable event routing for OVRFLW event

`pub fn compare0(&mut self) -> COMPARE0_W`[src]

Bit 16 - Write '1' to disable event routing for COMPARE[0] event

`pub fn compare1(&mut self) -> COMPARE1_W`[src]

Bit 17 - Write '1' to disable event routing for COMPARE[1] event

`pub fn compare2(&mut self) -> COMPARE2_W`[src]

`impl W<u32, Reg<u32, _INTENSET>>`[src]

`pub fn endecb(&mut self) -> ENDECB_W`[src]

Bit 0 - Write '1' to enable interrupt for ENDECB event

`pub fn errorecb(&mut self) -> ERRORECB_W`[src]

Bit 1 - Write '1' to enable interrupt for ERRORECB event

`impl W<u32, Reg<u32, _INTENCLR>>`[src]

`pub fn endecb(&mut self) -> ENDECB_W`[src]

`pub fn resolved(&mut self) -> RESOLVED_W`[src]

Bit 1 - Write '1' to enable interrupt for RESOLVED event

`pub fn notresolved(&mut self) -> NOTRESOLVED_W`[src]

Bit 2 - Write '1' to enable interrupt for NOTRESOLVED event

`impl W<u32, Reg<u32, _INTENCLR>>`[src]

`pub fn end(&mut self) -> END_W`[src]

Bit 0 - Write '1' to disable interrupt for END event

`pub fn resolved(&mut self) -> RESOLVED_W`[src]

`impl W<u32, Reg<u32, _INTENSET>>`[src]

`pub fn endksgen(&mut self) -> ENDKSGEN_W`[src]

Bit 0 - Write '1' to enable interrupt for ENDKSGEN event

`pub fn endcrypt(&mut self) -> ENDCRYPT_W`[src]

Bit 1 - Write '1' to enable interrupt for ENDCRYPT event

`pub fn error(&mut self) -> ERROR_W`[src]

Bit 2 - Write '1' to enable interrupt for ERROR event

`impl W<u32, Reg<u32, _INTENCLR>>`[src]

`pub fn endksgen(&mut self) -> ENDKSGEN_W`[src]

Bit 0 - Write '1' to disable interrupt for ENDKSGEN event

`pub fn endcrypt(&mut self) -> ENDCRYPT_W`[src]

Bit 1 - Write '1' to disable interrupt for ENDCRYPT event

`pub fn error(&mut self) -> ERROR_W`[src]

Bit 2 - Write '1' to disable interrupt for ERROR event

`impl W<u32, Reg<u32, _ENABLE>>`[src]

`pub fn enable(&mut self) -> ENABLE_W`[src]

Bits 0:1 - Enable or disable CCM

`impl W<u32, Reg<u32, _MODE>>`[src]

`pub fn mode(&mut self) -> MODE_W`[src]

Bit 0 - The mode of operation to be used. The settings in this register apply whenever either the KSGEN or CRYPT tasks are triggered.

`pub fn datarate(&mut self) -> DATARATE_W`[src]

Bits 16:17 - Radio data rate that the CCM shall run synchronous with

`pub fn length(&mut self) -> LENGTH_W`[src]

Bit 24 - Packet length configuration

`impl W<u32, Reg<u32, _CNFPTR>>`[src]

`pub fn cnfptr(&mut self) -> CNFPTR_W`[src]

Bits 0:31 - Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview)

`impl W<u32, Reg<u32, _INPTR>>`[src]

`pub fn inptr(&mut self) -> INPTR_W`[src]

Bits 0:31 - Input pointer

`impl W<u32, Reg<u32, _OUTPTR>>`[src]

`pub fn outptr(&mut self) -> OUTPTR_W`[src]

Bits 0:31 - Output pointer

`impl W<u32, Reg<u32, _SCRATCHPTR>>`[src]

`pub fn scratchptr(&mut self) -> SCRATCHPTR_W`[src]

Bits 0:31 - Pointer to a scratch data area used for temporary storage during key-stream generation, MIC generation and encryption/decryption.

`impl W<u32, Reg<u32, _MAXPACKETSIZE>>`[src]

`pub fn maxpacketsize(&mut self) -> MAXPACKETSIZE_W`[src]

Bits 0:7 - Length of key-stream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted.

`impl W<u32, Reg<u32, _RATEOVERRIDE>>`[src]

`pub fn rateoverride(&mut self) -> RATEOVERRIDE_W`[src]

Bits 0:1 - Data rate override setting.

`impl W<u32, Reg<u32, _TASKS_START>>`[src]

`pub fn tasks_start(&mut self) -> TASKS_START_W`[src]

Bit 0

`impl W<u32, Reg<u32, _EVENTS_TIMEOUT>>`[src]

`pub fn events_timeout(&mut self) -> EVENTS_TIMEOUT_W`[src]

Bit 0

`impl W<u32, Reg<u32, _INTENSET>>`[src]

`pub fn timeout(&mut self) -> TIMEOUT_W`[src]

Bit 0 - Write '1' to enable interrupt for TIMEOUT event

`impl W<u32, Reg<u32, _INTENCLR>>`[src]

`pub fn timeout(&mut self) -> TIMEOUT_W`[src]

Bit 0 - Write '1' to disable interrupt for TIMEOUT event

`impl W<u32, Reg<u32, _CRV>>`[src]

`pub fn crv(&mut self) -> CRV_W`[src]

Bits 0:31 - Counter reload value in number of cycles of the 32.768 kHz clock

`impl W<u32, Reg<u32, _RREN>>`[src]

`pub fn rr0(&mut self) -> RR0_W`[src]

Bit 0 - Enable or disable RR[0] register

`pub fn rr1(&mut self) -> RR1_W`[src]

Bit 1 - Enable or disable RR[1] register

`pub fn rr2(&mut self) -> RR2_W`[src]

Bit 2 - Enable or disable RR[2] register

`pub fn rr3(&mut self) -> RR3_W`[src]

Bit 3 - Enable or disable RR[3] register

`pub fn rr4(&mut self) -> RR4_W`[src]

Bit 4 - Enable or disable RR[4] register

`pub fn rr5(&mut self) -> RR5_W`[src]

Bit 5 - Enable or disable RR[5] register

`pub fn rr6(&mut self) -> RR6_W`[src]

Bit 6 - Enable or disable RR[6] register

`pub fn rr7(&mut self) -> RR7_W`[src]

Bit 7 - Enable or disable RR[7] register

`impl W<u32, Reg<u32, _CONFIG>>`[src]

`pub fn sleep(&mut self) -> SLEEP_W`[src]

Bit 0 - Configure the watchdog to either be paused, or kept running, while the CPU is sleeping

`pub fn halt(&mut self) -> HALT_W`[src]

Bit 3 - Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger

`pub fn samplerdy_stop(&mut self) -> SAMPLERDY_STOP_W`[src]

Bit 1 - Shortcut between SAMPLERDY event and STOP task

`pub fn reportrdy_rdclracc(&mut self) -> REPORTRDY_RDCLRACC_W`[src]

Bit 2 - Shortcut between REPORTRDY event and RDCLRACC task

`pub fn reportrdy_stop(&mut self) -> REPORTRDY_STOP_W`[src]

Bit 3 - Shortcut between REPORTRDY event and STOP task

`pub fn dblrdy_rdclrdbl(&mut self) -> DBLRDY_RDCLRDBL_W`[src]

Bit 4 - Shortcut between DBLRDY event and RDCLRDBL task

`pub fn dblrdy_stop(&mut self) -> DBLRDY_STOP_W`[src]

Bit 5 - Shortcut between DBLRDY event and STOP task

`pub fn samplerdy_readclracc(&mut self) -> SAMPLERDY_READCLRACC_W`[src]

Bit 6 - Shortcut between SAMPLERDY event and READCLRACC task

`impl W<u32, Reg<u32, _INTENSET>>`[src]

`pub fn samplerdy(&mut self) -> SAMPLERDY_W`[src]

Bit 0 - Write '1' to enable interrupt for SAMPLERDY event

`pub fn reportrdy(&mut self) -> REPORTRDY_W`[src]

Bit 1 - Write '1' to enable interrupt for REPORTRDY event

`pub fn accof(&mut self) -> ACCOF_W`[src]

Bit 2 - Write '1' to enable interrupt for ACCOF event

`pub fn dblrdy(&mut self) -> DBLRDY_W`[src]

Bit 3 - Write '1' to enable interrupt for DBLRDY event

`pub fn stopped(&mut self) -> STOPPED_W`[src]

Bit 4 - Write '1' to enable interrupt for STOPPED event

`impl W<u32, Reg<u32, _INTENCLR>>`[src]

`pub fn samplerdy(&mut self) -> SAMPLERDY_W`[src]

Bit 0 - Write '1' to disable interrupt for SAMPLERDY event

`pub fn reportrdy(&mut self) -> REPORTRDY_W`[src]

Bit 1 - Write '1' to disable interrupt for REPORTRDY event

`pub fn accof(&mut self) -> ACCOF_W`[src]

Bit 2 - Write '1' to disable interrupt for ACCOF event

`pub fn dblrdy(&mut self) -> DBLRDY_W`[src]

`impl W<u32, Reg<u32, _SHORTS>>`[src]

`pub fn ready_sample(&mut self) -> READY_SAMPLE_W`[src]

Bit 0 - Shortcut between READY event and SAMPLE task

`pub fn ready_stop(&mut self) -> READY_STOP_W`[src]

Bit 1 - Shortcut between READY event and STOP task

`pub fn down_stop(&mut self) -> DOWN_STOP_W`[src]

Bit 2 - Shortcut between DOWN event and STOP task

`pub fn up_stop(&mut self) -> UP_STOP_W`[src]

Bit 3 - Shortcut between UP event and STOP task

`pub fn cross_stop(&mut self) -> CROSS_STOP_W`[src]

Bit 4 - Shortcut between CROSS event and STOP task

`impl W<u32, Reg<u32, _INTEN>>`[src]

`pub fn ready(&mut self) -> READY_W`[src]

Bit 0 - Enable or disable interrupt for READY event

`pub fn down(&mut self) -> DOWN_W`[src]

Bit 1 - Enable or disable interrupt for DOWN event

`pub fn up(&mut self) -> UP_W`[src]

Bit 2 - Enable or disable interrupt for UP event

`pub fn cross(&mut self) -> CROSS_W`[src]

Bit 3 - Enable or disable interrupt for CROSS event

`impl W<u32, Reg<u32, _INTENSET>>`[src]

`pub fn ready(&mut self) -> READY_W`[src]

Bit 0 - Write '1' to enable interrupt for READY event

`pub fn down(&mut self) -> DOWN_W`[src]

Bit 1 - Write '1' to enable interrupt for DOWN event

`pub fn up(&mut self) -> UP_W`[src]

Bit 2 - Write '1' to enable interrupt for UP event

`pub fn cross(&mut self) -> CROSS_W`[src]

Bit 3 - Write '1' to enable interrupt for CROSS event

`impl W<u32, Reg<u32, _INTENCLR>>`[src]

`pub fn ready(&mut self) -> READY_W`[src]

Bit 0 - Write '1' to disable interrupt for READY event

`pub fn down(&mut self) -> DOWN_W`[src]

Bit 1 - Write '1' to disable interrupt for DOWN event

`pub fn up(&mut self) -> UP_W`[src]

Bit 2 - Write '1' to disable interrupt for UP event

`pub fn cross(&mut self) -> CROSS_W`[src]

Bit 3 - Write '1' to disable interrupt for CROSS event

`impl W<u32, Reg<u32, _ENABLE>>`[src]

`pub fn enable(&mut self) -> ENABLE_W`[src]

Bits 0:1 - Enable or disable COMP

`impl W<u32, Reg<u32, _PSEL>>`[src]

`pub fn psel(&mut self) -> PSEL_W`[src]

Bits 0:2 - Analog pin select

`impl W<u32, Reg<u32, _REFSEL>>`[src]

`pub fn refsel(&mut self) -> REFSEL_W`[src]

Bits 0:2 - Reference select

`impl W<u32, Reg<u32, _EXTREFSEL>>`[src]

`pub fn extrefsel(&mut self) -> EXTREFSEL_W`[src]

Bits 0:2 - External analog reference select

`impl W<u32, Reg<u32, _TH>>`[src]

`pub fn thdown(&mut self) -> THDOWN_W`[src]

Bits 0:5 - VDOWN = (THDOWN+1)/64*VREF

`pub fn thup(&mut self) -> THUP_W`[src]

Bits 8:13 - VUP = (THUP+1)/64*VREF

`impl W<u32, Reg<u32, _MODE>>`[src]

`pub fn sp(&mut self) -> SP_W`[src]

`pub fn ready_stop(&mut self) -> READY_STOP_W`[src]

Bit 1 - Shortcut between READY event and STOP task

`pub fn down_stop(&mut self) -> DOWN_STOP_W`[src]

Bit 2 - Shortcut between DOWN event and STOP task

`pub fn up_stop(&mut self) -> UP_STOP_W`[src]

Bit 3 - Shortcut between UP event and STOP task

`pub fn cross_stop(&mut self) -> CROSS_STOP_W`[src]

Bit 4 - Shortcut between CROSS event and STOP task

`impl W<u32, Reg<u32, _INTENSET>>`[src]

`pub fn ready(&mut self) -> READY_W`[src]

Bit 0 - Write '1' to enable interrupt for READY event

`pub fn down(&mut self) -> DOWN_W`[src]

Bit 1 - Write '1' to enable interrupt for DOWN event

`pub fn up(&mut self) -> UP_W`[src]

Bit 2 - Write '1' to enable interrupt for UP event

`pub fn cross(&mut self) -> CROSS_W`[src]

Bit 3 - Write '1' to enable interrupt for CROSS event

`impl W<u32, Reg<u32, _INTENCLR>>`[src]

`pub fn ready(&mut self) -> READY_W`[src]

Bit 0 - Write '1' to disable interrupt for READY event

`pub fn down(&mut self) -> DOWN_W`[src]

Bit 1 - Write '1' to disable interrupt for DOWN event

`pub fn up(&mut self) -> UP_W`[src]

Bit 2 - Write '1' to disable interrupt for UP event

`pub fn cross(&mut self) -> CROSS_W`[src]

Bit 3 - Write '1' to disable interrupt for CROSS event

`impl W<u32, Reg<u32, _ENABLE>>`[src]

`pub fn enable(&mut self) -> ENABLE_W`[src]

Bits 0:1 - Enable or disable LPCOMP

`impl W<u32, Reg<u32, _PSEL>>`[src]

`pub fn psel(&mut self) -> PSEL_W`[src]

Bits 0:2 - Analog pin select

`impl W<u32, Reg<u32, _REFSEL>>`[src]

`pub fn refsel(&mut self) -> REFSEL_W`[src]

Bits 0:3 - Reference select

`impl W<u32, Reg<u32, _EXTREFSEL>>`[src]

`pub fn extrefsel(&mut self) -> EXTREFSEL_W`[src]

Bit 0 - External analog reference select

`impl W<u32, Reg<u32, _ANADETECT>>`[src]

`pub fn anadetect(&mut self) -> ANADETECT_W`[src]

Bits 0:1 - Analog detect configuration

`impl W<u32, Reg<u32, _HYST>>`[src]

`pub fn hyst(&mut self) -> HYST_W`[src]

Bit 0 - Comparator hysteresis enable

`impl W<u32, Reg<u32, _TASKS_TRIGGER>>`[src]

`pub fn tasks_trigger(&mut self) -> TASKS_TRIGGER_W`[src]

Bit 0

`impl W<u32, Reg<u32, _EVENTS_TRIGGERED>>`[src]

`pub fn events_triggered(&mut self) -> EVENTS_TRIGGERED_W`[src]

Bit 0

`impl W<u32, Reg<u32, _INTEN>>`[src]

`pub fn triggered0(&mut self) -> TRIGGERED0_W`[src]

Bit 0 - Enable or disable interrupt for TRIGGERED[0] event

`pub fn triggered1(&mut self) -> TRIGGERED1_W`[src]

Bit 1 - Enable or disable interrupt for TRIGGERED[1] event

`pub fn triggered2(&mut self) -> TRIGGERED2_W`[src]

Bit 2 - Enable or disable interrupt for TRIGGERED[2] event

`pub fn triggered3(&mut self) -> TRIGGERED3_W`[src]

Bit 3 - Enable or disable interrupt for TRIGGERED[3] event

`pub fn triggered4(&mut self) -> TRIGGERED4_W`[src]

Bit 4 - Enable or disable interrupt for TRIGGERED[4] event

`pub fn triggered5(&mut self) -> TRIGGERED5_W`[src]

Bit 5 - Enable or disable interrupt for TRIGGERED[5] event

`pub fn triggered6(&mut self) -> TRIGGERED6_W`[src]

Bit 6 - Enable or disable interrupt for TRIGGERED[6] event

`pub fn triggered7(&mut self) -> TRIGGERED7_W`[src]

Bit 7 - Enable or disable interrupt for TRIGGERED[7] event

`pub fn triggered8(&mut self) -> TRIGGERED8_W`[src]

Bit 8 - Enable or disable interrupt for TRIGGERED[8] event

`pub fn triggered9(&mut self) -> TRIGGERED9_W`[src]

Bit 9 - Enable or disable interrupt for TRIGGERED[9] event

`pub fn triggered10(&mut self) -> TRIGGERED10_W`[src]

Bit 10 - Enable or disable interrupt for TRIGGERED[10] event

`pub fn triggered11(&mut self) -> TRIGGERED11_W`[src]

Bit 11 - Enable or disable interrupt for TRIGGERED[11] event

`pub fn triggered12(&mut self) -> TRIGGERED12_W`[src]

Bit 12 - Enable or disable interrupt for TRIGGERED[12] event

`pub fn triggered13(&mut self) -> TRIGGERED13_W`[src]

Bit 13 - Enable or disable interrupt for TRIGGERED[13] event

`pub fn triggered14(&mut self) -> TRIGGERED14_W`[src]

Bit 14 - Enable or disable interrupt for TRIGGERED[14] event

`pub fn triggered15(&mut self) -> TRIGGERED15_W`[src]

Bit 15 - Enable or disable interrupt for TRIGGERED[15] event

`impl W<u32, Reg<u32, _INTENSET>>`[src]

`pub fn triggered0(&mut self) -> TRIGGERED0_W`[src]

Bit 0 - Write '1' to enable interrupt for TRIGGERED[0] event

`pub fn triggered1(&mut self) -> TRIGGERED1_W`[src]

Bit 1 - Write '1' to enable interrupt for TRIGGERED[1] event

`pub fn triggered2(&mut self) -> TRIGGERED2_W`[src]

Bit 2 - Write '1' to enable interrupt for TRIGGERED[2] event

`pub fn triggered3(&mut self) -> TRIGGERED3_W`[src]

Bit 3 - Write '1' to enable interrupt for TRIGGERED[3] event

`pub fn triggered4(&mut self) -> TRIGGERED4_W`[src]

Bit 4 - Write '1' to enable interrupt for TRIGGERED[4] event

`pub fn triggered5(&mut self) -> TRIGGERED5_W`[src]

Bit 5 - Write '1' to enable interrupt for TRIGGERED[5] event

`pub fn triggered6(&mut self) -> TRIGGERED6_W`[src]

Bit 6 - Write '1' to enable interrupt for TRIGGERED[6] event

`pub fn triggered7(&mut self) -> TRIGGERED7_W`[src]

Bit 7 - Write '1' to enable interrupt for TRIGGERED[7] event

`pub fn triggered8(&mut self) -> TRIGGERED8_W`[src]

Bit 8 - Write '1' to enable interrupt for TRIGGERED[8] event

`pub fn triggered9(&mut self) -> TRIGGERED9_W`[src]

Bit 9 - Write '1' to enable interrupt for TRIGGERED[9] event

`pub fn triggered10(&mut self) -> TRIGGERED10_W`[src]

Bit 10 - Write '1' to enable interrupt for TRIGGERED[10] event

`pub fn triggered11(&mut self) -> TRIGGERED11_W`[src]

Bit 11 - Write '1' to enable interrupt for TRIGGERED[11] event

`pub fn triggered12(&mut self) -> TRIGGERED12_W`[src]

Bit 12 - Write '1' to enable interrupt for TRIGGERED[12] event

`pub fn triggered13(&mut self) -> TRIGGERED13_W`[src]

Bit 13 - Write '1' to enable interrupt for TRIGGERED[13] event

`pub fn triggered14(&mut self) -> TRIGGERED14_W`[src]

Bit 14 - Write '1' to enable interrupt for TRIGGERED[14] event

`pub fn triggered15(&mut self) -> TRIGGERED15_W`[src]

Bit 15 - Write '1' to enable interrupt for TRIGGERED[15] event

`impl W<u32, Reg<u32, _INTENCLR>>`[src]

`pub fn triggered0(&mut self) -> TRIGGERED0_W`[src]

Bit 0 - Write '1' to disable interrupt for TRIGGERED[0] event

`pub fn triggered1(&mut self) -> TRIGGERED1_W`[src]

Bit 1 - Write '1' to disable interrupt for TRIGGERED[1] event

`pub fn triggered2(&mut self) -> TRIGGERED2_W`[src]

Bit 2 - Write '1' to disable interrupt for TRIGGERED[2] event

`pub fn triggered3(&mut self) -> TRIGGERED3_W`[src]

Bit 3 - Write '1' to disable interrupt for TRIGGERED[3] event

`pub fn triggered4(&mut self) -> TRIGGERED4_W`[src]

Bit 4 - Write '1' to disable interrupt for TRIGGERED[4] event

`pub fn triggered5(&mut self) -> TRIGGERED5_W`[src]

Bit 5 - Write '1' to disable interrupt for TRIGGERED[5] event

`pub fn triggered6(&mut self) -> TRIGGERED6_W`[src]

Bit 6 - Write '1' to disable interrupt for TRIGGERED[6] event

`pub fn triggered7(&mut self) -> TRIGGERED7_W`[src]

Bit 7 - Write '1' to disable interrupt for TRIGGERED[7] event

`pub fn triggered8(&mut self) -> TRIGGERED8_W`[src]

Bit 8 - Write '1' to disable interrupt for TRIGGERED[8] event

`pub fn triggered9(&mut self) -> TRIGGERED9_W`[src]

Bit 9 - Write '1' to disable interrupt for TRIGGERED[9] event

`pub fn triggered10(&mut self) -> TRIGGERED10_W`[src]

Bit 10 - Write '1' to disable interrupt for TRIGGERED[10] event

`pub fn triggered11(&mut self) -> TRIGGERED11_W`[src]

Bit 11 - Write '1' to disable interrupt for TRIGGERED[11] event

`pub fn triggered12(&mut self) -> TRIGGERED12_W`[src]

Bit 12 - Write '1' to disable interrupt for TRIGGERED[12] event

`pub fn triggered13(&mut self) -> TRIGGERED13_W`[src]

Bit 13 - Write '1' to disable interrupt for TRIGGERED[13] event

`pub fn triggered14(&mut self) -> TRIGGERED14_W`[src]

`impl W<u32, Reg<u32, _SHORTS>>`[src]

`pub fn compare0_clear(&mut self) -> COMPARE0_CLEAR_W`[src]

Bit 0 - Shortcut between COMPARE[0] event and CLEAR task

`pub fn compare1_clear(&mut self) -> COMPARE1_CLEAR_W`[src]

Bit 1 - Shortcut between COMPARE[1] event and CLEAR task

`pub fn compare2_clear(&mut self) -> COMPARE2_CLEAR_W`[src]

Bit 2 - Shortcut between COMPARE[2] event and CLEAR task

`pub fn compare3_clear(&mut self) -> COMPARE3_CLEAR_W`[src]

Bit 3 - Shortcut between COMPARE[3] event and CLEAR task

`pub fn compare4_clear(&mut self) -> COMPARE4_CLEAR_W`[src]

Bit 4 - Shortcut between COMPARE[4] event and CLEAR task

`pub fn compare5_clear(&mut self) -> COMPARE5_CLEAR_W`[src]

Bit 5 - Shortcut between COMPARE[5] event and CLEAR task

`pub fn compare0_stop(&mut self) -> COMPARE0_STOP_W`[src]

Bit 8 - Shortcut between COMPARE[0] event and STOP task

`pub fn compare1_stop(&mut self) -> COMPARE1_STOP_W`[src]

Bit 9 - Shortcut between COMPARE[1] event and STOP task

`pub fn compare2_stop(&mut self) -> COMPARE2_STOP_W`[src]

Bit 10 - Shortcut between COMPARE[2] event and STOP task

`pub fn compare3_stop(&mut self) -> COMPARE3_STOP_W`[src]

Bit 11 - Shortcut between COMPARE[3] event and STOP task

`pub fn compare4_stop(&mut self) -> COMPARE4_STOP_W`[src]

Bit 12 - Shortcut between COMPARE[4] event and STOP task

`pub fn compare5_stop(&mut self) -> COMPARE5_STOP_W`[src]

Bit 13 - Shortcut between COMPARE[5] event and STOP task

`impl W<u32, Reg<u32, _INTENSET>>`[src]

`pub fn compare0(&mut self) -> COMPARE0_W`[src]

Bit 16 - Write '1' to enable interrupt for COMPARE[0] event

`pub fn compare1(&mut self) -> COMPARE1_W`[src]

Bit 17 - Write '1' to enable interrupt for COMPARE[1] event

`pub fn compare2(&mut self) -> COMPARE2_W`[src]

Bit 18 - Write '1' to enable interrupt for COMPARE[2] event

`pub fn compare3(&mut self) -> COMPARE3_W`[src]

Bit 19 - Write '1' to enable interrupt for COMPARE[3] event

`pub fn compare4(&mut self) -> COMPARE4_W`[src]

Bit 20 - Write '1' to enable interrupt for COMPARE[4] event

`pub fn compare5(&mut self) -> COMPARE5_W`[src]

Bit 21 - Write '1' to enable interrupt for COMPARE[5] event

`impl W<u32, Reg<u32, _INTENCLR>>`[src]

`pub fn compare0(&mut self) -> COMPARE0_W`[src]

Bit 16 - Write '1' to disable interrupt for COMPARE[0] event

`pub fn compare1(&mut self) -> COMPARE1_W`[src]

Bit 17 - Write '1' to disable interrupt for COMPARE[1] event

`pub fn compare2(&mut self) -> COMPARE2_W`[src]

Bit 18 - Write '1' to disable interrupt for COMPARE[2] event

`pub fn compare3(&mut self) -> COMPARE3_W`[src]

Bit 19 - Write '1' to disable interrupt for COMPARE[3] event

`pub fn compare4(&mut self) -> COMPARE4_W`[src]

Bit 20 - Write '1' to disable interrupt for COMPARE[4] event

`pub fn compare5(&mut self) -> COMPARE5_W`[src]

Bit 21 - Write '1' to disable interrupt for COMPARE[5] event

`impl W<u32, Reg<u32, _MODE>>`[src]

`pub fn mode(&mut self) -> MODE_W`[src]

Bits 0:1 - Timer mode

`impl W<u32, Reg<u32, _BITMODE>>`[src]

`pub fn bitmode(&mut self) -> BITMODE_W`[src]

Bits 0:1 - Timer bit width

`impl W<u32, Reg<u32, _PRESCALER>>`[src]

`pub fn prescaler(&mut self) -> PRESCALER_W`[src]

Bits 0:3 - Prescaler value

`impl W<u32, Reg<u32, _CC>>`[src]

`pub fn cc(&mut self) -> CC_W`[src]

Bits 0:31 - Capture/Compare value

`impl W<u32, Reg<u32, _PTR>>`[src]

`pub fn ptr(&mut self) -> PTR_W`[src]

Bits 0:31 - Beginning address in RAM of this sequence

`impl W<u32, Reg<u32, _CNT>>`[src]

`pub fn cnt(&mut self) -> CNT_W`[src]

Bits 0:14 - Number of values (duty cycles) in this sequence

`impl W<u32, Reg<u32, _REFRESH>>`[src]

`pub fn cnt(&mut self) -> CNT_W`[src]

Bits 0:23 - Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods)

`impl W<u32, Reg<u32, _ENDDELAY>>`[src]

`pub fn cnt(&mut self) -> CNT_W`[src]

Bits 0:23 - Time added after the sequence in PWM periods

`impl W<u32, Reg<u32, _OUT>>`[src]

`pub fn pin(&mut self) -> PIN_W`[src]

Bits 0:4 - Pin number

`pub fn port(&mut self) -> PORT_W`[src]

`pub fn seqend1_stop(&mut self) -> SEQEND1_STOP_W`[src]

Bit 1 - Shortcut between SEQEND[1] event and STOP task

`pub fn loopsdone_seqstart0(&mut self) -> LOOPSDONE_SEQSTART0_W`[src]

Bit 2 - Shortcut between LOOPSDONE event and SEQSTART[0] task

`pub fn loopsdone_seqstart1(&mut self) -> LOOPSDONE_SEQSTART1_W`[src]

Bit 3 - Shortcut between LOOPSDONE event and SEQSTART[1] task

`pub fn loopsdone_stop(&mut self) -> LOOPSDONE_STOP_W`[src]

Bit 4 - Shortcut between LOOPSDONE event and STOP task

`impl W<u32, Reg<u32, _INTEN>>`[src]

`pub fn stopped(&mut self) -> STOPPED_W`[src]

Bit 1 - Enable or disable interrupt for STOPPED event

`pub fn seqstarted0(&mut self) -> SEQSTARTED0_W`[src]

Bit 2 - Enable or disable interrupt for SEQSTARTED[0] event

`pub fn seqstarted1(&mut self) -> SEQSTARTED1_W`[src]

Bit 3 - Enable or disable interrupt for SEQSTARTED[1] event

`pub fn seqend0(&mut self) -> SEQEND0_W`[src]

Bit 4 - Enable or disable interrupt for SEQEND[0] event

`pub fn seqend1(&mut self) -> SEQEND1_W`[src]

Bit 5 - Enable or disable interrupt for SEQEND[1] event

`pub fn pwmperiodend(&mut self) -> PWMPERIODEND_W`[src]

Bit 6 - Enable or disable interrupt for PWMPERIODEND event

`pub fn loopsdone(&mut self) -> LOOPSDONE_W`[src]

Bit 7 - Enable or disable interrupt for LOOPSDONE event

`impl W<u32, Reg<u32, _INTENSET>>`[src]

`pub fn stopped(&mut self) -> STOPPED_W`[src]

Bit 1 - Write '1' to enable interrupt for STOPPED event

`pub fn seqstarted0(&mut self) -> SEQSTARTED0_W`[src]

Bit 2 - Write '1' to enable interrupt for SEQSTARTED[0] event

`pub fn seqstarted1(&mut self) -> SEQSTARTED1_W`[src]

Bit 3 - Write '1' to enable interrupt for SEQSTARTED[1] event

`pub fn seqend0(&mut self) -> SEQEND0_W`[src]

Bit 4 - Write '1' to enable interrupt for SEQEND[0] event

`pub fn seqend1(&mut self) -> SEQEND1_W`[src]

Bit 5 - Write '1' to enable interrupt for SEQEND[1] event

`pub fn pwmperiodend(&mut self) -> PWMPERIODEND_W`[src]

Bit 6 - Write '1' to enable interrupt for PWMPERIODEND event

`pub fn loopsdone(&mut self) -> LOOPSDONE_W`[src]

Bit 7 - Write '1' to enable interrupt for LOOPSDONE event

`impl W<u32, Reg<u32, _INTENCLR>>`[src]

`pub fn stopped(&mut self) -> STOPPED_W`[src]

Bit 1 - Write '1' to disable interrupt for STOPPED event

`pub fn seqstarted0(&mut self) -> SEQSTARTED0_W`[src]

Bit 2 - Write '1' to disable interrupt for SEQSTARTED[0] event

`pub fn seqstarted1(&mut self) -> SEQSTARTED1_W`[src]

Bit 3 - Write '1' to disable interrupt for SEQSTARTED[1] event

`pub fn seqend0(&mut self) -> SEQEND0_W`[src]

Bit 4 - Write '1' to disable interrupt for SEQEND[0] event

`pub fn seqend1(&mut self) -> SEQEND1_W`[src]

Bit 5 - Write '1' to disable interrupt for SEQEND[1] event

`pub fn pwmperiodend(&mut self) -> PWMPERIODEND_W`[src]

Bit 6 - Write '1' to disable interrupt for PWMPERIODEND event

`pub fn loopsdone(&mut self) -> LOOPSDONE_W`[src]

Bit 7 - Write '1' to disable interrupt for LOOPSDONE event

`impl W<u32, Reg<u32, _ENABLE>>`[src]

`pub fn enable(&mut self) -> ENABLE_W`[src]

Bit 0 - Enable or disable PWM module

`impl W<u32, Reg<u32, _MODE>>`[src]

`pub fn updown(&mut self) -> UPDOWN_W`[src]

Bit 0 - Selects up mode or up-and-down mode for the counter

`impl W<u32, Reg<u32, _COUNTERTOP>>`[src]

`pub fn countertop(&mut self) -> COUNTERTOP_W`[src]

Bits 0:14 - Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM are used.

`impl W<u32, Reg<u32, _PRESCALER>>`[src]

`pub fn prescaler(&mut self) -> PRESCALER_W`[src]

Bits 0:2 - Prescaler of PWM_CLK

`impl W<u32, Reg<u32, _DECODER>>`[src]

`pub fn load(&mut self) -> LOAD_W`[src]

Bits 0:1 - How a sequence is read from RAM and spread to the compare register

`pub fn mode(&mut self) -> MODE_W`[src]

Bit 8 - Selects source for advancing the active sequence

`impl W<u32, Reg<u32, _LOOP>>`[src]

`pub fn cnt(&mut self) -> CNT_W`[src]

Bits 0:15 - Number of playbacks of pattern cycles

`impl W<u32, Reg<u32, _CLK>>`[src]

`pub fn pin(&mut self) -> PIN_W`[src]

Bits 0:4 - Pin number

`pub fn port(&mut self) -> PORT_W`[src]

Bit 5 - Port number

`pub fn connect(&mut self) -> CONNECT_W`[src]

Bit 31 - Connection

`impl W<u32, Reg<u32, _DIN>>`[src]

`pub fn pin(&mut self) -> PIN_W`[src]

Bits 0:4 - Pin number

`pub fn port(&mut self) -> PORT_W`[src]

`impl W<u32, Reg<u32, _INTEN>>`[src]

`pub fn started(&mut self) -> STARTED_W`[src]

Bit 0 - Enable or disable interrupt for STARTED event

`pub fn stopped(&mut self) -> STOPPED_W`[src]

Bit 1 - Enable or disable interrupt for STOPPED event

`pub fn end(&mut self) -> END_W`[src]

Bit 2 - Enable or disable interrupt for END event

`impl W<u32, Reg<u32, _INTENSET>>`[src]

`pub fn started(&mut self) -> STARTED_W`[src]

Bit 0 - Write '1' to enable interrupt for STARTED event

`pub fn stopped(&mut self) -> STOPPED_W`[src]

Bit 1 - Write '1' to enable interrupt for STOPPED event

`pub fn end(&mut self) -> END_W`[src]

Bit 2 - Write '1' to enable interrupt for END event

`impl W<u32, Reg<u32, _INTENCLR>>`[src]

`pub fn started(&mut self) -> STARTED_W`[src]

Bit 0 - Write '1' to disable interrupt for STARTED event

`pub fn stopped(&mut self) -> STOPPED_W`[src]

Bit 1 - Write '1' to disable interrupt for STOPPED event

`pub fn end(&mut self) -> END_W`[src]

Bit 2 - Write '1' to disable interrupt for END event

`impl W<u32, Reg<u32, _ENABLE>>`[src]

`pub fn enable(&mut self) -> ENABLE_W`[src]

Bit 0 - Enable or disable PDM module

`impl W<u32, Reg<u32, _PDMCLKCTRL>>`[src]

`pub fn freq(&mut self) -> FREQ_W`[src]

Bits 0:31 - PDM_CLK frequency

`impl W<u32, Reg<u32, _MODE>>`[src]

`pub fn operation(&mut self) -> OPERATION_W`[src]

Bit 0 - Mono or stereo operation

`pub fn edge(&mut self) -> EDGE_W`[src]

Bit 1 - Defines on which PDM_CLK edge Left (or mono) is sampled

`impl W<u32, Reg<u32, _GAINL>>`[src]

`pub fn gainl(&mut self) -> GAINL_W`[src]

Bits 0:6 - Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust

`impl W<u32, Reg<u32, _GAINR>>`[src]

`pub fn gainr(&mut self) -> GAINR_W`[src]

Bits 0:6 - Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters)

`impl W<u32, Reg<u32, _RATIO>>`[src]

`pub fn ratio(&mut self) -> RATIO_W`[src]

Bit 0 - Selects the ratio between PDM_CLK and output sample rate

`impl W<u32, Reg<u32, _ADDR>>`[src]

`pub fn addr(&mut self) -> ADDR_W`[src]

Bits 0:31 - Valid word-aligned start address of region n to protect. Address must point to a flash page boundary.

`impl W<u32, Reg<u32, _SIZE>>`[src]

`pub fn size(&mut self) -> SIZE_W`[src]

Bits 0:31 - Size of flash region n in bytes. Must be a multiple of the flash page size, and the maximum region size is limited to 512kB.

`impl W<u32, Reg<u32, _PERM>>`[src]

`pub fn write(&mut self) -> WRITE_W`[src]

Bit 1 - Configure write and erase permissions for region n. Write '0' has no effect.

`pub fn read(&mut self) -> READ_W`[src]

Bit 2 - Configure read permissions for region n. Write '0' has no effect.

`impl W<u32, Reg<u32, _CONFIG>>`[src]

`pub fn wen(&mut self) -> WEN_W`[src]

Bits 0:1 - Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated.

`impl W<u32, Reg<u32, _ERASEPAGE>>`[src]

`pub fn erasepage(&mut self) -> ERASEPAGE_W`[src]

Bits 0:31 - Register for starting erase of a page in code area

`impl W<u32, Reg<u32, _ERASEPCR1>>`[src]

`pub fn erasepcr1(&mut self) -> ERASEPCR1_W`[src]

Bits 0:31 - Register for erasing a page in code area. Equivalent to ERASEPAGE.

`impl W<u32, Reg<u32, _ERASEALL>>`[src]

`pub fn eraseall(&mut self) -> ERASEALL_W`[src]

Bit 0 - Erase all non-volatile memory including UICR registers. Note that the erase must be enabled using CONFIG.WEN before the non-volatile memory can be erased.

`impl W<u32, Reg<u32, _ERASEPCR0>>`[src]

`pub fn erasepcr0(&mut self) -> ERASEPCR0_W`[src]

Bits 0:31 - Register for starting erase of a page in code area. Equivalent to ERASEPAGE.

`impl W<u32, Reg<u32, _ERASEUICR>>`[src]

`pub fn eraseuicr(&mut self) -> ERASEUICR_W`[src]

Bit 0 - Register starting erase of all user information configuration registers. Note that the erase must be enabled using CONFIG.WEN before the UICR can be erased.

`impl W<u32, Reg<u32, _ERASEPAGEPARTIAL>>`[src]

`pub fn erasepagepartial(&mut self) -> ERASEPAGEPARTIAL_W`[src]

Bits 0:31 - Register for starting partial erase of a page in code area

`impl W<u32, Reg<u32, _ERASEPAGEPARTIALCFG>>`[src]

`pub fn duration(&mut self) -> DURATION_W`[src]

Bits 0:6 - Duration of the partial erase in milliseconds

`impl W<u32, Reg<u32, _ICACHECNF>>`[src]

`pub fn cacheen(&mut self) -> CACHEEN_W`[src]

Bit 0 - Cache enable

`pub fn cacheprofen(&mut self) -> CACHEPROFEN_W`[src]

Bit 8 - Cache profiling enable

`impl W<u32, Reg<u32, _IHIT>>`[src]

`pub fn hits(&mut self) -> HITS_W`[src]

Bits 0:31 - Number of cache hits

`impl W<u32, Reg<u32, _IMISS>>`[src]

`pub fn misses(&mut self) -> MISSES_W`[src]

Bits 0:31 - Number of cache misses

`impl W<u32, Reg<u32, _EN>>`[src]

`pub fn en(&mut self) -> EN_W`[src]

Bit 0

`impl W<u32, Reg<u32, _DIS>>`[src]

`pub fn dis(&mut self) -> DIS_W`[src]

Bit 0

`impl W<u32, Reg<u32, _EEP>>`[src]

`pub fn eep(&mut self) -> EEP_W`[src]

Bits 0:31 - Pointer to event register. Accepts only addresses to registers from the Event group.

`impl W<u32, Reg<u32, _TEP>>`[src]

`pub fn tep(&mut self) -> TEP_W`[src]

Bits 0:31 - Pointer to task register. Accepts only addresses to registers from the Task group.

`impl W<u32, Reg<u32, _TEP>>`[src]

`pub fn tep(&mut self) -> TEP_W`[src]

Bits 0:31 - Pointer to task register

`impl W<u32, Reg<u32, _CHEN>>`[src]

`pub fn ch0(&mut self) -> CH0_W`[src]

Bit 0 - Enable or disable channel 0

`pub fn ch1(&mut self) -> CH1_W`[src]

Bit 1 - Enable or disable channel 1

`pub fn ch2(&mut self) -> CH2_W`[src]

Bit 2 - Enable or disable channel 2

`pub fn ch3(&mut self) -> CH3_W`[src]

Bit 3 - Enable or disable channel 3

`pub fn ch4(&mut self) -> CH4_W`[src]

Bit 4 - Enable or disable channel 4

`pub fn ch5(&mut self) -> CH5_W`[src]

Bit 5 - Enable or disable channel 5

`pub fn ch6(&mut self) -> CH6_W`[src]

Bit 6 - Enable or disable channel 6

`pub fn ch7(&mut self) -> CH7_W`[src]

Bit 7 - Enable or disable channel 7

`pub fn ch8(&mut self) -> CH8_W`[src]

Bit 8 - Enable or disable channel 8

`pub fn ch9(&mut self) -> CH9_W`[src]

Bit 9 - Enable or disable channel 9

`pub fn ch10(&mut self) -> CH10_W`[src]

Bit 10 - Enable or disable channel 10

`pub fn ch11(&mut self) -> CH11_W`[src]

Bit 11 - Enable or disable channel 11

`pub fn ch12(&mut self) -> CH12_W`[src]

Bit 12 - Enable or disable channel 12

`pub fn ch13(&mut self) -> CH13_W`[src]

Bit 13 - Enable or disable channel 13

`pub fn ch14(&mut self) -> CH14_W`[src]

Bit 14 - Enable or disable channel 14

`pub fn ch15(&mut self) -> CH15_W`[src]

Bit 15 - Enable or disable channel 15

`pub fn ch16(&mut self) -> CH16_W`[src]

Bit 16 - Enable or disable channel 16

`pub fn ch17(&mut self) -> CH17_W`[src]

Bit 17 - Enable or disable channel 17

`pub fn ch18(&mut self) -> CH18_W`[src]

Bit 18 - Enable or disable channel 18

`pub fn ch19(&mut self) -> CH19_W`[src]

Bit 19 - Enable or disable channel 19

`pub fn ch20(&mut self) -> CH20_W`[src]

Bit 20 - Enable or disable channel 20

`pub fn ch21(&mut self) -> CH21_W`[src]

Bit 21 - Enable or disable channel 21

`pub fn ch22(&mut self) -> CH22_W`[src]

Bit 22 - Enable or disable channel 22

`pub fn ch23(&mut self) -> CH23_W`[src]

Bit 23 - Enable or disable channel 23

`pub fn ch24(&mut self) -> CH24_W`[src]

Bit 24 - Enable or disable channel 24

`pub fn ch25(&mut self) -> CH25_W`[src]

Bit 25 - Enable or disable channel 25

`pub fn ch26(&mut self) -> CH26_W`[src]

Bit 26 - Enable or disable channel 26

`pub fn ch27(&mut self) -> CH27_W`[src]

Bit 27 - Enable or disable channel 27

`pub fn ch28(&mut self) -> CH28_W`[src]

Bit 28 - Enable or disable channel 28

`pub fn ch29(&mut self) -> CH29_W`[src]

Bit 29 - Enable or disable channel 29

`pub fn ch30(&mut self) -> CH30_W`[src]

Bit 30 - Enable or disable channel 30

`pub fn ch31(&mut self) -> CH31_W`[src]

Bit 31 - Enable or disable channel 31

`impl W<u32, Reg<u32, _CHENSET>>`[src]

`pub fn ch0(&mut self) -> CH0_W`[src]

Bit 0 - Channel 0 enable set register. Writing '0' has no effect

`pub fn ch1(&mut self) -> CH1_W`[src]

Bit 1 - Channel 1 enable set register. Writing '0' has no effect

`pub fn ch2(&mut self) -> CH2_W`[src]

Bit 2 - Channel 2 enable set register. Writing '0' has no effect

`pub fn ch3(&mut self) -> CH3_W`[src]

Bit 3 - Channel 3 enable set register. Writing '0' has no effect

`pub fn ch4(&mut self) -> CH4_W`[src]

Bit 4 - Channel 4 enable set register. Writing '0' has no effect

`pub fn ch5(&mut self) -> CH5_W`[src]

Bit 5 - Channel 5 enable set register. Writing '0' has no effect

`pub fn ch6(&mut self) -> CH6_W`[src]

Bit 6 - Channel 6 enable set register. Writing '0' has no effect

`pub fn ch7(&mut self) -> CH7_W`[src]

Bit 7 - Channel 7 enable set register. Writing '0' has no effect

`pub fn ch8(&mut self) -> CH8_W`[src]

Bit 8 - Channel 8 enable set register. Writing '0' has no effect

`pub fn ch9(&mut self) -> CH9_W`[src]

Bit 9 - Channel 9 enable set register. Writing '0' has no effect

`pub fn ch10(&mut self) -> CH10_W`[src]

Bit 10 - Channel 10 enable set register. Writing '0' has no effect

`pub fn ch11(&mut self) -> CH11_W`[src]

Bit 11 - Channel 11 enable set register. Writing '0' has no effect

`pub fn ch12(&mut self) -> CH12_W`[src]

Bit 12 - Channel 12 enable set register. Writing '0' has no effect

`pub fn ch13(&mut self) -> CH13_W`[src]

Bit 13 - Channel 13 enable set register. Writing '0' has no effect

`pub fn ch14(&mut self) -> CH14_W`[src]

Bit 14 - Channel 14 enable set register. Writing '0' has no effect

`pub fn ch15(&mut self) -> CH15_W`[src]

Bit 15 - Channel 15 enable set register. Writing '0' has no effect

`pub fn ch16(&mut self) -> CH16_W`[src]

Bit 16 - Channel 16 enable set register. Writing '0' has no effect

`pub fn ch17(&mut self) -> CH17_W`[src]

Bit 17 - Channel 17 enable set register. Writing '0' has no effect

`pub fn ch18(&mut self) -> CH18_W`[src]

Bit 18 - Channel 18 enable set register. Writing '0' has no effect

`pub fn ch19(&mut self) -> CH19_W`[src]

Bit 19 - Channel 19 enable set register. Writing '0' has no effect

`pub fn ch20(&mut self) -> CH20_W`[src]

Bit 20 - Channel 20 enable set register. Writing '0' has no effect

`pub fn ch21(&mut self) -> CH21_W`[src]

Bit 21 - Channel 21 enable set register. Writing '0' has no effect

`pub fn ch22(&mut self) -> CH22_W`[src]

Bit 22 - Channel 22 enable set register. Writing '0' has no effect

`pub fn ch23(&mut self) -> CH23_W`[src]

Bit 23 - Channel 23 enable set register. Writing '0' has no effect

`pub fn ch24(&mut self) -> CH24_W`[src]

Bit 24 - Channel 24 enable set register. Writing '0' has no effect

`pub fn ch25(&mut self) -> CH25_W`[src]

Bit 25 - Channel 25 enable set register. Writing '0' has no effect

`pub fn ch26(&mut self) -> CH26_W`[src]

Bit 26 - Channel 26 enable set register. Writing '0' has no effect

`pub fn ch27(&mut self) -> CH27_W`[src]

Bit 27 - Channel 27 enable set register. Writing '0' has no effect

`pub fn ch28(&mut self) -> CH28_W`[src]

Bit 28 - Channel 28 enable set register. Writing '0' has no effect

`pub fn ch29(&mut self) -> CH29_W`[src]

Bit 29 - Channel 29 enable set register. Writing '0' has no effect

`pub fn ch30(&mut self) -> CH30_W`[src]

Bit 30 - Channel 30 enable set register. Writing '0' has no effect

`pub fn ch31(&mut self) -> CH31_W`[src]

Bit 31 - Channel 31 enable set register. Writing '0' has no effect

`impl W<u32, Reg<u32, _CHENCLR>>`[src]

`pub fn ch0(&mut self) -> CH0_W`[src]

Bit 0 - Channel 0 enable clear register. Writing '0' has no effect

`pub fn ch1(&mut self) -> CH1_W`[src]

Bit 1 - Channel 1 enable clear register. Writing '0' has no effect

`pub fn ch2(&mut self) -> CH2_W`[src]

Bit 2 - Channel 2 enable clear register. Writing '0' has no effect

`pub fn ch3(&mut self) -> CH3_W`[src]

Bit 3 - Channel 3 enable clear register. Writing '0' has no effect

`pub fn ch4(&mut self) -> CH4_W`[src]

Bit 4 - Channel 4 enable clear register. Writing '0' has no effect

`pub fn ch5(&mut self) -> CH5_W`[src]

Bit 5 - Channel 5 enable clear register. Writing '0' has no effect

`pub fn ch6(&mut self) -> CH6_W`[src]

Bit 6 - Channel 6 enable clear register. Writing '0' has no effect

`pub fn ch7(&mut self) -> CH7_W`[src]

Bit 7 - Channel 7 enable clear register. Writing '0' has no effect

`pub fn ch8(&mut self) -> CH8_W`[src]

Bit 8 - Channel 8 enable clear register. Writing '0' has no effect

`pub fn ch9(&mut self) -> CH9_W`[src]

Bit 9 - Channel 9 enable clear register. Writing '0' has no effect

`pub fn ch10(&mut self) -> CH10_W`[src]

Bit 10 - Channel 10 enable clear register. Writing '0' has no effect

`pub fn ch11(&mut self) -> CH11_W`[src]

Bit 11 - Channel 11 enable clear register. Writing '0' has no effect

`pub fn ch12(&mut self) -> CH12_W`[src]

Bit 12 - Channel 12 enable clear register. Writing '0' has no effect

`pub fn ch13(&mut self) -> CH13_W`[src]

Bit 13 - Channel 13 enable clear register. Writing '0' has no effect

`pub fn ch14(&mut self) -> CH14_W`[src]

Bit 14 - Channel 14 enable clear register. Writing '0' has no effect

`pub fn ch15(&mut self) -> CH15_W`[src]

Bit 15 - Channel 15 enable clear register. Writing '0' has no effect

`pub fn ch16(&mut self) -> CH16_W`[src]

Bit 16 - Channel 16 enable clear register. Writing '0' has no effect

`pub fn ch17(&mut self) -> CH17_W`[src]

Bit 17 - Channel 17 enable clear register. Writing '0' has no effect

`pub fn ch18(&mut self) -> CH18_W`[src]

Bit 18 - Channel 18 enable clear register. Writing '0' has no effect

`pub fn ch19(&mut self) -> CH19_W`[src]

Bit 19 - Channel 19 enable clear register. Writing '0' has no effect

`pub fn ch20(&mut self) -> CH20_W`[src]

Bit 20 - Channel 20 enable clear register. Writing '0' has no effect

`pub fn ch21(&mut self) -> CH21_W`[src]

Bit 21 - Channel 21 enable clear register. Writing '0' has no effect

`pub fn ch22(&mut self) -> CH22_W`[src]

Bit 22 - Channel 22 enable clear register. Writing '0' has no effect

`pub fn ch23(&mut self) -> CH23_W`[src]

Bit 23 - Channel 23 enable clear register. Writing '0' has no effect

`pub fn ch24(&mut self) -> CH24_W`[src]

Bit 24 - Channel 24 enable clear register. Writing '0' has no effect

`pub fn ch25(&mut self) -> CH25_W`[src]

Bit 25 - Channel 25 enable clear register. Writing '0' has no effect

`pub fn ch26(&mut self) -> CH26_W`[src]

Bit 26 - Channel 26 enable clear register. Writing '0' has no effect

`pub fn ch27(&mut self) -> CH27_W`[src]

Bit 27 - Channel 27 enable clear register. Writing '0' has no effect

`pub fn ch28(&mut self) -> CH28_W`[src]

Bit 28 - Channel 28 enable clear register. Writing '0' has no effect

`pub fn ch29(&mut self) -> CH29_W`[src]

Bit 29 - Channel 29 enable clear register. Writing '0' has no effect

`pub fn ch30(&mut self) -> CH30_W`[src]

Bit 30 - Channel 30 enable clear register. Writing '0' has no effect

`pub fn ch31(&mut self) -> CH31_W`[src]

Bit 31 - Channel 31 enable clear register. Writing '0' has no effect

`impl W<u32, Reg<u32, _CHG>>`[src]

`pub fn ch0(&mut self) -> CH0_W`[src]

Bit 0 - Include or exclude channel 0

`pub fn ch1(&mut self) -> CH1_W`[src]

Bit 1 - Include or exclude channel 1

`pub fn ch2(&mut self) -> CH2_W`[src]

Bit 2 - Include or exclude channel 2

`pub fn ch3(&mut self) -> CH3_W`[src]

Bit 3 - Include or exclude channel 3

`pub fn ch4(&mut self) -> CH4_W`[src]

Bit 4 - Include or exclude channel 4

`pub fn ch5(&mut self) -> CH5_W`[src]

Bit 5 - Include or exclude channel 5

`pub fn ch6(&mut self) -> CH6_W`[src]

Bit 6 - Include or exclude channel 6

`pub fn ch7(&mut self) -> CH7_W`[src]

Bit 7 - Include or exclude channel 7

`pub fn ch8(&mut self) -> CH8_W`[src]

Bit 8 - Include or exclude channel 8

`pub fn ch9(&mut self) -> CH9_W`[src]

Bit 9 - Include or exclude channel 9

`pub fn ch10(&mut self) -> CH10_W`[src]

Bit 10 - Include or exclude channel 10

`pub fn ch11(&mut self) -> CH11_W`[src]

Bit 11 - Include or exclude channel 11

`pub fn ch12(&mut self) -> CH12_W`[src]

Bit 12 - Include or exclude channel 12

`pub fn ch13(&mut self) -> CH13_W`[src]

Bit 13 - Include or exclude channel 13

`pub fn ch14(&mut self) -> CH14_W`[src]

Bit 14 - Include or exclude channel 14

`pub fn ch15(&mut self) -> CH15_W`[src]

Bit 15 - Include or exclude channel 15

`pub fn ch16(&mut self) -> CH16_W`[src]

Bit 16 - Include or exclude channel 16

`pub fn ch17(&mut self) -> CH17_W`[src]

Bit 17 - Include or exclude channel 17

`pub fn ch18(&mut self) -> CH18_W`[src]

Bit 18 - Include or exclude channel 18

`pub fn ch19(&mut self) -> CH19_W`[src]

Bit 19 - Include or exclude channel 19

`pub fn ch20(&mut self) -> CH20_W`[src]

Bit 20 - Include or exclude channel 20

`pub fn ch21(&mut self) -> CH21_W`[src]

Bit 21 - Include or exclude channel 21

`pub fn ch22(&mut self) -> CH22_W`[src]

Bit 22 - Include or exclude channel 22

`pub fn ch23(&mut self) -> CH23_W`[src]

Bit 23 - Include or exclude channel 23

`pub fn ch24(&mut self) -> CH24_W`[src]

Bit 24 - Include or exclude channel 24

`pub fn ch25(&mut self) -> CH25_W`[src]

Bit 25 - Include or exclude channel 25

`pub fn ch26(&mut self) -> CH26_W`[src]

Bit 26 - Include or exclude channel 26

`pub fn ch27(&mut self) -> CH27_W`[src]

Bit 27 - Include or exclude channel 27

`pub fn ch28(&mut self) -> CH28_W`[src]

Bit 28 - Include or exclude channel 28

`pub fn ch29(&mut self) -> CH29_W`[src]

Bit 29 - Include or exclude channel 29

`pub fn ch30(&mut self) -> CH30_W`[src]

Bit 30 - Include or exclude channel 30

`pub fn ch31(&mut self) -> CH31_W`[src]

Bit 31 - Include or exclude channel 31

`impl W<u32, Reg<u32, _WA>>`[src]

`pub fn wa(&mut self) -> WA_W`[src]

Bit 0

`impl W<u32, Reg<u32, _RA>>`[src]

`pub fn ra(&mut self) -> RA_W`[src]

Bit 0

`impl W<u32, Reg<u32, _WA>>`[src]

`pub fn wa(&mut self) -> WA_W`[src]

Bit 0

`impl W<u32, Reg<u32, _RA>>`[src]

`pub fn ra(&mut self) -> RA_W`[src]

Bit 0

`impl W<u32, Reg<u32, _SUBSTATWA>>`[src]

`pub fn sr0(&mut self) -> SR0_W`[src]

Bit 0 - Subregion 0 in region n (write '1' to clear)

`pub fn sr1(&mut self) -> SR1_W`[src]

Bit 1 - Subregion 1 in region n (write '1' to clear)

`pub fn sr2(&mut self) -> SR2_W`[src]

Bit 2 - Subregion 2 in region n (write '1' to clear)

`pub fn sr3(&mut self) -> SR3_W`[src]

Bit 3 - Subregion 3 in region n (write '1' to clear)

`pub fn sr4(&mut self) -> SR4_W`[src]

Bit 4 - Subregion 4 in region n (write '1' to clear)

`pub fn sr5(&mut self) -> SR5_W`[src]

Bit 5 - Subregion 5 in region n (write '1' to clear)

`pub fn sr6(&mut self) -> SR6_W`[src]

Bit 6 - Subregion 6 in region n (write '1' to clear)

`pub fn sr7(&mut self) -> SR7_W`[src]

Bit 7 - Subregion 7 in region n (write '1' to clear)

`pub fn sr8(&mut self) -> SR8_W`[src]

Bit 8 - Subregion 8 in region n (write '1' to clear)

`pub fn sr9(&mut self) -> SR9_W`[src]

Bit 9 - Subregion 9 in region n (write '1' to clear)

`pub fn sr10(&mut self) -> SR10_W`[src]

Bit 10 - Subregion 10 in region n (write '1' to clear)

`pub fn sr11(&mut self) -> SR11_W`[src]

Bit 11 - Subregion 11 in region n (write '1' to clear)

`pub fn sr12(&mut self) -> SR12_W`[src]

Bit 12 - Subregion 12 in region n (write '1' to clear)

`pub fn sr13(&mut self) -> SR13_W`[src]

Bit 13 - Subregion 13 in region n (write '1' to clear)

`pub fn sr14(&mut self) -> SR14_W`[src]

Bit 14 - Subregion 14 in region n (write '1' to clear)

`pub fn sr15(&mut self) -> SR15_W`[src]

Bit 15 - Subregion 15 in region n (write '1' to clear)

`pub fn sr16(&mut self) -> SR16_W`[src]

Bit 16 - Subregion 16 in region n (write '1' to clear)

`pub fn sr17(&mut self) -> SR17_W`[src]

Bit 17 - Subregion 17 in region n (write '1' to clear)

`pub fn sr18(&mut self) -> SR18_W`[src]

Bit 18 - Subregion 18 in region n (write '1' to clear)

`pub fn sr19(&mut self) -> SR19_W`[src]

Bit 19 - Subregion 19 in region n (write '1' to clear)

`pub fn sr20(&mut self) -> SR20_W`[src]

Bit 20 - Subregion 20 in region n (write '1' to clear)

`pub fn sr21(&mut self) -> SR21_W`[src]

Bit 21 - Subregion 21 in region n (write '1' to clear)

`pub fn sr22(&mut self) -> SR22_W`[src]

Bit 22 - Subregion 22 in region n (write '1' to clear)

`pub fn sr23(&mut self) -> SR23_W`[src]

Bit 23 - Subregion 23 in region n (write '1' to clear)

`pub fn sr24(&mut self) -> SR24_W`[src]

Bit 24 - Subregion 24 in region n (write '1' to clear)

`pub fn sr25(&mut self) -> SR25_W`[src]

Bit 25 - Subregion 25 in region n (write '1' to clear)

`pub fn sr26(&mut self) -> SR26_W`[src]

Bit 26 - Subregion 26 in region n (write '1' to clear)

`pub fn sr27(&mut self) -> SR27_W`[src]

Bit 27 - Subregion 27 in region n (write '1' to clear)

`pub fn sr28(&mut self) -> SR28_W`[src]

Bit 28 - Subregion 28 in region n (write '1' to clear)

`pub fn sr29(&mut self) -> SR29_W`[src]

Bit 29 - Subregion 29 in region n (write '1' to clear)

`pub fn sr30(&mut self) -> SR30_W`[src]

Bit 30 - Subregion 30 in region n (write '1' to clear)

`pub fn sr31(&mut self) -> SR31_W`[src]

Bit 31 - Subregion 31 in region n (write '1' to clear)

`impl W<u32, Reg<u32, _SUBSTATRA>>`[src]

`pub fn sr0(&mut self) -> SR0_W`[src]

Bit 0 - Subregion 0 in region n (write '1' to clear)

`pub fn sr1(&mut self) -> SR1_W`[src]

Bit 1 - Subregion 1 in region n (write '1' to clear)

`pub fn sr2(&mut self) -> SR2_W`[src]

Bit 2 - Subregion 2 in region n (write '1' to clear)

`pub fn sr3(&mut self) -> SR3_W`[src]

Bit 3 - Subregion 3 in region n (write '1' to clear)

`pub fn sr4(&mut self) -> SR4_W`[src]

Bit 4 - Subregion 4 in region n (write '1' to clear)

`pub fn sr5(&mut self) -> SR5_W`[src]

Bit 5 - Subregion 5 in region n (write '1' to clear)

`pub fn sr6(&mut self) -> SR6_W`[src]

Bit 6 - Subregion 6 in region n (write '1' to clear)

`pub fn sr7(&mut self) -> SR7_W`[src]

Bit 7 - Subregion 7 in region n (write '1' to clear)

`pub fn sr8(&mut self) -> SR8_W`[src]

Bit 8 - Subregion 8 in region n (write '1' to clear)

`pub fn sr9(&mut self) -> SR9_W`[src]

Bit 9 - Subregion 9 in region n (write '1' to clear)

`pub fn sr10(&mut self) -> SR10_W`[src]

Bit 10 - Subregion 10 in region n (write '1' to clear)

`pub fn sr11(&mut self) -> SR11_W`[src]

Bit 11 - Subregion 11 in region n (write '1' to clear)

`pub fn sr12(&mut self) -> SR12_W`[src]

Bit 12 - Subregion 12 in region n (write '1' to clear)

`pub fn sr13(&mut self) -> SR13_W`[src]

Bit 13 - Subregion 13 in region n (write '1' to clear)

`pub fn sr14(&mut self) -> SR14_W`[src]

Bit 14 - Subregion 14 in region n (write '1' to clear)

`pub fn sr15(&mut self) -> SR15_W`[src]

Bit 15 - Subregion 15 in region n (write '1' to clear)

`pub fn sr16(&mut self) -> SR16_W`[src]

Bit 16 - Subregion 16 in region n (write '1' to clear)

`pub fn sr17(&mut self) -> SR17_W`[src]

Bit 17 - Subregion 17 in region n (write '1' to clear)

`pub fn sr18(&mut self) -> SR18_W`[src]

Bit 18 - Subregion 18 in region n (write '1' to clear)

`pub fn sr19(&mut self) -> SR19_W`[src]

Bit 19 - Subregion 19 in region n (write '1' to clear)

`pub fn sr20(&mut self) -> SR20_W`[src]

Bit 20 - Subregion 20 in region n (write '1' to clear)

`pub fn sr21(&mut self) -> SR21_W`[src]

Bit 21 - Subregion 21 in region n (write '1' to clear)

`pub fn sr22(&mut self) -> SR22_W`[src]

Bit 22 - Subregion 22 in region n (write '1' to clear)

`pub fn sr23(&mut self) -> SR23_W`[src]

Bit 23 - Subregion 23 in region n (write '1' to clear)

`pub fn sr24(&mut self) -> SR24_W`[src]

Bit 24 - Subregion 24 in region n (write '1' to clear)

`pub fn sr25(&mut self) -> SR25_W`[src]

Bit 25 - Subregion 25 in region n (write '1' to clear)

`pub fn sr26(&mut self) -> SR26_W`[src]

Bit 26 - Subregion 26 in region n (write '1' to clear)

`pub fn sr27(&mut self) -> SR27_W`[src]

Bit 27 - Subregion 27 in region n (write '1' to clear)

`pub fn sr28(&mut self) -> SR28_W`[src]

Bit 28 - Subregion 28 in region n (write '1' to clear)

`pub fn sr29(&mut self) -> SR29_W`[src]

Bit 29 - Subregion 29 in region n (write '1' to clear)

`pub fn sr30(&mut self) -> SR30_W`[src]

Bit 30 - Subregion 30 in region n (write '1' to clear)

`pub fn sr31(&mut self) -> SR31_W`[src]

Bit 31 - Subregion 31 in region n (write '1' to clear)

`impl W<u32, Reg<u32, _START>>`[src]

`pub fn start(&mut self) -> START_W`[src]

Bits 0:31 - Start address for region

`impl W<u32, Reg<u32, _END>>`[src]

`pub fn end(&mut self) -> END_W`[src]

Bits 0:31 - End address of region.

`impl W<u32, Reg<u32, _SUBS>>`[src]

`pub fn sr0(&mut self) -> SR0_W`[src]

Bit 0 - Include or exclude subregion 0 in region

`pub fn sr1(&mut self) -> SR1_W`[src]

Bit 1 - Include or exclude subregion 1 in region

`pub fn sr2(&mut self) -> SR2_W`[src]

Bit 2 - Include or exclude subregion 2 in region

`pub fn sr3(&mut self) -> SR3_W`[src]

Bit 3 - Include or exclude subregion 3 in region

`pub fn sr4(&mut self) -> SR4_W`[src]

Bit 4 - Include or exclude subregion 4 in region

`pub fn sr5(&mut self) -> SR5_W`[src]

Bit 5 - Include or exclude subregion 5 in region

`pub fn sr6(&mut self) -> SR6_W`[src]

Bit 6 - Include or exclude subregion 6 in region

`pub fn sr7(&mut self) -> SR7_W`[src]

Bit 7 - Include or exclude subregion 7 in region

`pub fn sr8(&mut self) -> SR8_W`[src]

Bit 8 - Include or exclude subregion 8 in region

`pub fn sr9(&mut self) -> SR9_W`[src]

Bit 9 - Include or exclude subregion 9 in region

`pub fn sr10(&mut self) -> SR10_W`[src]

Bit 10 - Include or exclude subregion 10 in region

`pub fn sr11(&mut self) -> SR11_W`[src]

Bit 11 - Include or exclude subregion 11 in region

`pub fn sr12(&mut self) -> SR12_W`[src]

Bit 12 - Include or exclude subregion 12 in region

`pub fn sr13(&mut self) -> SR13_W`[src]

Bit 13 - Include or exclude subregion 13 in region

`pub fn sr14(&mut self) -> SR14_W`[src]

Bit 14 - Include or exclude subregion 14 in region

`pub fn sr15(&mut self) -> SR15_W`[src]

Bit 15 - Include or exclude subregion 15 in region

`pub fn sr16(&mut self) -> SR16_W`[src]

Bit 16 - Include or exclude subregion 16 in region

`pub fn sr17(&mut self) -> SR17_W`[src]

Bit 17 - Include or exclude subregion 17 in region

`pub fn sr18(&mut self) -> SR18_W`[src]

Bit 18 - Include or exclude subregion 18 in region

`pub fn sr19(&mut self) -> SR19_W`[src]

Bit 19 - Include or exclude subregion 19 in region

`pub fn sr20(&mut self) -> SR20_W`[src]

Bit 20 - Include or exclude subregion 20 in region

`pub fn sr21(&mut self) -> SR21_W`[src]

Bit 21 - Include or exclude subregion 21 in region

`pub fn sr22(&mut self) -> SR22_W`[src]

Bit 22 - Include or exclude subregion 22 in region

`pub fn sr23(&mut self) -> SR23_W`[src]

Bit 23 - Include or exclude subregion 23 in region

`pub fn sr24(&mut self) -> SR24_W`[src]

Bit 24 - Include or exclude subregion 24 in region

`pub fn sr25(&mut self) -> SR25_W`[src]

Bit 25 - Include or exclude subregion 25 in region

`pub fn sr26(&mut self) -> SR26_W`[src]

Bit 26 - Include or exclude subregion 26 in region

`pub fn sr27(&mut self) -> SR27_W`[src]

Bit 27 - Include or exclude subregion 27 in region

`pub fn sr28(&mut self) -> SR28_W`[src]

Bit 28 - Include or exclude subregion 28 in region

`pub fn sr29(&mut self) -> SR29_W`[src]

Bit 29 - Include or exclude subregion 29 in region

`pub fn sr30(&mut self) -> SR30_W`[src]

Bit 30 - Include or exclude subregion 30 in region

`pub fn sr31(&mut self) -> SR31_W`[src]

Bit 31 - Include or exclude subregion 31 in region

`impl W<u32, Reg<u32, _INTEN>>`[src]

`pub fn region0wa(&mut self) -> REGION0WA_W`[src]

Bit 0 - Enable or disable interrupt for REGION[0].WA event

`pub fn region0ra(&mut self) -> REGION0RA_W`[src]

Bit 1 - Enable or disable interrupt for REGION[0].RA event

`pub fn region1wa(&mut self) -> REGION1WA_W`[src]

Bit 2 - Enable or disable interrupt for REGION[1].WA event

`pub fn region1ra(&mut self) -> REGION1RA_W`[src]

Bit 3 - Enable or disable interrupt for REGION[1].RA event

`pub fn region2wa(&mut self) -> REGION2WA_W`[src]

Bit 4 - Enable or disable interrupt for REGION[2].WA event

`pub fn region2ra(&mut self) -> REGION2RA_W`[src]

Bit 5 - Enable or disable interrupt for REGION[2].RA event

`pub fn region3wa(&mut self) -> REGION3WA_W`[src]

Bit 6 - Enable or disable interrupt for REGION[3].WA event

`pub fn region3ra(&mut self) -> REGION3RA_W`[src]

Bit 7 - Enable or disable interrupt for REGION[3].RA event

`pub fn pregion0wa(&mut self) -> PREGION0WA_W`[src]

Bit 24 - Enable or disable interrupt for PREGION[0].WA event

`pub fn pregion0ra(&mut self) -> PREGION0RA_W`[src]

Bit 25 - Enable or disable interrupt for PREGION[0].RA event

`pub fn pregion1wa(&mut self) -> PREGION1WA_W`[src]

Bit 26 - Enable or disable interrupt for PREGION[1].WA event

`pub fn pregion1ra(&mut self) -> PREGION1RA_W`[src]

Bit 27 - Enable or disable interrupt for PREGION[1].RA event

`impl W<u32, Reg<u32, _INTENSET>>`[src]

`pub fn region0wa(&mut self) -> REGION0WA_W`[src]

Bit 0 - Write '1' to enable interrupt for REGION[0].WA event

`pub fn region0ra(&mut self) -> REGION0RA_W`[src]

Bit 1 - Write '1' to enable interrupt for REGION[0].RA event

`pub fn region1wa(&mut self) -> REGION1WA_W`[src]

Bit 2 - Write '1' to enable interrupt for REGION[1].WA event

`pub fn region1ra(&mut self) -> REGION1RA_W`[src]

Bit 3 - Write '1' to enable interrupt for REGION[1].RA event

`pub fn region2wa(&mut self) -> REGION2WA_W`[src]

Bit 4 - Write '1' to enable interrupt for REGION[2].WA event

`pub fn region2ra(&mut self) -> REGION2RA_W`[src]

Bit 5 - Write '1' to enable interrupt for REGION[2].RA event

`pub fn region3wa(&mut self) -> REGION3WA_W`[src]

Bit 6 - Write '1' to enable interrupt for REGION[3].WA event

`pub fn region3ra(&mut self) -> REGION3RA_W`[src]

Bit 7 - Write '1' to enable interrupt for REGION[3].RA event

`pub fn pregion0wa(&mut self) -> PREGION0WA_W`[src]

Bit 24 - Write '1' to enable interrupt for PREGION[0].WA event

`pub fn pregion0ra(&mut self) -> PREGION0RA_W`[src]

Bit 25 - Write '1' to enable interrupt for PREGION[0].RA event

`pub fn pregion1wa(&mut self) -> PREGION1WA_W`[src]

Bit 26 - Write '1' to enable interrupt for PREGION[1].WA event

`pub fn pregion1ra(&mut self) -> PREGION1RA_W`[src]

Bit 27 - Write '1' to enable interrupt for PREGION[1].RA event

`impl W<u32, Reg<u32, _INTENCLR>>`[src]

`pub fn region0wa(&mut self) -> REGION0WA_W`[src]

Bit 0 - Write '1' to disable interrupt for REGION[0].WA event

`pub fn region0ra(&mut self) -> REGION0RA_W`[src]

Bit 1 - Write '1' to disable interrupt for REGION[0].RA event

`pub fn region1wa(&mut self) -> REGION1WA_W`[src]

Bit 2 - Write '1' to disable interrupt for REGION[1].WA event

`pub fn region1ra(&mut self) -> REGION1RA_W`[src]

Bit 3 - Write '1' to disable interrupt for REGION[1].RA event

`pub fn region2wa(&mut self) -> REGION2WA_W`[src]

Bit 4 - Write '1' to disable interrupt for REGION[2].WA event

`pub fn region2ra(&mut self) -> REGION2RA_W`[src]

Bit 5 - Write '1' to disable interrupt for REGION[2].RA event

`pub fn region3wa(&mut self) -> REGION3WA_W`[src]

Bit 6 - Write '1' to disable interrupt for REGION[3].WA event

`pub fn region3ra(&mut self) -> REGION3RA_W`[src]

Bit 7 - Write '1' to disable interrupt for REGION[3].RA event

`pub fn pregion0wa(&mut self) -> PREGION0WA_W`[src]

Bit 24 - Write '1' to disable interrupt for PREGION[0].WA event

`pub fn pregion0ra(&mut self) -> PREGION0RA_W`[src]

Bit 25 - Write '1' to disable interrupt for PREGION[0].RA event

`pub fn pregion1wa(&mut self) -> PREGION1WA_W`[src]

Bit 26 - Write '1' to disable interrupt for PREGION[1].WA event

`pub fn pregion1ra(&mut self) -> PREGION1RA_W`[src]

Bit 27 - Write '1' to disable interrupt for PREGION[1].RA event

`impl W<u32, Reg<u32, _NMIEN>>`[src]

`pub fn region0wa(&mut self) -> REGION0WA_W`[src]

Bit 0 - Enable or disable non-maskable interrupt for REGION[0].WA event

`pub fn region0ra(&mut self) -> REGION0RA_W`[src]

Bit 1 - Enable or disable non-maskable interrupt for REGION[0].RA event

`pub fn region1wa(&mut self) -> REGION1WA_W`[src]

Bit 2 - Enable or disable non-maskable interrupt for REGION[1].WA event

`pub fn region1ra(&mut self) -> REGION1RA_W`[src]

Bit 3 - Enable or disable non-maskable interrupt for REGION[1].RA event

`pub fn region2wa(&mut self) -> REGION2WA_W`[src]

Bit 4 - Enable or disable non-maskable interrupt for REGION[2].WA event

`pub fn region2ra(&mut self) -> REGION2RA_W`[src]

Bit 5 - Enable or disable non-maskable interrupt for REGION[2].RA event

`pub fn region3wa(&mut self) -> REGION3WA_W`[src]

Bit 6 - Enable or disable non-maskable interrupt for REGION[3].WA event

`pub fn region3ra(&mut self) -> REGION3RA_W`[src]

Bit 7 - Enable or disable non-maskable interrupt for REGION[3].RA event

`pub fn pregion0wa(&mut self) -> PREGION0WA_W`[src]

Bit 24 - Enable or disable non-maskable interrupt for PREGION[0].WA event

`pub fn pregion0ra(&mut self) -> PREGION0RA_W`[src]

Bit 25 - Enable or disable non-maskable interrupt for PREGION[0].RA event

`pub fn pregion1wa(&mut self) -> PREGION1WA_W`[src]

Bit 26 - Enable or disable non-maskable interrupt for PREGION[1].WA event

`pub fn pregion1ra(&mut self) -> PREGION1RA_W`[src]

Bit 27 - Enable or disable non-maskable interrupt for PREGION[1].RA event

`impl W<u32, Reg<u32, _NMIENSET>>`[src]

`pub fn region0wa(&mut self) -> REGION0WA_W`[src]

Bit 0 - Write '1' to enable non-maskable interrupt for REGION[0].WA event

`pub fn region0ra(&mut self) -> REGION0RA_W`[src]

Bit 1 - Write '1' to enable non-maskable interrupt for REGION[0].RA event

`pub fn region1wa(&mut self) -> REGION1WA_W`[src]

Bit 2 - Write '1' to enable non-maskable interrupt for REGION[1].WA event

`pub fn region1ra(&mut self) -> REGION1RA_W`[src]

Bit 3 - Write '1' to enable non-maskable interrupt for REGION[1].RA event

`pub fn region2wa(&mut self) -> REGION2WA_W`[src]

Bit 4 - Write '1' to enable non-maskable interrupt for REGION[2].WA event

`pub fn region2ra(&mut self) -> REGION2RA_W`[src]

Bit 5 - Write '1' to enable non-maskable interrupt for REGION[2].RA event

`pub fn region3wa(&mut self) -> REGION3WA_W`[src]

Bit 6 - Write '1' to enable non-maskable interrupt for REGION[3].WA event

`pub fn region3ra(&mut self) -> REGION3RA_W`[src]

Bit 7 - Write '1' to enable non-maskable interrupt for REGION[3].RA event

`pub fn pregion0wa(&mut self) -> PREGION0WA_W`[src]

Bit 24 - Write '1' to enable non-maskable interrupt for PREGION[0].WA event

`pub fn pregion0ra(&mut self) -> PREGION0RA_W`[src]

Bit 25 - Write '1' to enable non-maskable interrupt for PREGION[0].RA event

`pub fn pregion1wa(&mut self) -> PREGION1WA_W`[src]

Bit 26 - Write '1' to enable non-maskable interrupt for PREGION[1].WA event

`pub fn pregion1ra(&mut self) -> PREGION1RA_W`[src]

Bit 27 - Write '1' to enable non-maskable interrupt for PREGION[1].RA event

`impl W<u32, Reg<u32, _NMIENCLR>>`[src]

`pub fn region0wa(&mut self) -> REGION0WA_W`[src]

Bit 0 - Write '1' to disable non-maskable interrupt for REGION[0].WA event

`pub fn region0ra(&mut self) -> REGION0RA_W`[src]

Bit 1 - Write '1' to disable non-maskable interrupt for REGION[0].RA event

`pub fn region1wa(&mut self) -> REGION1WA_W`[src]

Bit 2 - Write '1' to disable non-maskable interrupt for REGION[1].WA event

`pub fn region1ra(&mut self) -> REGION1RA_W`[src]

Bit 3 - Write '1' to disable non-maskable interrupt for REGION[1].RA event

`pub fn region2wa(&mut self) -> REGION2WA_W`[src]

Bit 4 - Write '1' to disable non-maskable interrupt for REGION[2].WA event

`pub fn region2ra(&mut self) -> REGION2RA_W`[src]

Bit 5 - Write '1' to disable non-maskable interrupt for REGION[2].RA event

`pub fn region3wa(&mut self) -> REGION3WA_W`[src]

Bit 6 - Write '1' to disable non-maskable interrupt for REGION[3].WA event

`pub fn region3ra(&mut self) -> REGION3RA_W`[src]

Bit 7 - Write '1' to disable non-maskable interrupt for REGION[3].RA event

`pub fn pregion0wa(&mut self) -> PREGION0WA_W`[src]

Bit 24 - Write '1' to disable non-maskable interrupt for PREGION[0].WA event

`pub fn pregion0ra(&mut self) -> PREGION0RA_W`[src]

Bit 25 - Write '1' to disable non-maskable interrupt for PREGION[0].RA event

`pub fn pregion1wa(&mut self) -> PREGION1WA_W`[src]

Bit 26 - Write '1' to disable non-maskable interrupt for PREGION[1].WA event

`pub fn pregion1ra(&mut self) -> PREGION1RA_W`[src]

Bit 27 - Write '1' to disable non-maskable interrupt for PREGION[1].RA event

`impl W<u32, Reg<u32, _REGIONEN>>`[src]

`pub fn rgn0wa(&mut self) -> RGN0WA_W`[src]

Bit 0 - Enable/disable write access watch in region[0]

`pub fn rgn0ra(&mut self) -> RGN0RA_W`[src]

Bit 1 - Enable/disable read access watch in region[0]

`pub fn rgn1wa(&mut self) -> RGN1WA_W`[src]

Bit 2 - Enable/disable write access watch in region[1]

`pub fn rgn1ra(&mut self) -> RGN1RA_W`[src]

Bit 3 - Enable/disable read access watch in region[1]

`pub fn rgn2wa(&mut self) -> RGN2WA_W`[src]

Bit 4 - Enable/disable write access watch in region[2]

`pub fn rgn2ra(&mut self) -> RGN2RA_W`[src]

Bit 5 - Enable/disable read access watch in region[2]

`pub fn rgn3wa(&mut self) -> RGN3WA_W`[src]

Bit 6 - Enable/disable write access watch in region[3]

`pub fn rgn3ra(&mut self) -> RGN3RA_W`[src]

Bit 7 - Enable/disable read access watch in region[3]

`pub fn prgn0wa(&mut self) -> PRGN0WA_W`[src]

Bit 24 - Enable/disable write access watch in PREGION[0]

`pub fn prgn0ra(&mut self) -> PRGN0RA_W`[src]

Bit 25 - Enable/disable read access watch in PREGION[0]

`pub fn prgn1wa(&mut self) -> PRGN1WA_W`[src]

Bit 26 - Enable/disable write access watch in PREGION[1]

`pub fn prgn1ra(&mut self) -> PRGN1RA_W`[src]

Bit 27 - Enable/disable read access watch in PREGION[1]

`impl W<u32, Reg<u32, _REGIONENSET>>`[src]

`pub fn rgn0wa(&mut self) -> RGN0WA_W`[src]

Bit 0 - Enable write access watch in region[0]

`pub fn rgn0ra(&mut self) -> RGN0RA_W`[src]

Bit 1 - Enable read access watch in region[0]

`pub fn rgn1wa(&mut self) -> RGN1WA_W`[src]

Bit 2 - Enable write access watch in region[1]

`pub fn rgn1ra(&mut self) -> RGN1RA_W`[src]

Bit 3 - Enable read access watch in region[1]

`pub fn rgn2wa(&mut self) -> RGN2WA_W`[src]

Bit 4 - Enable write access watch in region[2]

`pub fn rgn2ra(&mut self) -> RGN2RA_W`[src]

Bit 5 - Enable read access watch in region[2]

`pub fn rgn3wa(&mut self) -> RGN3WA_W`[src]

Bit 6 - Enable write access watch in region[3]

`pub fn rgn3ra(&mut self) -> RGN3RA_W`[src]

Bit 7 - Enable read access watch in region[3]

`pub fn prgn0wa(&mut self) -> PRGN0WA_W`[src]

Bit 24 - Enable write access watch in PREGION[0]

`pub fn prgn0ra(&mut self) -> PRGN0RA_W`[src]

Bit 25 - Enable read access watch in PREGION[0]

`pub fn prgn1wa(&mut self) -> PRGN1WA_W`[src]

Bit 26 - Enable write access watch in PREGION[1]

`pub fn prgn1ra(&mut self) -> PRGN1RA_W`[src]

Bit 27 - Enable read access watch in PREGION[1]

`impl W<u32, Reg<u32, _REGIONENCLR>>`[src]

`pub fn rgn0wa(&mut self) -> RGN0WA_W`[src]

Bit 0 - Disable write access watch in region[0]

`pub fn rgn0ra(&mut self) -> RGN0RA_W`[src]

Bit 1 - Disable read access watch in region[0]

`pub fn rgn1wa(&mut self) -> RGN1WA_W`[src]

Bit 2 - Disable write access watch in region[1]

`pub fn rgn1ra(&mut self) -> RGN1RA_W`[src]

Bit 3 - Disable read access watch in region[1]

`pub fn rgn2wa(&mut self) -> RGN2WA_W`[src]

Bit 4 - Disable write access watch in region[2]

`pub fn rgn2ra(&mut self) -> RGN2RA_W`[src]

Bit 5 - Disable read access watch in region[2]

`pub fn rgn3wa(&mut self) -> RGN3WA_W`[src]

Bit 6 - Disable write access watch in region[3]

`pub fn rgn3ra(&mut self) -> RGN3RA_W`[src]

Bit 7 - Disable read access watch in region[3]

`pub fn prgn0wa(&mut self) -> PRGN0WA_W`[src]

Bit 24 - Disable write access watch in PREGION[0]

`pub fn prgn0ra(&mut self) -> PRGN0RA_W`[src]

Bit 25 - Disable read access watch in PREGION[0]

`pub fn prgn1wa(&mut self) -> PRGN1WA_W`[src]

Bit 26 - Disable write access watch in PREGION[1]

`pub fn prgn1ra(&mut self) -> PRGN1RA_W`[src]

Bit 27 - Disable read access watch in PREGION[1]

`impl W<u32, Reg<u32, _MODE>>`[src]

`pub fn mode(&mut self) -> MODE_W`[src]

Bit 0 - I2S mode.

`impl W<u32, Reg<u32, _RXEN>>`[src]

`pub fn rxen(&mut self) -> RXEN_W`[src]

Bit 0 - Reception (RX) enable.

`impl W<u32, Reg<u32, _TXEN>>`[src]

`pub fn txen(&mut self) -> TXEN_W`[src]

Bit 0 - Transmission (TX) enable.

`impl W<u32, Reg<u32, _MCKEN>>`[src]

`pub fn mcken(&mut self) -> MCKEN_W`[src]

Bit 0 - Master clock generator enable.

`impl W<u32, Reg<u32, _MCKFREQ>>`[src]

`pub fn mckfreq(&mut self) -> MCKFREQ_W`[src]

Bits 0:31 - Master clock generator frequency.

`impl W<u32, Reg<u32, _RATIO>>`[src]

`pub fn ratio(&mut self) -> RATIO_W`[src]

Bits 0:3 - MCK / LRCK ratio.

`impl W<u32, Reg<u32, _SWIDTH>>`[src]

`pub fn swidth(&mut self) -> SWIDTH_W`[src]

Bits 0:1 - Sample width.

`impl W<u32, Reg<u32, _ALIGN>>`[src]

`pub fn align(&mut self) -> ALIGN_W`[src]

Bit 0 - Alignment of sample within a frame.

`impl W<u32, Reg<u32, _FORMAT>>`[src]

`pub fn format(&mut self) -> FORMAT_W`[src]

Bit 0 - Frame format.

`impl W<u32, Reg<u32, _CHANNELS>>`[src]

`pub fn channels(&mut self) -> CHANNELS_W`[src]

Bits 0:1 - Enable channels.

`impl W<u32, Reg<u32, _PTR>>`[src]

`pub fn ptr(&mut self) -> PTR_W`[src]

Bits 0:31 - Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address.

`impl W<u32, Reg<u32, _PTR>>`[src]

`pub fn ptr(&mut self) -> PTR_W`[src]

Bits 0:31 - Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address.

`pub fn tasks_stop(&mut self) -> TASKS_STOP_W`[src]

Bit 0

`impl W<u32, Reg<u32, _EVENTS_RXPTRUPD>>`[src]

`pub fn events_rxptrupd(&mut self) -> EVENTS_RXPTRUPD_W`[src]

Bit 0

`impl W<u32, Reg<u32, _EVENTS_STOPPED>>`[src]

`pub fn events_stopped(&mut self) -> EVENTS_STOPPED_W`[src]

Bit 0

`impl W<u32, Reg<u32, _EVENTS_TXPTRUPD>>`[src]

`pub fn events_txptrupd(&mut self) -> EVENTS_TXPTRUPD_W`[src]

Bit 0

`impl W<u32, Reg<u32, _INTEN>>`[src]

`pub fn rxptrupd(&mut self) -> RXPTRUPD_W`[src]

Bit 1 - Enable or disable interrupt for RXPTRUPD event

`pub fn stopped(&mut self) -> STOPPED_W`[src]

Bit 2 - Enable or disable interrupt for STOPPED event

`pub fn txptrupd(&mut self) -> TXPTRUPD_W`[src]

Bit 5 - Enable or disable interrupt for TXPTRUPD event

`impl W<u32, Reg<u32, _INTENSET>>`[src]

`pub fn rxptrupd(&mut self) -> RXPTRUPD_W`[src]

Bit 1 - Write '1' to enable interrupt for RXPTRUPD event

`pub fn stopped(&mut self) -> STOPPED_W`[src]

Bit 2 - Write '1' to enable interrupt for STOPPED event

`pub fn txptrupd(&mut self) -> TXPTRUPD_W`[src]

Bit 5 - Write '1' to enable interrupt for TXPTRUPD event

`impl W<u32, Reg<u32, _INTENCLR>>`[src]

`pub fn rxptrupd(&mut self) -> RXPTRUPD_W`[src]

Bit 1 - Write '1' to disable interrupt for RXPTRUPD event

`pub fn stopped(&mut self) -> STOPPED_W`[src]

`pub fn ep0datadone_startepout0(&mut self) -> EP0DATADONE_STARTEPOUT0_W`[src]

Bit 1 - Shortcut between EP0DATADONE event and STARTEPOUT[0] task

`pub fn ep0datadone_ep0status(&mut self) -> EP0DATADONE_EP0STATUS_W`[src]

Bit 2 - Shortcut between EP0DATADONE event and EP0STATUS task

`pub fn endepout0_ep0status(&mut self) -> ENDEPOUT0_EP0STATUS_W`[src]

Bit 3 - Shortcut between ENDEPOUT[0] event and EP0STATUS task

`pub fn endepout0_ep0rcvout(&mut self) -> ENDEPOUT0_EP0RCVOUT_W`[src]

Bit 4 - Shortcut between ENDEPOUT[0] event and EP0RCVOUT task

`impl W<u32, Reg<u32, _INTEN>>`[src]

`pub fn usbreset(&mut self) -> USBRESET_W`[src]

Bit 0 - Enable or disable interrupt for USBRESET event

`pub fn started(&mut self) -> STARTED_W`[src]

Bit 1 - Enable or disable interrupt for STARTED event

`pub fn endepin0(&mut self) -> ENDEPIN0_W`[src]

Bit 2 - Enable or disable interrupt for ENDEPIN[0] event

`pub fn endepin1(&mut self) -> ENDEPIN1_W`[src]

Bit 3 - Enable or disable interrupt for ENDEPIN[1] event

`pub fn endepin2(&mut self) -> ENDEPIN2_W`[src]

Bit 4 - Enable or disable interrupt for ENDEPIN[2] event

`pub fn endepin3(&mut self) -> ENDEPIN3_W`[src]

Bit 5 - Enable or disable interrupt for ENDEPIN[3] event

`pub fn endepin4(&mut self) -> ENDEPIN4_W`[src]

Bit 6 - Enable or disable interrupt for ENDEPIN[4] event

`pub fn endepin5(&mut self) -> ENDEPIN5_W`[src]

Bit 7 - Enable or disable interrupt for ENDEPIN[5] event

`pub fn endepin6(&mut self) -> ENDEPIN6_W`[src]

Bit 8 - Enable or disable interrupt for ENDEPIN[6] event

`pub fn endepin7(&mut self) -> ENDEPIN7_W`[src]

Bit 9 - Enable or disable interrupt for ENDEPIN[7] event

`pub fn ep0datadone(&mut self) -> EP0DATADONE_W`[src]

Bit 10 - Enable or disable interrupt for EP0DATADONE event

`pub fn endisoin(&mut self) -> ENDISOIN_W`[src]

Bit 11 - Enable or disable interrupt for ENDISOIN event

`pub fn endepout0(&mut self) -> ENDEPOUT0_W`[src]

Bit 12 - Enable or disable interrupt for ENDEPOUT[0] event

`pub fn endepout1(&mut self) -> ENDEPOUT1_W`[src]

Bit 13 - Enable or disable interrupt for ENDEPOUT[1] event

`pub fn endepout2(&mut self) -> ENDEPOUT2_W`[src]

Bit 14 - Enable or disable interrupt for ENDEPOUT[2] event

`pub fn endepout3(&mut self) -> ENDEPOUT3_W`[src]

Bit 15 - Enable or disable interrupt for ENDEPOUT[3] event

`pub fn endepout4(&mut self) -> ENDEPOUT4_W`[src]

Bit 16 - Enable or disable interrupt for ENDEPOUT[4] event

`pub fn endepout5(&mut self) -> ENDEPOUT5_W`[src]

Bit 17 - Enable or disable interrupt for ENDEPOUT[5] event

`pub fn endepout6(&mut self) -> ENDEPOUT6_W`[src]

Bit 18 - Enable or disable interrupt for ENDEPOUT[6] event

`pub fn endepout7(&mut self) -> ENDEPOUT7_W`[src]

Bit 19 - Enable or disable interrupt for ENDEPOUT[7] event

`pub fn endisoout(&mut self) -> ENDISOOUT_W`[src]

Bit 20 - Enable or disable interrupt for ENDISOOUT event

`pub fn sof(&mut self) -> SOF_W`[src]

Bit 21 - Enable or disable interrupt for SOF event

`pub fn usbevent(&mut self) -> USBEVENT_W`[src]

Bit 22 - Enable or disable interrupt for USBEVENT event

`pub fn ep0setup(&mut self) -> EP0SETUP_W`[src]

Bit 23 - Enable or disable interrupt for EP0SETUP event

`pub fn epdata(&mut self) -> EPDATA_W`[src]

Bit 24 - Enable or disable interrupt for EPDATA event

`impl W<u32, Reg<u32, _INTENSET>>`[src]

`pub fn usbreset(&mut self) -> USBRESET_W`[src]

Bit 0 - Write '1' to enable interrupt for USBRESET event

`pub fn started(&mut self) -> STARTED_W`[src]

Bit 1 - Write '1' to enable interrupt for STARTED event

`pub fn endepin0(&mut self) -> ENDEPIN0_W`[src]

Bit 2 - Write '1' to enable interrupt for ENDEPIN[0] event

`pub fn endepin1(&mut self) -> ENDEPIN1_W`[src]

Bit 3 - Write '1' to enable interrupt for ENDEPIN[1] event

`pub fn endepin2(&mut self) -> ENDEPIN2_W`[src]

Bit 4 - Write '1' to enable interrupt for ENDEPIN[2] event

`pub fn endepin3(&mut self) -> ENDEPIN3_W`[src]

Bit 5 - Write '1' to enable interrupt for ENDEPIN[3] event

`pub fn endepin4(&mut self) -> ENDEPIN4_W`[src]

Bit 6 - Write '1' to enable interrupt for ENDEPIN[4] event

`pub fn endepin5(&mut self) -> ENDEPIN5_W`[src]

Bit 7 - Write '1' to enable interrupt for ENDEPIN[5] event

`pub fn endepin6(&mut self) -> ENDEPIN6_W`[src]

Bit 8 - Write '1' to enable interrupt for ENDEPIN[6] event

`pub fn endepin7(&mut self) -> ENDEPIN7_W`[src]

Bit 9 - Write '1' to enable interrupt for ENDEPIN[7] event

`pub fn ep0datadone(&mut self) -> EP0DATADONE_W`[src]

Bit 10 - Write '1' to enable interrupt for EP0DATADONE event

`pub fn endisoin(&mut self) -> ENDISOIN_W`[src]

Bit 11 - Write '1' to enable interrupt for ENDISOIN event

`pub fn endepout0(&mut self) -> ENDEPOUT0_W`[src]

Bit 12 - Write '1' to enable interrupt for ENDEPOUT[0] event

`pub fn endepout1(&mut self) -> ENDEPOUT1_W`[src]

Bit 13 - Write '1' to enable interrupt for ENDEPOUT[1] event

`pub fn endepout2(&mut self) -> ENDEPOUT2_W`[src]

Bit 14 - Write '1' to enable interrupt for ENDEPOUT[2] event

`pub fn endepout3(&mut self) -> ENDEPOUT3_W`[src]

Bit 15 - Write '1' to enable interrupt for ENDEPOUT[3] event

`pub fn endepout4(&mut self) -> ENDEPOUT4_W`[src]

Bit 16 - Write '1' to enable interrupt for ENDEPOUT[4] event

`pub fn endepout5(&mut self) -> ENDEPOUT5_W`[src]

Bit 17 - Write '1' to enable interrupt for ENDEPOUT[5] event

`pub fn endepout6(&mut self) -> ENDEPOUT6_W`[src]

Bit 18 - Write '1' to enable interrupt for ENDEPOUT[6] event

`pub fn endepout7(&mut self) -> ENDEPOUT7_W`[src]

Bit 19 - Write '1' to enable interrupt for ENDEPOUT[7] event

`pub fn endisoout(&mut self) -> ENDISOOUT_W`[src]

Bit 20 - Write '1' to enable interrupt for ENDISOOUT event

`pub fn sof(&mut self) -> SOF_W`[src]

Bit 21 - Write '1' to enable interrupt for SOF event

`pub fn usbevent(&mut self) -> USBEVENT_W`[src]

Bit 22 - Write '1' to enable interrupt for USBEVENT event

`pub fn ep0setup(&mut self) -> EP0SETUP_W`[src]

Bit 23 - Write '1' to enable interrupt for EP0SETUP event

`pub fn epdata(&mut self) -> EPDATA_W`[src]

Bit 24 - Write '1' to enable interrupt for EPDATA event

`impl W<u32, Reg<u32, _INTENCLR>>`[src]

`pub fn usbreset(&mut self) -> USBRESET_W`[src]

Bit 0 - Write '1' to disable interrupt for USBRESET event

`pub fn started(&mut self) -> STARTED_W`[src]

Bit 1 - Write '1' to disable interrupt for STARTED event

`pub fn endepin0(&mut self) -> ENDEPIN0_W`[src]

Bit 2 - Write '1' to disable interrupt for ENDEPIN[0] event

`pub fn endepin1(&mut self) -> ENDEPIN1_W`[src]

Bit 3 - Write '1' to disable interrupt for ENDEPIN[1] event

`pub fn endepin2(&mut self) -> ENDEPIN2_W`[src]

Bit 4 - Write '1' to disable interrupt for ENDEPIN[2] event

`pub fn endepin3(&mut self) -> ENDEPIN3_W`[src]

Bit 5 - Write '1' to disable interrupt for ENDEPIN[3] event

`pub fn endepin4(&mut self) -> ENDEPIN4_W`[src]

Bit 6 - Write '1' to disable interrupt for ENDEPIN[4] event

`pub fn endepin5(&mut self) -> ENDEPIN5_W`[src]

Bit 7 - Write '1' to disable interrupt for ENDEPIN[5] event

`pub fn endepin6(&mut self) -> ENDEPIN6_W`[src]

Bit 8 - Write '1' to disable interrupt for ENDEPIN[6] event

`pub fn endepin7(&mut self) -> ENDEPIN7_W`[src]

Bit 9 - Write '1' to disable interrupt for ENDEPIN[7] event

`pub fn ep0datadone(&mut self) -> EP0DATADONE_W`[src]

Bit 10 - Write '1' to disable interrupt for EP0DATADONE event

`pub fn endisoin(&mut self) -> ENDISOIN_W`[src]

Bit 11 - Write '1' to disable interrupt for ENDISOIN event

`pub fn endepout0(&mut self) -> ENDEPOUT0_W`[src]

Bit 12 - Write '1' to disable interrupt for ENDEPOUT[0] event

`pub fn endepout1(&mut self) -> ENDEPOUT1_W`[src]

Bit 13 - Write '1' to disable interrupt for ENDEPOUT[1] event

`pub fn endepout2(&mut self) -> ENDEPOUT2_W`[src]

Bit 14 - Write '1' to disable interrupt for ENDEPOUT[2] event

`pub fn endepout3(&mut self) -> ENDEPOUT3_W`[src]

Bit 15 - Write '1' to disable interrupt for ENDEPOUT[3] event

`pub fn endepout4(&mut self) -> ENDEPOUT4_W`[src]

Bit 16 - Write '1' to disable interrupt for ENDEPOUT[4] event

`pub fn endepout5(&mut self) -> ENDEPOUT5_W`[src]

Bit 17 - Write '1' to disable interrupt for ENDEPOUT[5] event

`pub fn endepout6(&mut self) -> ENDEPOUT6_W`[src]

Bit 18 - Write '1' to disable interrupt for ENDEPOUT[6] event

`pub fn endepout7(&mut self) -> ENDEPOUT7_W`[src]

Bit 19 - Write '1' to disable interrupt for ENDEPOUT[7] event

`pub fn endisoout(&mut self) -> ENDISOOUT_W`[src]

Bit 20 - Write '1' to disable interrupt for ENDISOOUT event

`pub fn sof(&mut self) -> SOF_W`[src]

Bit 21 - Write '1' to disable interrupt for SOF event

`pub fn usbevent(&mut self) -> USBEVENT_W`[src]

Bit 22 - Write '1' to disable interrupt for USBEVENT event

`pub fn ep0setup(&mut self) -> EP0SETUP_W`[src]

Bit 23 - Write '1' to disable interrupt for EP0SETUP event

`pub fn epdata(&mut self) -> EPDATA_W`[src]

Bit 24 - Write '1' to disable interrupt for EPDATA event

`impl W<u32, Reg<u32, _EVENTCAUSE>>`[src]

`pub fn isooutcrc(&mut self) -> ISOOUTCRC_W`[src]

Bit 0 - CRC error was detected on isochronous OUT endpoint 8. Write '1' to clear.

`pub fn suspend(&mut self) -> SUSPEND_W`[src]

Bit 8 - Signals that USB lines have been idle long enough for the device to enter suspend. Write '1' to clear.

`pub fn resume(&mut self) -> RESUME_W`[src]

Bit 9 - Signals that a RESUME condition (K state or activity restart) has been detected on USB lines. Write '1' to clear.

`pub fn usbwuallowed(&mut self) -> USBWUALLOWED_W`[src]

Bit 10 - USB MAC has been woken up and operational. Write '1' to clear.

`pub fn ready(&mut self) -> READY_W`[src]

Bit 11 - USB device is ready for normal operation. Write '1' to clear.

`impl W<u32, Reg<u32, _EPSTATUS>>`[src]

`pub fn epin0(&mut self) -> EPIN0_W`[src]

Bit 0 - Captured state of endpoint's EasyDMA registers. Write '1' to clear.

`pub fn epin1(&mut self) -> EPIN1_W`[src]

Bit 1 - Captured state of endpoint's EasyDMA registers. Write '1' to clear.

`pub fn epin2(&mut self) -> EPIN2_W`[src]

Bit 2 - Captured state of endpoint's EasyDMA registers. Write '1' to clear.

`pub fn epin3(&mut self) -> EPIN3_W`[src]

Bit 3 - Captured state of endpoint's EasyDMA registers. Write '1' to clear.

`pub fn epin4(&mut self) -> EPIN4_W`[src]

Bit 4 - Captured state of endpoint's EasyDMA registers. Write '1' to clear.

`pub fn epin5(&mut self) -> EPIN5_W`[src]

Bit 5 - Captured state of endpoint's EasyDMA registers. Write '1' to clear.

`pub fn epin6(&mut self) -> EPIN6_W`[src]

Bit 6 - Captured state of endpoint's EasyDMA registers. Write '1' to clear.

`pub fn epin7(&mut self) -> EPIN7_W`[src]

Bit 7 - Captured state of endpoint's EasyDMA registers. Write '1' to clear.

`pub fn epin8(&mut self) -> EPIN8_W`[src]

Bit 8 - Captured state of endpoint's EasyDMA registers. Write '1' to clear.

`pub fn epout0(&mut self) -> EPOUT0_W`[src]

Bit 16 - Captured state of endpoint's EasyDMA registers. Write '1' to clear.

`pub fn epout1(&mut self) -> EPOUT1_W`[src]

Bit 17 - Captured state of endpoint's EasyDMA registers. Write '1' to clear.

`pub fn epout2(&mut self) -> EPOUT2_W`[src]

Bit 18 - Captured state of endpoint's EasyDMA registers. Write '1' to clear.

`pub fn epout3(&mut self) -> EPOUT3_W`[src]

Bit 19 - Captured state of endpoint's EasyDMA registers. Write '1' to clear.

`pub fn epout4(&mut self) -> EPOUT4_W`[src]

Bit 20 - Captured state of endpoint's EasyDMA registers. Write '1' to clear.

`pub fn epout5(&mut self) -> EPOUT5_W`[src]

Bit 21 - Captured state of endpoint's EasyDMA registers. Write '1' to clear.

`pub fn epout6(&mut self) -> EPOUT6_W`[src]

Bit 22 - Captured state of endpoint's EasyDMA registers. Write '1' to clear.

`pub fn epout7(&mut self) -> EPOUT7_W`[src]

Bit 23 - Captured state of endpoint's EasyDMA registers. Write '1' to clear.

`pub fn epout8(&mut self) -> EPOUT8_W`[src]

Bit 24 - Captured state of endpoint's EasyDMA registers. Write '1' to clear.

`impl W<u32, Reg<u32, _EPDATASTATUS>>`[src]

`pub fn epin1(&mut self) -> EPIN1_W`[src]

Bit 1 - Acknowledged data transfer on this IN endpoint. Write '1' to clear.

`pub fn epin2(&mut self) -> EPIN2_W`[src]

Bit 2 - Acknowledged data transfer on this IN endpoint. Write '1' to clear.

`pub fn epin3(&mut self) -> EPIN3_W`[src]

Bit 3 - Acknowledged data transfer on this IN endpoint. Write '1' to clear.

`pub fn epin4(&mut self) -> EPIN4_W`[src]

Bit 4 - Acknowledged data transfer on this IN endpoint. Write '1' to clear.

`pub fn epin5(&mut self) -> EPIN5_W`[src]

Bit 5 - Acknowledged data transfer on this IN endpoint. Write '1' to clear.

`pub fn epin6(&mut self) -> EPIN6_W`[src]

Bit 6 - Acknowledged data transfer on this IN endpoint. Write '1' to clear.

`pub fn epin7(&mut self) -> EPIN7_W`[src]

Bit 7 - Acknowledged data transfer on this IN endpoint. Write '1' to clear.

`pub fn epout1(&mut self) -> EPOUT1_W`[src]

Bit 17 - Acknowledged data transfer on this OUT endpoint. Write '1' to clear.

`pub fn epout2(&mut self) -> EPOUT2_W`[src]

Bit 18 - Acknowledged data transfer on this OUT endpoint. Write '1' to clear.

`pub fn epout3(&mut self) -> EPOUT3_W`[src]

Bit 19 - Acknowledged data transfer on this OUT endpoint. Write '1' to clear.

`pub fn epout4(&mut self) -> EPOUT4_W`[src]

Bit 20 - Acknowledged data transfer on this OUT endpoint. Write '1' to clear.

`pub fn epout5(&mut self) -> EPOUT5_W`[src]

Bit 21 - Acknowledged data transfer on this OUT endpoint. Write '1' to clear.

`pub fn epout6(&mut self) -> EPOUT6_W`[src]

Bit 22 - Acknowledged data transfer on this OUT endpoint. Write '1' to clear.

`pub fn epout7(&mut self) -> EPOUT7_W`[src]

Bit 23 - Acknowledged data transfer on this OUT endpoint. Write '1' to clear.

`impl W<u32, Reg<u32, _ENABLE>>`[src]

`pub fn enable(&mut self) -> ENABLE_W`[src]

Bit 0 - Enable USB

`impl W<u32, Reg<u32, _USBPULLUP>>`[src]

`pub fn connect(&mut self) -> CONNECT_W`[src]

Bit 0 - Control of the USB pull-up on the D+ line

`impl W<u32, Reg<u32, _DPDMVALUE>>`[src]

`pub fn state(&mut self) -> STATE_W`[src]

Bits 0:4 - State D+ and D- lines will be forced into by the DPDMDRIVE task

`impl W<u32, Reg<u32, _DTOGGLE>>`[src]

`pub fn ep(&mut self) -> EP_W`[src]

Bits 0:2 - Select bulk endpoint number

`pub fn io(&mut self) -> IO_W`[src]

Bit 7 - Selects IN or OUT endpoint

`pub fn value(&mut self) -> VALUE_W`[src]

Bits 8:9 - Data toggle value

`impl W<u32, Reg<u32, _EPINEN>>`[src]

`pub fn in0(&mut self) -> IN0_W`[src]

Bit 0 - Enable IN endpoint 0

`pub fn in1(&mut self) -> IN1_W`[src]

Bit 1 - Enable IN endpoint 1

`pub fn in2(&mut self) -> IN2_W`[src]

Bit 2 - Enable IN endpoint 2

`pub fn in3(&mut self) -> IN3_W`[src]

Bit 3 - Enable IN endpoint 3

`pub fn in4(&mut self) -> IN4_W`[src]

Bit 4 - Enable IN endpoint 4

`pub fn in5(&mut self) -> IN5_W`[src]

Bit 5 - Enable IN endpoint 5

`pub fn in6(&mut self) -> IN6_W`[src]

Bit 6 - Enable IN endpoint 6

`pub fn in7(&mut self) -> IN7_W`[src]

Bit 7 - Enable IN endpoint 7

`pub fn isoin(&mut self) -> ISOIN_W`[src]

Bit 8 - Enable ISO IN endpoint

`impl W<u32, Reg<u32, _EPOUTEN>>`[src]

`pub fn out0(&mut self) -> OUT0_W`[src]

Bit 0 - Enable OUT endpoint 0

`pub fn out1(&mut self) -> OUT1_W`[src]

Bit 1 - Enable OUT endpoint 1

`pub fn out2(&mut self) -> OUT2_W`[src]

Bit 2 - Enable OUT endpoint 2

`pub fn out3(&mut self) -> OUT3_W`[src]

Bit 3 - Enable OUT endpoint 3

`pub fn out4(&mut self) -> OUT4_W`[src]

Bit 4 - Enable OUT endpoint 4

`pub fn out5(&mut self) -> OUT5_W`[src]

Bit 5 - Enable OUT endpoint 5

`pub fn out6(&mut self) -> OUT6_W`[src]

Bit 6 - Enable OUT endpoint 6

`pub fn out7(&mut self) -> OUT7_W`[src]

Bit 7 - Enable OUT endpoint 7

`pub fn isoout(&mut self) -> ISOOUT_W`[src]

Bit 8 - Enable ISO OUT endpoint 8

`impl W<u32, Reg<u32, _EPSTALL>>`[src]

`pub fn ep(&mut self) -> EP_W`[src]

Bits 0:2 - Select endpoint number

`pub fn io(&mut self) -> IO_W`[src]

Bit 7 - Selects IN or OUT endpoint

`pub fn stall(&mut self) -> STALL_W`[src]

Bit 8 - Stall selected endpoint

`impl W<u32, Reg<u32, _ISOSPLIT>>`[src]

`pub fn split(&mut self) -> SPLIT_W`[src]

Bits 0:15 - Controls the split of ISO buffers

`impl W<u32, Reg<u32, _LOWPOWER>>`[src]

`pub fn lowpower(&mut self) -> LOWPOWER_W`[src]

Bit 0 - Controls USBD peripheral low-power mode during USB suspend

`impl W<u32, Reg<u32, _ISOINCONFIG>>`[src]

`pub fn response(&mut self) -> RESPONSE_W`[src]

Bit 0 - Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent

`impl W<u32, Reg<u32, _SRC>>`[src]

`pub fn src(&mut self) -> SRC_W`[src]

Bits 0:31 - Word-aligned flash memory source address.

`impl W<u32, Reg<u32, _DST>>`[src]

`pub fn dst(&mut self) -> DST_W`[src]

Bits 0:31 - Word-aligned RAM destination address.

`impl W<u32, Reg<u32, _CNT>>`[src]

`pub fn cnt(&mut self) -> CNT_W`[src]

Bits 0:20 - Read transfer length in number of bytes. The length must be a multiple of 4 bytes.

`impl W<u32, Reg<u32, _DST>>`[src]

`pub fn dst(&mut self) -> DST_W`[src]

Bits 0:31 - Word-aligned flash destination address.

`impl W<u32, Reg<u32, _SRC>>`[src]

`pub fn src(&mut self) -> SRC_W`[src]

Bits 0:31 - Word-aligned RAM source address.

`impl W<u32, Reg<u32, _CNT>>`[src]

`pub fn cnt(&mut self) -> CNT_W`[src]

Bits 0:20 - Write transfer length in number of bytes. The length must be a multiple of 4 bytes.

`impl W<u32, Reg<u32, _PTR>>`[src]

`pub fn ptr(&mut self) -> PTR_W`[src]

Bits 0:31 - Word-aligned start address of block to be erased.

`pub fn readoc(&mut self) -> READOC_W`[src]

Bits 0:2 - Configure number of data lines and opcode used for reading.

`pub fn writeoc(&mut self) -> WRITEOC_W`[src]

Bits 3:5 - Configure number of data lines and opcode used for writing.

`pub fn addrmode(&mut self) -> ADDRMODE_W`[src]

Bit 6 - Addressing mode.

`pub fn dpmenable(&mut self) -> DPMENABLE_W`[src]

Bit 7 - Enable deep power-down mode (DPM) feature.

`pub fn ppsize(&mut self) -> PPSIZE_W`[src]

Bit 12 - Page size for commands PP, PP2O, PP4O and PP4IO.

`impl W<u32, Reg<u32, _IFCONFIG1>>`[src]

`pub fn sckdelay(&mut self) -> SCKDELAY_W`[src]

Bits 0:7 - Minimum amount of time that the CSN pin must stay high before it can go low again. Value is specified in number of 16 MHz periods (62.5 ns).

`pub fn dpmen(&mut self) -> DPMEN_W`[src]

Bit 24 - Enter/exit deep power-down mode (DPM) for external flash memory.

`pub fn spimode(&mut self) -> SPIMODE_W`[src]

Bit 25 - Select SPI mode.

`pub fn sckfreq(&mut self) -> SCKFREQ_W`[src]

Bits 28:31 - SCK frequency is given as 32 MHz / (SCKFREQ + 1).

`impl W<u32, Reg<u32, _DPMDUR>>`[src]

`pub fn enter(&mut self) -> ENTER_W`[src]

Bits 0:15 - Duration needed by external flash to enter DPM. Duration is given as ENTER * 256 * 62.5 ns.

`pub fn exit(&mut self) -> EXIT_W`[src]

Bits 16:31 - Duration needed by external flash to exit DPM. Duration is given as EXIT * 256 * 62.5 ns.

`impl W<u32, Reg<u32, _ADDRCONF>>`[src]

`pub fn opcode(&mut self) -> OPCODE_W`[src]

Bits 0:7 - Opcode that enters the 32-bit addressing mode.

`pub fn byte0(&mut self) -> BYTE0_W`[src]

Bits 8:15 - Byte 0 following opcode.

`pub fn byte1(&mut self) -> BYTE1_W`[src]

Bits 16:23 - Byte 1 following byte 0.

`pub fn mode(&mut self) -> MODE_W`[src]

Bits 24:25 - Extended addressing mode.

`pub fn wipwait(&mut self) -> WIPWAIT_W`[src]

Bit 26 - Wait for write complete before sending command.

`pub fn wren(&mut self) -> WREN_W`[src]

Bit 27 - Send WREN (write enable opcode 0x06) before instruction.

`impl W<u32, Reg<u32, _CINSTRCONF>>`[src]

`pub fn opcode(&mut self) -> OPCODE_W`[src]

Bits 0:7 - Opcode of Custom instruction.

`pub fn length(&mut self) -> LENGTH_W`[src]

Bits 8:11 - Length of custom instruction in number of bytes.

`pub fn lio2(&mut self) -> LIO2_W`[src]

Bit 12 - Level of the IO2 pin (if connected) during transmission of custom instruction.

`pub fn lio3(&mut self) -> LIO3_W`[src]

Bit 13 - Level of the IO3 pin (if connected) during transmission of custom instruction.

`pub fn wipwait(&mut self) -> WIPWAIT_W`[src]

Bit 14 - Wait for write complete before sending command.

`pub fn wren(&mut self) -> WREN_W`[src]

Bit 15 - Send WREN (write enable opcode 0x06) before instruction.

`pub fn lfen(&mut self) -> LFEN_W`[src]

Bit 16 - Enable long frame mode. When enabled, a custom instruction transaction has to be ended by writing the LFSTOP field.

`pub fn lfstop(&mut self) -> LFSTOP_W`[src]

Bit 17 - Stop (finalize) long frame transaction

`impl W<u32, Reg<u32, _CINSTRDAT0>>`[src]

`pub fn byte0(&mut self) -> BYTE0_W`[src]

Bits 0:7 - Data byte 0

`pub fn byte1(&mut self) -> BYTE1_W`[src]

Bits 8:15 - Data byte 1

`pub fn byte2(&mut self) -> BYTE2_W`[src]

Bits 16:23 - Data byte 2

`pub fn byte3(&mut self) -> BYTE3_W`[src]

Bits 24:31 - Data byte 3

`impl W<u32, Reg<u32, _CINSTRDAT1>>`[src]

`pub fn byte4(&mut self) -> BYTE4_W`[src]

Bits 0:7 - Data byte 4

`pub fn byte5(&mut self) -> BYTE5_W`[src]

Bits 8:15 - Data byte 5

`pub fn byte6(&mut self) -> BYTE6_W`[src]

Bits 16:23 - Data byte 6

`pub fn byte7(&mut self) -> BYTE7_W`[src]

Bits 24:31 - Data byte 7

`impl W<u32, Reg<u32, _IFTIMING>>`[src]

`pub fn rxdelay(&mut self) -> RXDELAY_W`[src]

Bits 8:10 - Timing related to sampling of the input serial data. The value of RXDELAY specifies the number of 64 MHz cycles (15.625 ns) delay from the the rising edge of the SPI Clock (SCK) until the input serial data is sampled. As en example, if set to 0 the input serial data is sampled on the rising edge of SCK.

`impl W<u32, Reg<u32, _OUT>>`[src]

`pub fn pin0(&mut self) -> PIN0_W`[src]

Bit 0 - Pin 0

`pub fn pin1(&mut self) -> PIN1_W`[src]

Bit 1 - Pin 1

`pub fn pin2(&mut self) -> PIN2_W`[src]

Bit 2 - Pin 2

`pub fn pin3(&mut self) -> PIN3_W`[src]

Bit 3 - Pin 3

`pub fn pin4(&mut self) -> PIN4_W`[src]

Bit 4 - Pin 4

`pub fn pin5(&mut self) -> PIN5_W`[src]

Bit 5 - Pin 5

`pub fn pin6(&mut self) -> PIN6_W`[src]

Bit 6 - Pin 6

`pub fn pin7(&mut self) -> PIN7_W`[src]

Bit 7 - Pin 7

`pub fn pin8(&mut self) -> PIN8_W`[src]

Bit 8 - Pin 8

`pub fn pin9(&mut self) -> PIN9_W`[src]

Bit 9 - Pin 9

`pub fn pin10(&mut self) -> PIN10_W`[src]

Bit 10 - Pin 10

`pub fn pin11(&mut self) -> PIN11_W`[src]

Bit 11 - Pin 11

`pub fn pin12(&mut self) -> PIN12_W`[src]

Bit 12 - Pin 12

`pub fn pin13(&mut self) -> PIN13_W`[src]

Bit 13 - Pin 13

`pub fn pin14(&mut self) -> PIN14_W`[src]

Bit 14 - Pin 14

`pub fn pin15(&mut self) -> PIN15_W`[src]

Bit 15 - Pin 15

`pub fn pin16(&mut self) -> PIN16_W`[src]

Bit 16 - Pin 16

`pub fn pin17(&mut self) -> PIN17_W`[src]

Bit 17 - Pin 17

`pub fn pin18(&mut self) -> PIN18_W`[src]

Bit 18 - Pin 18

`pub fn pin19(&mut self) -> PIN19_W`[src]

Bit 19 - Pin 19

`pub fn pin20(&mut self) -> PIN20_W`[src]

Bit 20 - Pin 20

`pub fn pin21(&mut self) -> PIN21_W`[src]

Bit 21 - Pin 21

`pub fn pin22(&mut self) -> PIN22_W`[src]

Bit 22 - Pin 22

`pub fn pin23(&mut self) -> PIN23_W`[src]

Bit 23 - Pin 23

`pub fn pin24(&mut self) -> PIN24_W`[src]

Bit 24 - Pin 24

`pub fn pin25(&mut self) -> PIN25_W`[src]

Bit 25 - Pin 25

`pub fn pin26(&mut self) -> PIN26_W`[src]

Bit 26 - Pin 26

`pub fn pin27(&mut self) -> PIN27_W`[src]

Bit 27 - Pin 27

`pub fn pin28(&mut self) -> PIN28_W`[src]

Bit 28 - Pin 28

`pub fn pin29(&mut self) -> PIN29_W`[src]

Bit 29 - Pin 29

`pub fn pin30(&mut self) -> PIN30_W`[src]

Bit 30 - Pin 30

`pub fn pin31(&mut self) -> PIN31_W`[src]

Bit 31 - Pin 31

`impl W<u32, Reg<u32, _OUTSET>>`[src]

`pub fn pin0(&mut self) -> PIN0_W`[src]

Bit 0 - Pin 0

`pub fn pin1(&mut self) -> PIN1_W`[src]

Bit 1 - Pin 1

`pub fn pin2(&mut self) -> PIN2_W`[src]

Bit 2 - Pin 2

`pub fn pin3(&mut self) -> PIN3_W`[src]

Bit 3 - Pin 3

`pub fn pin4(&mut self) -> PIN4_W`[src]

Bit 4 - Pin 4

`pub fn pin5(&mut self) -> PIN5_W`[src]

Bit 5 - Pin 5

`pub fn pin6(&mut self) -> PIN6_W`[src]

Bit 6 - Pin 6

`pub fn pin7(&mut self) -> PIN7_W`[src]

Bit 7 - Pin 7

`pub fn pin8(&mut self) -> PIN8_W`[src]

Bit 8 - Pin 8

`pub fn pin9(&mut self) -> PIN9_W`[src]

Bit 9 - Pin 9

`pub fn pin10(&mut self) -> PIN10_W`[src]

Bit 10 - Pin 10

`pub fn pin11(&mut self) -> PIN11_W`[src]

Bit 11 - Pin 11

`pub fn pin12(&mut self) -> PIN12_W`[src]

Bit 12 - Pin 12

`pub fn pin13(&mut self) -> PIN13_W`[src]

Bit 13 - Pin 13

`pub fn pin14(&mut self) -> PIN14_W`[src]

Bit 14 - Pin 14

`pub fn pin15(&mut self) -> PIN15_W`[src]

Bit 15 - Pin 15

`pub fn pin16(&mut self) -> PIN16_W`[src]

Bit 16 - Pin 16

`pub fn pin17(&mut self) -> PIN17_W`[src]

Bit 17 - Pin 17

`pub fn pin18(&mut self) -> PIN18_W`[src]

Bit 18 - Pin 18

`pub fn pin19(&mut self) -> PIN19_W`[src]

Bit 19 - Pin 19

`pub fn pin20(&mut self) -> PIN20_W`[src]

Bit 20 - Pin 20

`pub fn pin21(&mut self) -> PIN21_W`[src]

Bit 21 - Pin 21

`pub fn pin22(&mut self) -> PIN22_W`[src]

Bit 22 - Pin 22

`pub fn pin23(&mut self) -> PIN23_W`[src]

Bit 23 - Pin 23

`pub fn pin24(&mut self) -> PIN24_W`[src]

Bit 24 - Pin 24

`pub fn pin25(&mut self) -> PIN25_W`[src]

Bit 25 - Pin 25

`pub fn pin26(&mut self) -> PIN26_W`[src]

Bit 26 - Pin 26

`pub fn pin27(&mut self) -> PIN27_W`[src]

Bit 27 - Pin 27

`pub fn pin28(&mut self) -> PIN28_W`[src]

Bit 28 - Pin 28

`pub fn pin29(&mut self) -> PIN29_W`[src]

Bit 29 - Pin 29

`pub fn pin30(&mut self) -> PIN30_W`[src]

Bit 30 - Pin 30

`pub fn pin31(&mut self) -> PIN31_W`[src]

Bit 31 - Pin 31

`impl W<u32, Reg<u32, _OUTCLR>>`[src]

`pub fn pin0(&mut self) -> PIN0_W`[src]

Bit 0 - Pin 0

`pub fn pin1(&mut self) -> PIN1_W`[src]

Bit 1 - Pin 1

`pub fn pin2(&mut self) -> PIN2_W`[src]

Bit 2 - Pin 2

`pub fn pin3(&mut self) -> PIN3_W`[src]

Bit 3 - Pin 3

`pub fn pin4(&mut self) -> PIN4_W`[src]

Bit 4 - Pin 4

`pub fn pin5(&mut self) -> PIN5_W`[src]

Bit 5 - Pin 5

`pub fn pin6(&mut self) -> PIN6_W`[src]

Bit 6 - Pin 6

`pub fn pin7(&mut self) -> PIN7_W`[src]

Bit 7 - Pin 7

`pub fn pin8(&mut self) -> PIN8_W`[src]

Bit 8 - Pin 8

`pub fn pin9(&mut self) -> PIN9_W`[src]

Bit 9 - Pin 9

`pub fn pin10(&mut self) -> PIN10_W`[src]

Bit 10 - Pin 10

`pub fn pin11(&mut self) -> PIN11_W`[src]

Bit 11 - Pin 11

`pub fn pin12(&mut self) -> PIN12_W`[src]

Bit 12 - Pin 12

`pub fn pin13(&mut self) -> PIN13_W`[src]

Bit 13 - Pin 13

`pub fn pin14(&mut self) -> PIN14_W`[src]

Bit 14 - Pin 14

`pub fn pin15(&mut self) -> PIN15_W`[src]

Bit 15 - Pin 15

`pub fn pin16(&mut self) -> PIN16_W`[src]

Bit 16 - Pin 16

`pub fn pin17(&mut self) -> PIN17_W`[src]

Bit 17 - Pin 17

`pub fn pin18(&mut self) -> PIN18_W`[src]

Bit 18 - Pin 18

`pub fn pin19(&mut self) -> PIN19_W`[src]

Bit 19 - Pin 19

`pub fn pin20(&mut self) -> PIN20_W`[src]

Bit 20 - Pin 20

`pub fn pin21(&mut self) -> PIN21_W`[src]

Bit 21 - Pin 21

`pub fn pin22(&mut self) -> PIN22_W`[src]

Bit 22 - Pin 22

`pub fn pin23(&mut self) -> PIN23_W`[src]

Bit 23 - Pin 23

`pub fn pin24(&mut self) -> PIN24_W`[src]

Bit 24 - Pin 24

`pub fn pin25(&mut self) -> PIN25_W`[src]

Bit 25 - Pin 25

`pub fn pin26(&mut self) -> PIN26_W`[src]

Bit 26 - Pin 26

`pub fn pin27(&mut self) -> PIN27_W`[src]

Bit 27 - Pin 27

`pub fn pin28(&mut self) -> PIN28_W`[src]

Bit 28 - Pin 28

`pub fn pin29(&mut self) -> PIN29_W`[src]

Bit 29 - Pin 29

`pub fn pin30(&mut self) -> PIN30_W`[src]

Bit 30 - Pin 30

`pub fn pin31(&mut self) -> PIN31_W`[src]

Bit 31 - Pin 31

`impl W<u32, Reg<u32, _DIR>>`[src]

`pub fn pin0(&mut self) -> PIN0_W`[src]

Bit 0 - Pin 0

`pub fn pin1(&mut self) -> PIN1_W`[src]

Bit 1 - Pin 1

`pub fn pin2(&mut self) -> PIN2_W`[src]

Bit 2 - Pin 2

`pub fn pin3(&mut self) -> PIN3_W`[src]

Bit 3 - Pin 3

`pub fn pin4(&mut self) -> PIN4_W`[src]

Bit 4 - Pin 4

`pub fn pin5(&mut self) -> PIN5_W`[src]

Bit 5 - Pin 5

`pub fn pin6(&mut self) -> PIN6_W`[src]

Bit 6 - Pin 6

`pub fn pin7(&mut self) -> PIN7_W`[src]

Bit 7 - Pin 7

`pub fn pin8(&mut self) -> PIN8_W`[src]

Bit 8 - Pin 8

`pub fn pin9(&mut self) -> PIN9_W`[src]

Bit 9 - Pin 9

`pub fn pin10(&mut self) -> PIN10_W`[src]

Bit 10 - Pin 10

`pub fn pin11(&mut self) -> PIN11_W`[src]

Bit 11 - Pin 11

`pub fn pin12(&mut self) -> PIN12_W`[src]

Bit 12 - Pin 12

`pub fn pin13(&mut self) -> PIN13_W`[src]

Bit 13 - Pin 13

`pub fn pin14(&mut self) -> PIN14_W`[src]

Bit 14 - Pin 14

`pub fn pin15(&mut self) -> PIN15_W`[src]

Bit 15 - Pin 15

`pub fn pin16(&mut self) -> PIN16_W`[src]

Bit 16 - Pin 16

`pub fn pin17(&mut self) -> PIN17_W`[src]

Bit 17 - Pin 17

`pub fn pin18(&mut self) -> PIN18_W`[src]

Bit 18 - Pin 18

`pub fn pin19(&mut self) -> PIN19_W`[src]

Bit 19 - Pin 19

`pub fn pin20(&mut self) -> PIN20_W`[src]

Bit 20 - Pin 20

`pub fn pin21(&mut self) -> PIN21_W`[src]

Bit 21 - Pin 21

`pub fn pin22(&mut self) -> PIN22_W`[src]

Bit 22 - Pin 22

`pub fn pin23(&mut self) -> PIN23_W`[src]

Bit 23 - Pin 23

`pub fn pin24(&mut self) -> PIN24_W`[src]

Bit 24 - Pin 24

`pub fn pin25(&mut self) -> PIN25_W`[src]

Bit 25 - Pin 25

`pub fn pin26(&mut self) -> PIN26_W`[src]

Bit 26 - Pin 26

`pub fn pin27(&mut self) -> PIN27_W`[src]

Bit 27 - Pin 27

`pub fn pin28(&mut self) -> PIN28_W`[src]

Bit 28 - Pin 28

`pub fn pin29(&mut self) -> PIN29_W`[src]

Bit 29 - Pin 29

`pub fn pin30(&mut self) -> PIN30_W`[src]

Bit 30 - Pin 30

`pub fn pin31(&mut self) -> PIN31_W`[src]

Bit 31 - Pin 31

`impl W<u32, Reg<u32, _DIRSET>>`[src]

`pub fn pin0(&mut self) -> PIN0_W`[src]

Bit 0 - Set as output pin 0

`pub fn pin1(&mut self) -> PIN1_W`[src]

Bit 1 - Set as output pin 1

`pub fn pin2(&mut self) -> PIN2_W`[src]

Bit 2 - Set as output pin 2

`pub fn pin3(&mut self) -> PIN3_W`[src]

Bit 3 - Set as output pin 3

`pub fn pin4(&mut self) -> PIN4_W`[src]

Bit 4 - Set as output pin 4

`pub fn pin5(&mut self) -> PIN5_W`[src]

Bit 5 - Set as output pin 5

`pub fn pin6(&mut self) -> PIN6_W`[src]

Bit 6 - Set as output pin 6

`pub fn pin7(&mut self) -> PIN7_W`[src]

Bit 7 - Set as output pin 7

`pub fn pin8(&mut self) -> PIN8_W`[src]

Bit 8 - Set as output pin 8

`pub fn pin9(&mut self) -> PIN9_W`[src]

Bit 9 - Set as output pin 9

`pub fn pin10(&mut self) -> PIN10_W`[src]

Bit 10 - Set as output pin 10

`pub fn pin11(&mut self) -> PIN11_W`[src]

Bit 11 - Set as output pin 11

`pub fn pin12(&mut self) -> PIN12_W`[src]

Bit 12 - Set as output pin 12

`pub fn pin13(&mut self) -> PIN13_W`[src]

Bit 13 - Set as output pin 13

`pub fn pin14(&mut self) -> PIN14_W`[src]

Bit 14 - Set as output pin 14

`pub fn pin15(&mut self) -> PIN15_W`[src]

Bit 15 - Set as output pin 15

`pub fn pin16(&mut self) -> PIN16_W`[src]

Bit 16 - Set as output pin 16

`pub fn pin17(&mut self) -> PIN17_W`[src]

Bit 17 - Set as output pin 17

`pub fn pin18(&mut self) -> PIN18_W`[src]

Bit 18 - Set as output pin 18

`pub fn pin19(&mut self) -> PIN19_W`[src]

Bit 19 - Set as output pin 19

`pub fn pin20(&mut self) -> PIN20_W`[src]

Bit 20 - Set as output pin 20

`pub fn pin21(&mut self) -> PIN21_W`[src]

Bit 21 - Set as output pin 21

`pub fn pin22(&mut self) -> PIN22_W`[src]

Bit 22 - Set as output pin 22

`pub fn pin23(&mut self) -> PIN23_W`[src]

Bit 23 - Set as output pin 23

`pub fn pin24(&mut self) -> PIN24_W`[src]

Bit 24 - Set as output pin 24

`pub fn pin25(&mut self) -> PIN25_W`[src]

Bit 25 - Set as output pin 25

`pub fn pin26(&mut self) -> PIN26_W`[src]

Bit 26 - Set as output pin 26

`pub fn pin27(&mut self) -> PIN27_W`[src]

Bit 27 - Set as output pin 27

`pub fn pin28(&mut self) -> PIN28_W`[src]

Bit 28 - Set as output pin 28

`pub fn pin29(&mut self) -> PIN29_W`[src]

Bit 29 - Set as output pin 29

`pub fn pin30(&mut self) -> PIN30_W`[src]

Bit 30 - Set as output pin 30

`pub fn pin31(&mut self) -> PIN31_W`[src]

Bit 31 - Set as output pin 31

`impl W<u32, Reg<u32, _DIRCLR>>`[src]

`pub fn pin0(&mut self) -> PIN0_W`[src]

Bit 0 - Set as input pin 0

`pub fn pin1(&mut self) -> PIN1_W`[src]

Bit 1 - Set as input pin 1

`pub fn pin2(&mut self) -> PIN2_W`[src]

Bit 2 - Set as input pin 2

`pub fn pin3(&mut self) -> PIN3_W`[src]

Bit 3 - Set as input pin 3

`pub fn pin4(&mut self) -> PIN4_W`[src]

Bit 4 - Set as input pin 4

`pub fn pin5(&mut self) -> PIN5_W`[src]

Bit 5 - Set as input pin 5

`pub fn pin6(&mut self) -> PIN6_W`[src]

Bit 6 - Set as input pin 6

`pub fn pin7(&mut self) -> PIN7_W`[src]

Bit 7 - Set as input pin 7

`pub fn pin8(&mut self) -> PIN8_W`[src]

Bit 8 - Set as input pin 8

`pub fn pin9(&mut self) -> PIN9_W`[src]

Bit 9 - Set as input pin 9

`pub fn pin10(&mut self) -> PIN10_W`[src]

Bit 10 - Set as input pin 10

`pub fn pin11(&mut self) -> PIN11_W`[src]

Bit 11 - Set as input pin 11

`pub fn pin12(&mut self) -> PIN12_W`[src]

Bit 12 - Set as input pin 12

`pub fn pin13(&mut self) -> PIN13_W`[src]

Bit 13 - Set as input pin 13

`pub fn pin14(&mut self) -> PIN14_W`[src]

Bit 14 - Set as input pin 14

`pub fn pin15(&mut self) -> PIN15_W`[src]

Bit 15 - Set as input pin 15

`pub fn pin16(&mut self) -> PIN16_W`[src]

Bit 16 - Set as input pin 16

`pub fn pin17(&mut self) -> PIN17_W`[src]

Bit 17 - Set as input pin 17

`pub fn pin18(&mut self) -> PIN18_W`[src]

Bit 18 - Set as input pin 18

`pub fn pin19(&mut self) -> PIN19_W`[src]

Bit 19 - Set as input pin 19

`pub fn pin20(&mut self) -> PIN20_W`[src]

Bit 20 - Set as input pin 20

`pub fn pin21(&mut self) -> PIN21_W`[src]

Bit 21 - Set as input pin 21

`pub fn pin22(&mut self) -> PIN22_W`[src]

Bit 22 - Set as input pin 22

`pub fn pin23(&mut self) -> PIN23_W`[src]

Bit 23 - Set as input pin 23

`pub fn pin24(&mut self) -> PIN24_W`[src]

Bit 24 - Set as input pin 24

`pub fn pin25(&mut self) -> PIN25_W`[src]

Bit 25 - Set as input pin 25

`pub fn pin26(&mut self) -> PIN26_W`[src]

Bit 26 - Set as input pin 26

`pub fn pin27(&mut self) -> PIN27_W`[src]

Bit 27 - Set as input pin 27

`pub fn pin28(&mut self) -> PIN28_W`[src]

Bit 28 - Set as input pin 28

`pub fn pin29(&mut self) -> PIN29_W`[src]

Bit 29 - Set as input pin 29

`pub fn pin30(&mut self) -> PIN30_W`[src]

Bit 30 - Set as input pin 30

`pub fn pin31(&mut self) -> PIN31_W`[src]

Bit 31 - Set as input pin 31

`impl W<u32, Reg<u32, _LATCH>>`[src]

`pub fn pin0(&mut self) -> PIN0_W`[src]

Bit 0 - Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear.

`pub fn pin1(&mut self) -> PIN1_W`[src]

Bit 1 - Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear.

`pub fn pin2(&mut self) -> PIN2_W`[src]

Bit 2 - Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear.

`pub fn pin3(&mut self) -> PIN3_W`[src]

Bit 3 - Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear.

`pub fn pin4(&mut self) -> PIN4_W`[src]

Bit 4 - Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear.

`pub fn pin5(&mut self) -> PIN5_W`[src]

Bit 5 - Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear.

`pub fn pin6(&mut self) -> PIN6_W`[src]

Bit 6 - Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear.

`pub fn pin7(&mut self) -> PIN7_W`[src]

Bit 7 - Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear.

`pub fn pin8(&mut self) -> PIN8_W`[src]

Bit 8 - Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear.

`pub fn pin9(&mut self) -> PIN9_W`[src]

Bit 9 - Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear.

`pub fn pin10(&mut self) -> PIN10_W`[src]

Bit 10 - Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear.

`pub fn pin11(&mut self) -> PIN11_W`[src]

Bit 11 - Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear.

`pub fn pin12(&mut self) -> PIN12_W`[src]

Bit 12 - Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear.

`pub fn pin13(&mut self) -> PIN13_W`[src]

Bit 13 - Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear.

`pub fn pin14(&mut self) -> PIN14_W`[src]

Bit 14 - Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear.

`pub fn pin15(&mut self) -> PIN15_W`[src]

Bit 15 - Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear.

`pub fn pin16(&mut self) -> PIN16_W`[src]

Bit 16 - Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear.

`pub fn pin17(&mut self) -> PIN17_W`[src]

Bit 17 - Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear.

`pub fn pin18(&mut self) -> PIN18_W`[src]

Bit 18 - Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear.

`pub fn pin19(&mut self) -> PIN19_W`[src]

Bit 19 - Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear.

`pub fn pin20(&mut self) -> PIN20_W`[src]

Bit 20 - Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear.

`pub fn pin21(&mut self) -> PIN21_W`[src]

Bit 21 - Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear.

`pub fn pin22(&mut self) -> PIN22_W`[src]

Bit 22 - Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear.

`pub fn pin23(&mut self) -> PIN23_W`[src]

Bit 23 - Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear.

`pub fn pin24(&mut self) -> PIN24_W`[src]

Bit 24 - Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear.

`pub fn pin25(&mut self) -> PIN25_W`[src]

Bit 25 - Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear.

`pub fn pin26(&mut self) -> PIN26_W`[src]

Bit 26 - Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear.

`pub fn pin27(&mut self) -> PIN27_W`[src]

Bit 27 - Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear.

`pub fn pin28(&mut self) -> PIN28_W`[src]

Bit 28 - Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear.

`pub fn pin29(&mut self) -> PIN29_W`[src]

Bit 29 - Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear.

`pub fn pin30(&mut self) -> PIN30_W`[src]

Bit 30 - Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear.

`pub fn pin31(&mut self) -> PIN31_W`[src]

Bit 31 - Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear.

`impl W<u32, Reg<u32, _DETECTMODE>>`[src]

`pub fn detectmode(&mut self) -> DETECTMODE_W`[src]

Bit 0 - Select between default DETECT signal behaviour and LDETECT mode

`impl W<u32, Reg<u32, _PIN_CNF>>`[src]

`pub fn dir(&mut self) -> DIR_W`[src]

Bit 0 - Pin direction. Same physical register as DIR register

`pub fn input(&mut self) -> INPUT_W`[src]

Bit 1 - Connect or disconnect input buffer

`pub fn pull(&mut self) -> PULL_W`[src]

Bits 2:3 - Pull configuration

`pub fn drive(&mut self) -> DRIVE_W`[src]

Bits 8:10 - Drive configuration

`pub fn sense(&mut self) -> SENSE_W`[src]

Bits 16:17 - Pin sensing mechanism

`impl W<u32, Reg<u32, _HOST_CRYPTOKEY_SEL>>`[src]

`pub fn host_cryptokey_sel(&mut self) -> HOST_CRYPTOKEY_SEL_W`[src]

Bits 0:1 - Select the source of the HW key that is used by the AES engine

`impl W<u32, Reg<u32, _HOST_IOT_KPRTL_LOCK>>`[src]

`pub fn host_iot_kprtl_lock(&mut self) -> HOST_IOT_KPRTL_LOCK_W`[src]

Bit 0 - This register is the K_PRTL lock register. When this register is set, K_PRTL can not be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain.

`impl W<u32, Reg<u32, _HOST_IOT_KDR0>>`[src]

`pub fn host_iot_kdr0(&mut self) -> HOST_IOT_KDR0_W`[src]

Bits 0:31 - Write: K_DR bits 31:0 Read: 0x00000000 when 128-bit K_DR key value is not yet retained in the CRYPTOCELL AO power domain Read: 0x00000001 when 128-bit K_DR key value is successfully retained in the CRYPTOCELL AO power domain

`impl W<u32, Reg<u32, _HOST_IOT_KDR1>>`[src]

`pub fn host_iot_kdr1(&mut self) -> HOST_IOT_KDR1_W`[src]

Bits 0:31 - K_DR bits 63:32

`impl W<u32, Reg<u32, _HOST_IOT_KDR2>>`[src]

`pub fn host_iot_kdr2(&mut self) -> HOST_IOT_KDR2_W`[src]

Bits 0:31 - K_DR bits 95:64

`impl W<u32, Reg<u32, _HOST_IOT_KDR3>>`[src]

`pub fn host_iot_kdr3(&mut self) -> HOST_IOT_KDR3_W`[src]

Bits 0:31 - K_DR bits 127:96

`impl W<u32, Reg<u32, _HOST_IOT_LCS>>`[src]

`pub fn lcs(&mut self) -> LCS_W`[src]

Bits 0:2 - Lifecycle state value. This field is write-once per reset.

`pub fn lcs_is_valid(&mut self) -> LCS_IS_VALID_W`[src]

Bit 8 - This field is read-only and indicates if CRYPTOCELL LCS has been successfully configured since last reset

`impl W<u32, Reg<u32, _ENABLE>>`[src]

`pub fn enable(&mut self) -> ENABLE_W`[src]

Bit 0 - Enable or disable the CRYPTOCELL subsystem

Auto Trait Implementations

`impl<U, REG> Send for W<U, REG> where REG: Send, U: Send,`

`impl<U, REG> Sync for W<U, REG> where REG: Sync, U: Sync,`

`impl<U, REG> Unpin for W<U, REG> where REG: Unpin, U: Unpin,`

Blanket Implementations

`impl<T> Any for T where T: 'static + ?Sized,` [src]

`fn type_id(&self) -> TypeId`[src]

`impl<T> Borrow<T> for T where T: ?Sized,` [src]

`fn borrow(&self) -> &T`[src]

`impl<T> BorrowMut<T> for T where T: ?Sized,` [src]

`fn borrow_mut(&mut self) -> &mut T`[src]

`impl<T> From<T> for T`[src]

`fn from(t: T) -> T`[src]

`impl<T, U> Into for T where U: From<T>,` [src]

`fn into(self) -> U`[src]

`impl<T> Same<T> for T`

`type Output = T`

Should always be Self

`impl<T, U> TryFrom for T where U: Into<T>,` [src]

`type Error = Infallible`

The type returned in the event of a conversion error.

`fn try_from(value: U) -> Result<T, <T as TryFrom>::Error>`[src]

`impl<T, U> TryInto for T where U: TryFrom<T>,` [src]

`type Error = >::Error`

The type returned in the event of a conversion error.

[−][src]Struct nrf52840_hal::pac::generic::W

Implementations

impl<U, REG> W<U, REG>[src]

pub unsafe fn bits(&mut self, bits: U) -> &mut W<U, REG>[src]

impl W<u32, Reg<u32, _NRFFW>>[src]

pub fn nrffw(&mut self) -> NRFFW_W[src]

impl W<u32, Reg<u32, _NRFHW>>[src]

pub fn nrfhw(&mut self) -> NRFHW_W[src]

impl W<u32, Reg<u32, _CUSTOMER>>[src]

pub fn customer(&mut self) -> CUSTOMER_W[src]

impl W<u32, Reg<u32, _PSELRESET>>[src]

pub fn pin(&mut self) -> PIN_W[src]

pub fn port(&mut self) -> PORT_W[src]

pub fn connect(&mut self) -> CONNECT_W[src]

impl W<u32, Reg<u32, _APPROTECT>>[src]

pub fn pall(&mut self) -> PALL_W[src]

impl W<u32, Reg<u32, _NFCPINS>>[src]

pub fn protect(&mut self) -> PROTECT_W[src]

impl W<u32, Reg<u32, _DEBUGCTRL>>[src]

pub fn cpuniden(&mut self) -> CPUNIDEN_W[src]

pub fn cpufpben(&mut self) -> CPUFPBEN_W[src]

impl W<u32, Reg<u32, _REGOUT0>>[src]

pub fn vout(&mut self) -> VOUT_W[src]

impl W<u32, Reg<u32, _TASKS_HFCLKSTART>>[src]

pub fn tasks_hfclkstart(&mut self) -> TASKS_HFCLKSTART_W[src]

impl W<u32, Reg<u32, _TASKS_HFCLKSTOP>>[src]

pub fn tasks_hfclkstop(&mut self) -> TASKS_HFCLKSTOP_W[src]

impl W<u32, Reg<u32, _TASKS_LFCLKSTART>>[src]

pub fn tasks_lfclkstart(&mut self) -> TASKS_LFCLKSTART_W[src]

impl W<u32, Reg<u32, _TASKS_LFCLKSTOP>>[src]

pub fn tasks_lfclkstop(&mut self) -> TASKS_LFCLKSTOP_W[src]

impl W<u32, Reg<u32, _TASKS_CAL>>[src]

pub fn tasks_cal(&mut self) -> TASKS_CAL_W[src]

impl W<u32, Reg<u32, _TASKS_CTSTART>>[src]

pub fn tasks_ctstart(&mut self) -> TASKS_CTSTART_W[src]

impl W<u32, Reg<u32, _TASKS_CTSTOP>>[src]

pub fn tasks_ctstop(&mut self) -> TASKS_CTSTOP_W[src]

impl W<u32, Reg<u32, _EVENTS_HFCLKSTARTED>>[src]

pub fn events_hfclkstarted(&mut self) -> EVENTS_HFCLKSTARTED_W[src]

impl W<u32, Reg<u32, _EVENTS_LFCLKSTARTED>>[src]

pub fn events_lfclkstarted(&mut self) -> EVENTS_LFCLKSTARTED_W[src]

impl W<u32, Reg<u32, _EVENTS_DONE>>[src]

pub fn events_done(&mut self) -> EVENTS_DONE_W[src]

impl W<u32, Reg<u32, _EVENTS_CTTO>>[src]

pub fn events_ctto(&mut self) -> EVENTS_CTTO_W[src]

impl W<u32, Reg<u32, _EVENTS_CTSTARTED>>[src]

pub fn events_ctstarted(&mut self) -> EVENTS_CTSTARTED_W[src]

impl W<u32, Reg<u32, _EVENTS_CTSTOPPED>>[src]

pub fn events_ctstopped(&mut self) -> EVENTS_CTSTOPPED_W[src]

impl W<u32, Reg<u32, _INTENSET>>[src]

pub fn hfclkstarted(&mut self) -> HFCLKSTARTED_W[src]

pub fn lfclkstarted(&mut self) -> LFCLKSTARTED_W[src]

pub fn done(&mut self) -> DONE_W[src]

pub fn ctto(&mut self) -> CTTO_W[src]

pub fn ctstarted(&mut self) -> CTSTARTED_W[src]

pub fn ctstopped(&mut self) -> CTSTOPPED_W[src]

impl W<u32, Reg<u32, _INTENCLR>>[src]

pub fn hfclkstarted(&mut self) -> HFCLKSTARTED_W[src]

pub fn lfclkstarted(&mut self) -> LFCLKSTARTED_W[src]

pub fn done(&mut self) -> DONE_W[src]

pub fn ctto(&mut self) -> CTTO_W[src]

pub fn ctstarted(&mut self) -> CTSTARTED_W[src]

pub fn ctstopped(&mut self) -> CTSTOPPED_W[src]

impl W<u32, Reg<u32, _LFCLKSRC>>[src]

pub fn src(&mut self) -> SRC_W[src]

pub fn bypass(&mut self) -> BYPASS_W[src]

pub fn external(&mut self) -> EXTERNAL_W[src]

impl W<u32, Reg<u32, _HFXODEBOUNCE>>[src]

pub fn hfxodebounce(&mut self) -> HFXODEBOUNCE_W[src]

impl W<u32, Reg<u32, _CTIV>>[src]

pub fn ctiv(&mut self) -> CTIV_W[src]

impl W<u32, Reg<u32, _TRACECONFIG>>[src]

pub fn traceportspeed(&mut self) -> TRACEPORTSPEED_W[src]

pub fn tracemux(&mut self) -> TRACEMUX_W[src]

impl W<u32, Reg<u32, _LFRCMODE>>[src]

pub fn mode(&mut self) -> MODE_W[src]

pub fn status(&mut self) -> STATUS_W[src]

impl W<u32, Reg<u32, _POWER>>[src]

pub fn s0power(&mut self) -> S0POWER_W[src]

pub fn s1power(&mut self) -> S1POWER_W[src]

`impl<U, REG> W<U, REG>`[src]

`pub unsafe fn bits(&mut self, bits: U) -> &mut W<U, REG>`[src]

`impl W<u32, Reg<u32, _NRFFW>>`[src]

`pub fn nrffw(&mut self) -> NRFFW_W`[src]

`impl W<u32, Reg<u32, _NRFHW>>`[src]

`pub fn nrfhw(&mut self) -> NRFHW_W`[src]

`impl W<u32, Reg<u32, _CUSTOMER>>`[src]

`pub fn customer(&mut self) -> CUSTOMER_W`[src]

`impl W<u32, Reg<u32, _PSELRESET>>`[src]

`pub fn pin(&mut self) -> PIN_W`[src]

`pub fn port(&mut self) -> PORT_W`[src]

`pub fn connect(&mut self) -> CONNECT_W`[src]

`impl W<u32, Reg<u32, _APPROTECT>>`[src]

`pub fn pall(&mut self) -> PALL_W`[src]

`impl W<u32, Reg<u32, _NFCPINS>>`[src]

`pub fn protect(&mut self) -> PROTECT_W`[src]

`impl W<u32, Reg<u32, _DEBUGCTRL>>`[src]

`pub fn cpuniden(&mut self) -> CPUNIDEN_W`[src]

`pub fn cpufpben(&mut self) -> CPUFPBEN_W`[src]

`impl W<u32, Reg<u32, _REGOUT0>>`[src]

`pub fn vout(&mut self) -> VOUT_W`[src]

`impl W<u32, Reg<u32, _TASKS_HFCLKSTART>>`[src]

`pub fn tasks_hfclkstart(&mut self) -> TASKS_HFCLKSTART_W`[src]

`impl W<u32, Reg<u32, _TASKS_HFCLKSTOP>>`[src]

`pub fn tasks_hfclkstop(&mut self) -> TASKS_HFCLKSTOP_W`[src]

`impl W<u32, Reg<u32, _TASKS_LFCLKSTART>>`[src]

`pub fn tasks_lfclkstart(&mut self) -> TASKS_LFCLKSTART_W`[src]

`impl W<u32, Reg<u32, _TASKS_LFCLKSTOP>>`[src]

`pub fn tasks_lfclkstop(&mut self) -> TASKS_LFCLKSTOP_W`[src]

`impl W<u32, Reg<u32, _TASKS_CAL>>`[src]

`pub fn tasks_cal(&mut self) -> TASKS_CAL_W`[src]

`impl W<u32, Reg<u32, _TASKS_CTSTART>>`[src]

`pub fn tasks_ctstart(&mut self) -> TASKS_CTSTART_W`[src]

`impl W<u32, Reg<u32, _TASKS_CTSTOP>>`[src]

`pub fn tasks_ctstop(&mut self) -> TASKS_CTSTOP_W`[src]

`impl W<u32, Reg<u32, _EVENTS_HFCLKSTARTED>>`[src]

`pub fn events_hfclkstarted(&mut self) -> EVENTS_HFCLKSTARTED_W`[src]

`impl W<u32, Reg<u32, _EVENTS_LFCLKSTARTED>>`[src]

`pub fn events_lfclkstarted(&mut self) -> EVENTS_LFCLKSTARTED_W`[src]

`impl W<u32, Reg<u32, _EVENTS_DONE>>`[src]

`pub fn events_done(&mut self) -> EVENTS_DONE_W`[src]

`impl W<u32, Reg<u32, _EVENTS_CTTO>>`[src]

`pub fn events_ctto(&mut self) -> EVENTS_CTTO_W`[src]

`impl W<u32, Reg<u32, _EVENTS_CTSTARTED>>`[src]

`pub fn events_ctstarted(&mut self) -> EVENTS_CTSTARTED_W`[src]

`impl W<u32, Reg<u32, _EVENTS_CTSTOPPED>>`[src]

`pub fn events_ctstopped(&mut self) -> EVENTS_CTSTOPPED_W`[src]

`impl W<u32, Reg<u32, _INTENSET>>`[src]

`pub fn hfclkstarted(&mut self) -> HFCLKSTARTED_W`[src]

`pub fn lfclkstarted(&mut self) -> LFCLKSTARTED_W`[src]

`pub fn done(&mut self) -> DONE_W`[src]

`pub fn ctto(&mut self) -> CTTO_W`[src]

`pub fn ctstarted(&mut self) -> CTSTARTED_W`[src]

`pub fn ctstopped(&mut self) -> CTSTOPPED_W`[src]

`impl W<u32, Reg<u32, _INTENCLR>>`[src]

`pub fn hfclkstarted(&mut self) -> HFCLKSTARTED_W`[src]

`pub fn lfclkstarted(&mut self) -> LFCLKSTARTED_W`[src]

`pub fn done(&mut self) -> DONE_W`[src]

`pub fn ctto(&mut self) -> CTTO_W`[src]

`pub fn ctstarted(&mut self) -> CTSTARTED_W`[src]

`pub fn ctstopped(&mut self) -> CTSTOPPED_W`[src]

`impl W<u32, Reg<u32, _LFCLKSRC>>`[src]

`pub fn src(&mut self) -> SRC_W`[src]

`pub fn bypass(&mut self) -> BYPASS_W`[src]

`pub fn external(&mut self) -> EXTERNAL_W`[src]

`impl W<u32, Reg<u32, _HFXODEBOUNCE>>`[src]

`pub fn hfxodebounce(&mut self) -> HFXODEBOUNCE_W`[src]

`impl W<u32, Reg<u32, _CTIV>>`[src]

`pub fn ctiv(&mut self) -> CTIV_W`[src]

`impl W<u32, Reg<u32, _TRACECONFIG>>`[src]

`pub fn traceportspeed(&mut self) -> TRACEPORTSPEED_W`[src]

`pub fn tracemux(&mut self) -> TRACEMUX_W`[src]

`impl W<u32, Reg<u32, _LFRCMODE>>`[src]

`pub fn mode(&mut self) -> MODE_W`[src]

`pub fn status(&mut self) -> STATUS_W`[src]

`impl W<u32, Reg<u32, _POWER>>`[src]

`pub fn s0power(&mut self) -> S0POWER_W`[src]

`pub fn s1power(&mut self) -> S1POWER_W`[src]

`pub fn s2power(&mut self) -> S2POWER_W`[src]

`pub fn s3power(&mut self) -> S3POWER_W`[src]