Struct nrf52833_hal::pac::spim0::iftiming::rxdelay::R [−][src]
pub struct R(_);
Expand description
Register RXDELAY
reader
Implementations
Bits 0:2 - Sample delay for input serial data on MISO. The value specifies the number of 64 MHz clock cycles (15.625 ns) delay from the the sampling edge of SCK (leading edge for CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA = 1) until the input serial data is sampled. As en example, if RXDELAY = 0 and CONFIG.CPHA = 0, the input serial data is sampled on the rising edge of SCK.
Methods from Deref<Target = R<RXDELAY_SPEC>>
Reads raw bits from register.
Trait Implementations
Performs the conversion.
Auto Trait Implementations
Blanket Implementations
Mutably borrows from an owned value. Read more
Casts the value.
Performs the conversion.
Performs the conversion.
Casts the value.
Casts the value.
Casts the value.
Casts the value.