pub struct W(/* private fields */);
Expand description
Register INTENSET
writer
Implementations§
source§impl W
impl W
sourcepub fn ready(
&mut self
) -> BitWriterRaw<'_, u32, INTENSET_SPEC, READY_AW, BitM, 0>
pub fn ready( &mut self ) -> BitWriterRaw<'_, u32, INTENSET_SPEC, READY_AW, BitM, 0>
Bit 0 - Write ‘1’ to Enable interrupt for READY event
sourcepub fn fielddetected(
&mut self
) -> BitWriterRaw<'_, u32, INTENSET_SPEC, FIELDDETECTED_AW, BitM, 1>
pub fn fielddetected( &mut self ) -> BitWriterRaw<'_, u32, INTENSET_SPEC, FIELDDETECTED_AW, BitM, 1>
Bit 1 - Write ‘1’ to Enable interrupt for FIELDDETECTED event
sourcepub fn fieldlost(
&mut self
) -> BitWriterRaw<'_, u32, INTENSET_SPEC, FIELDLOST_AW, BitM, 2>
pub fn fieldlost( &mut self ) -> BitWriterRaw<'_, u32, INTENSET_SPEC, FIELDLOST_AW, BitM, 2>
Bit 2 - Write ‘1’ to Enable interrupt for FIELDLOST event
sourcepub fn txframestart(
&mut self
) -> BitWriterRaw<'_, u32, INTENSET_SPEC, TXFRAMESTART_AW, BitM, 3>
pub fn txframestart( &mut self ) -> BitWriterRaw<'_, u32, INTENSET_SPEC, TXFRAMESTART_AW, BitM, 3>
Bit 3 - Write ‘1’ to Enable interrupt for TXFRAMESTART event
sourcepub fn txframeend(
&mut self
) -> BitWriterRaw<'_, u32, INTENSET_SPEC, TXFRAMEEND_AW, BitM, 4>
pub fn txframeend( &mut self ) -> BitWriterRaw<'_, u32, INTENSET_SPEC, TXFRAMEEND_AW, BitM, 4>
Bit 4 - Write ‘1’ to Enable interrupt for TXFRAMEEND event
sourcepub fn rxframestart(
&mut self
) -> BitWriterRaw<'_, u32, INTENSET_SPEC, RXFRAMESTART_AW, BitM, 5>
pub fn rxframestart( &mut self ) -> BitWriterRaw<'_, u32, INTENSET_SPEC, RXFRAMESTART_AW, BitM, 5>
Bit 5 - Write ‘1’ to Enable interrupt for RXFRAMESTART event
sourcepub fn rxframeend(
&mut self
) -> BitWriterRaw<'_, u32, INTENSET_SPEC, RXFRAMEEND_AW, BitM, 6>
pub fn rxframeend( &mut self ) -> BitWriterRaw<'_, u32, INTENSET_SPEC, RXFRAMEEND_AW, BitM, 6>
Bit 6 - Write ‘1’ to Enable interrupt for RXFRAMEEND event
sourcepub fn error(
&mut self
) -> BitWriterRaw<'_, u32, INTENSET_SPEC, ERROR_AW, BitM, 7>
pub fn error( &mut self ) -> BitWriterRaw<'_, u32, INTENSET_SPEC, ERROR_AW, BitM, 7>
Bit 7 - Write ‘1’ to Enable interrupt for ERROR event
sourcepub fn rxerror(
&mut self
) -> BitWriterRaw<'_, u32, INTENSET_SPEC, RXERROR_AW, BitM, 10>
pub fn rxerror( &mut self ) -> BitWriterRaw<'_, u32, INTENSET_SPEC, RXERROR_AW, BitM, 10>
Bit 10 - Write ‘1’ to Enable interrupt for RXERROR event
sourcepub fn endrx(
&mut self
) -> BitWriterRaw<'_, u32, INTENSET_SPEC, ENDRX_AW, BitM, 11>
pub fn endrx( &mut self ) -> BitWriterRaw<'_, u32, INTENSET_SPEC, ENDRX_AW, BitM, 11>
Bit 11 - Write ‘1’ to Enable interrupt for ENDRX event
sourcepub fn endtx(
&mut self
) -> BitWriterRaw<'_, u32, INTENSET_SPEC, ENDTX_AW, BitM, 12>
pub fn endtx( &mut self ) -> BitWriterRaw<'_, u32, INTENSET_SPEC, ENDTX_AW, BitM, 12>
Bit 12 - Write ‘1’ to Enable interrupt for ENDTX event
sourcepub fn autocolresstarted(
&mut self
) -> BitWriterRaw<'_, u32, INTENSET_SPEC, AUTOCOLRESSTARTED_AW, BitM, 14>
pub fn autocolresstarted( &mut self ) -> BitWriterRaw<'_, u32, INTENSET_SPEC, AUTOCOLRESSTARTED_AW, BitM, 14>
Bit 14 - Write ‘1’ to Enable interrupt for AUTOCOLRESSTARTED event
sourcepub fn collision(
&mut self
) -> BitWriterRaw<'_, u32, INTENSET_SPEC, COLLISION_AW, BitM, 18>
pub fn collision( &mut self ) -> BitWriterRaw<'_, u32, INTENSET_SPEC, COLLISION_AW, BitM, 18>
Bit 18 - Write ‘1’ to Enable interrupt for COLLISION event
sourcepub fn selected(
&mut self
) -> BitWriterRaw<'_, u32, INTENSET_SPEC, SELECTED_AW, BitM, 19>
pub fn selected( &mut self ) -> BitWriterRaw<'_, u32, INTENSET_SPEC, SELECTED_AW, BitM, 19>
Bit 19 - Write ‘1’ to Enable interrupt for SELECTED event
sourcepub fn started(
&mut self
) -> BitWriterRaw<'_, u32, INTENSET_SPEC, STARTED_AW, BitM, 20>
pub fn started( &mut self ) -> BitWriterRaw<'_, u32, INTENSET_SPEC, STARTED_AW, BitM, 20>
Bit 20 - Write ‘1’ to Enable interrupt for STARTED event
Methods from Deref<Target = W<INTENSET_SPEC>>§
sourcepub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>
pub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>
Writes raw bits to the register.