Struct nrf52832_hal::pac::generic::W [−][src]
pub struct W<U, REG> { /* fields omitted */ }
Expand description
Implementations
impl W<u32, Reg<u32, _CUSTOMER>>
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impl W<u32, Reg<u32, _CUSTOMER>>
[src]pub fn customer(&mut self) -> CUSTOMER_W<'_>
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pub fn customer(&mut self) -> CUSTOMER_W<'_>
[src]Bits 0:31 - Reserved for customer
impl W<u32, Reg<u32, _CONFIG0>>
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impl W<u32, Reg<u32, _CONFIG0>>
[src]pub fn region0(&mut self) -> REGION0_W<'_>
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pub fn region0(&mut self) -> REGION0_W<'_>
[src]Bit 0 - Enable protection for region 0. Write ‘0’ has no effect.
pub fn region1(&mut self) -> REGION1_W<'_>
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pub fn region1(&mut self) -> REGION1_W<'_>
[src]Bit 1 - Enable protection for region 1. Write ‘0’ has no effect.
pub fn region2(&mut self) -> REGION2_W<'_>
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pub fn region2(&mut self) -> REGION2_W<'_>
[src]Bit 2 - Enable protection for region 2. Write ‘0’ has no effect.
pub fn region3(&mut self) -> REGION3_W<'_>
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pub fn region3(&mut self) -> REGION3_W<'_>
[src]Bit 3 - Enable protection for region 3. Write ‘0’ has no effect.
pub fn region4(&mut self) -> REGION4_W<'_>
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pub fn region4(&mut self) -> REGION4_W<'_>
[src]Bit 4 - Enable protection for region 4. Write ‘0’ has no effect.
pub fn region5(&mut self) -> REGION5_W<'_>
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pub fn region5(&mut self) -> REGION5_W<'_>
[src]Bit 5 - Enable protection for region 5. Write ‘0’ has no effect.
pub fn region6(&mut self) -> REGION6_W<'_>
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pub fn region6(&mut self) -> REGION6_W<'_>
[src]Bit 6 - Enable protection for region 6. Write ‘0’ has no effect.
pub fn region7(&mut self) -> REGION7_W<'_>
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pub fn region7(&mut self) -> REGION7_W<'_>
[src]Bit 7 - Enable protection for region 7. Write ‘0’ has no effect.
pub fn region8(&mut self) -> REGION8_W<'_>
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pub fn region8(&mut self) -> REGION8_W<'_>
[src]Bit 8 - Enable protection for region 8. Write ‘0’ has no effect.
pub fn region9(&mut self) -> REGION9_W<'_>
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pub fn region9(&mut self) -> REGION9_W<'_>
[src]Bit 9 - Enable protection for region 9. Write ‘0’ has no effect.
pub fn region10(&mut self) -> REGION10_W<'_>
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pub fn region10(&mut self) -> REGION10_W<'_>
[src]Bit 10 - Enable protection for region 10. Write ‘0’ has no effect.
pub fn region11(&mut self) -> REGION11_W<'_>
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pub fn region11(&mut self) -> REGION11_W<'_>
[src]Bit 11 - Enable protection for region 11. Write ‘0’ has no effect.
pub fn region12(&mut self) -> REGION12_W<'_>
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pub fn region12(&mut self) -> REGION12_W<'_>
[src]Bit 12 - Enable protection for region 12. Write ‘0’ has no effect.
pub fn region13(&mut self) -> REGION13_W<'_>
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pub fn region13(&mut self) -> REGION13_W<'_>
[src]Bit 13 - Enable protection for region 13. Write ‘0’ has no effect.
pub fn region14(&mut self) -> REGION14_W<'_>
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pub fn region14(&mut self) -> REGION14_W<'_>
[src]Bit 14 - Enable protection for region 14. Write ‘0’ has no effect.
pub fn region15(&mut self) -> REGION15_W<'_>
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pub fn region15(&mut self) -> REGION15_W<'_>
[src]Bit 15 - Enable protection for region 15. Write ‘0’ has no effect.
pub fn region16(&mut self) -> REGION16_W<'_>
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pub fn region16(&mut self) -> REGION16_W<'_>
[src]Bit 16 - Enable protection for region 16. Write ‘0’ has no effect.
pub fn region17(&mut self) -> REGION17_W<'_>
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pub fn region17(&mut self) -> REGION17_W<'_>
[src]Bit 17 - Enable protection for region 17. Write ‘0’ has no effect.
pub fn region18(&mut self) -> REGION18_W<'_>
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pub fn region18(&mut self) -> REGION18_W<'_>
[src]Bit 18 - Enable protection for region 18. Write ‘0’ has no effect.
pub fn region19(&mut self) -> REGION19_W<'_>
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pub fn region19(&mut self) -> REGION19_W<'_>
[src]Bit 19 - Enable protection for region 19. Write ‘0’ has no effect.
pub fn region20(&mut self) -> REGION20_W<'_>
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pub fn region20(&mut self) -> REGION20_W<'_>
[src]Bit 20 - Enable protection for region 20. Write ‘0’ has no effect.
pub fn region21(&mut self) -> REGION21_W<'_>
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pub fn region21(&mut self) -> REGION21_W<'_>
[src]Bit 21 - Enable protection for region 21. Write ‘0’ has no effect.
pub fn region22(&mut self) -> REGION22_W<'_>
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pub fn region22(&mut self) -> REGION22_W<'_>
[src]Bit 22 - Enable protection for region 22. Write ‘0’ has no effect.
pub fn region23(&mut self) -> REGION23_W<'_>
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pub fn region23(&mut self) -> REGION23_W<'_>
[src]Bit 23 - Enable protection for region 23. Write ‘0’ has no effect.
pub fn region24(&mut self) -> REGION24_W<'_>
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pub fn region24(&mut self) -> REGION24_W<'_>
[src]Bit 24 - Enable protection for region 24. Write ‘0’ has no effect.
pub fn region25(&mut self) -> REGION25_W<'_>
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pub fn region25(&mut self) -> REGION25_W<'_>
[src]Bit 25 - Enable protection for region 25. Write ‘0’ has no effect.
pub fn region26(&mut self) -> REGION26_W<'_>
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pub fn region26(&mut self) -> REGION26_W<'_>
[src]Bit 26 - Enable protection for region 26. Write ‘0’ has no effect.
pub fn region27(&mut self) -> REGION27_W<'_>
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pub fn region27(&mut self) -> REGION27_W<'_>
[src]Bit 27 - Enable protection for region 27. Write ‘0’ has no effect.
pub fn region28(&mut self) -> REGION28_W<'_>
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pub fn region28(&mut self) -> REGION28_W<'_>
[src]Bit 28 - Enable protection for region 28. Write ‘0’ has no effect.
pub fn region29(&mut self) -> REGION29_W<'_>
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pub fn region29(&mut self) -> REGION29_W<'_>
[src]Bit 29 - Enable protection for region 29. Write ‘0’ has no effect.
pub fn region30(&mut self) -> REGION30_W<'_>
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pub fn region30(&mut self) -> REGION30_W<'_>
[src]Bit 30 - Enable protection for region 30. Write ‘0’ has no effect.
pub fn region31(&mut self) -> REGION31_W<'_>
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pub fn region31(&mut self) -> REGION31_W<'_>
[src]Bit 31 - Enable protection for region 31. Write ‘0’ has no effect.
impl W<u32, Reg<u32, _CONFIG1>>
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impl W<u32, Reg<u32, _CONFIG1>>
[src]pub fn region32(&mut self) -> REGION32_W<'_>
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pub fn region32(&mut self) -> REGION32_W<'_>
[src]Bit 0 - Enable protection for region 32. Write ‘0’ has no effect.
pub fn region33(&mut self) -> REGION33_W<'_>
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pub fn region33(&mut self) -> REGION33_W<'_>
[src]Bit 1 - Enable protection for region 33. Write ‘0’ has no effect.
pub fn region34(&mut self) -> REGION34_W<'_>
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pub fn region34(&mut self) -> REGION34_W<'_>
[src]Bit 2 - Enable protection for region 34. Write ‘0’ has no effect.
pub fn region35(&mut self) -> REGION35_W<'_>
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pub fn region35(&mut self) -> REGION35_W<'_>
[src]Bit 3 - Enable protection for region 35. Write ‘0’ has no effect.
pub fn region36(&mut self) -> REGION36_W<'_>
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pub fn region36(&mut self) -> REGION36_W<'_>
[src]Bit 4 - Enable protection for region 36. Write ‘0’ has no effect.
pub fn region37(&mut self) -> REGION37_W<'_>
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pub fn region37(&mut self) -> REGION37_W<'_>
[src]Bit 5 - Enable protection for region 37. Write ‘0’ has no effect.
pub fn region38(&mut self) -> REGION38_W<'_>
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pub fn region38(&mut self) -> REGION38_W<'_>
[src]Bit 6 - Enable protection for region 38. Write ‘0’ has no effect.
pub fn region39(&mut self) -> REGION39_W<'_>
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pub fn region39(&mut self) -> REGION39_W<'_>
[src]Bit 7 - Enable protection for region 39. Write ‘0’ has no effect.
pub fn region40(&mut self) -> REGION40_W<'_>
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pub fn region40(&mut self) -> REGION40_W<'_>
[src]Bit 8 - Enable protection for region 40. Write ‘0’ has no effect.
pub fn region41(&mut self) -> REGION41_W<'_>
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pub fn region41(&mut self) -> REGION41_W<'_>
[src]Bit 9 - Enable protection for region 41. Write ‘0’ has no effect.
pub fn region42(&mut self) -> REGION42_W<'_>
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pub fn region42(&mut self) -> REGION42_W<'_>
[src]Bit 10 - Enable protection for region 42. Write ‘0’ has no effect.
pub fn region43(&mut self) -> REGION43_W<'_>
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pub fn region43(&mut self) -> REGION43_W<'_>
[src]Bit 11 - Enable protection for region 43. Write ‘0’ has no effect.
pub fn region44(&mut self) -> REGION44_W<'_>
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pub fn region44(&mut self) -> REGION44_W<'_>
[src]Bit 12 - Enable protection for region 44. Write ‘0’ has no effect.
pub fn region45(&mut self) -> REGION45_W<'_>
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pub fn region45(&mut self) -> REGION45_W<'_>
[src]Bit 13 - Enable protection for region 45. Write ‘0’ has no effect.
pub fn region46(&mut self) -> REGION46_W<'_>
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pub fn region46(&mut self) -> REGION46_W<'_>
[src]Bit 14 - Enable protection for region 46. Write ‘0’ has no effect.
pub fn region47(&mut self) -> REGION47_W<'_>
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pub fn region47(&mut self) -> REGION47_W<'_>
[src]Bit 15 - Enable protection for region 47. Write ‘0’ has no effect.
pub fn region48(&mut self) -> REGION48_W<'_>
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pub fn region48(&mut self) -> REGION48_W<'_>
[src]Bit 16 - Enable protection for region 48. Write ‘0’ has no effect.
pub fn region49(&mut self) -> REGION49_W<'_>
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pub fn region49(&mut self) -> REGION49_W<'_>
[src]Bit 17 - Enable protection for region 49. Write ‘0’ has no effect.
pub fn region50(&mut self) -> REGION50_W<'_>
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pub fn region50(&mut self) -> REGION50_W<'_>
[src]Bit 18 - Enable protection for region 50. Write ‘0’ has no effect.
pub fn region51(&mut self) -> REGION51_W<'_>
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pub fn region51(&mut self) -> REGION51_W<'_>
[src]Bit 19 - Enable protection for region 51. Write ‘0’ has no effect.
pub fn region52(&mut self) -> REGION52_W<'_>
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pub fn region52(&mut self) -> REGION52_W<'_>
[src]Bit 20 - Enable protection for region 52. Write ‘0’ has no effect.
pub fn region53(&mut self) -> REGION53_W<'_>
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pub fn region53(&mut self) -> REGION53_W<'_>
[src]Bit 21 - Enable protection for region 53. Write ‘0’ has no effect.
pub fn region54(&mut self) -> REGION54_W<'_>
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pub fn region54(&mut self) -> REGION54_W<'_>
[src]Bit 22 - Enable protection for region 54. Write ‘0’ has no effect.
pub fn region55(&mut self) -> REGION55_W<'_>
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pub fn region55(&mut self) -> REGION55_W<'_>
[src]Bit 23 - Enable protection for region 55. Write ‘0’ has no effect.
pub fn region56(&mut self) -> REGION56_W<'_>
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pub fn region56(&mut self) -> REGION56_W<'_>
[src]Bit 24 - Enable protection for region 56. Write ‘0’ has no effect.
pub fn region57(&mut self) -> REGION57_W<'_>
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pub fn region57(&mut self) -> REGION57_W<'_>
[src]Bit 25 - Enable protection for region 57. Write ‘0’ has no effect.
pub fn region58(&mut self) -> REGION58_W<'_>
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pub fn region58(&mut self) -> REGION58_W<'_>
[src]Bit 26 - Enable protection for region 58. Write ‘0’ has no effect.
pub fn region59(&mut self) -> REGION59_W<'_>
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pub fn region59(&mut self) -> REGION59_W<'_>
[src]Bit 27 - Enable protection for region 59. Write ‘0’ has no effect.
pub fn region60(&mut self) -> REGION60_W<'_>
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pub fn region60(&mut self) -> REGION60_W<'_>
[src]Bit 28 - Enable protection for region 60. Write ‘0’ has no effect.
pub fn region61(&mut self) -> REGION61_W<'_>
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pub fn region61(&mut self) -> REGION61_W<'_>
[src]Bit 29 - Enable protection for region 61. Write ‘0’ has no effect.
pub fn region62(&mut self) -> REGION62_W<'_>
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pub fn region62(&mut self) -> REGION62_W<'_>
[src]Bit 30 - Enable protection for region 62. Write ‘0’ has no effect.
pub fn region63(&mut self) -> REGION63_W<'_>
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pub fn region63(&mut self) -> REGION63_W<'_>
[src]Bit 31 - Enable protection for region 63. Write ‘0’ has no effect.
impl W<u32, Reg<u32, _DISABLEINDEBUG>>
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impl W<u32, Reg<u32, _DISABLEINDEBUG>>
[src]pub fn disableindebug(&mut self) -> DISABLEINDEBUG_W<'_>
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pub fn disableindebug(&mut self) -> DISABLEINDEBUG_W<'_>
[src]Bit 0 - Disable the protection mechanism for NVM regions while in debug interface mode. This register will only disable the protection mechanism if the device is in debug interface mode.
impl W<u32, Reg<u32, _CONFIG2>>
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impl W<u32, Reg<u32, _CONFIG2>>
[src]pub fn region64(&mut self) -> REGION64_W<'_>
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pub fn region64(&mut self) -> REGION64_W<'_>
[src]Bit 0 - Enable protection for region 64. Write ‘0’ has no effect.
pub fn region65(&mut self) -> REGION65_W<'_>
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pub fn region65(&mut self) -> REGION65_W<'_>
[src]Bit 1 - Enable protection for region 65. Write ‘0’ has no effect.
pub fn region66(&mut self) -> REGION66_W<'_>
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pub fn region66(&mut self) -> REGION66_W<'_>
[src]Bit 2 - Enable protection for region 66. Write ‘0’ has no effect.
pub fn region67(&mut self) -> REGION67_W<'_>
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pub fn region67(&mut self) -> REGION67_W<'_>
[src]Bit 3 - Enable protection for region 67. Write ‘0’ has no effect.
pub fn region68(&mut self) -> REGION68_W<'_>
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pub fn region68(&mut self) -> REGION68_W<'_>
[src]Bit 4 - Enable protection for region 68. Write ‘0’ has no effect.
pub fn region69(&mut self) -> REGION69_W<'_>
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pub fn region69(&mut self) -> REGION69_W<'_>
[src]Bit 5 - Enable protection for region 69. Write ‘0’ has no effect.
pub fn region70(&mut self) -> REGION70_W<'_>
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pub fn region70(&mut self) -> REGION70_W<'_>
[src]Bit 6 - Enable protection for region 70. Write ‘0’ has no effect.
pub fn region71(&mut self) -> REGION71_W<'_>
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pub fn region71(&mut self) -> REGION71_W<'_>
[src]Bit 7 - Enable protection for region 71. Write ‘0’ has no effect.
pub fn region72(&mut self) -> REGION72_W<'_>
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pub fn region72(&mut self) -> REGION72_W<'_>
[src]Bit 8 - Enable protection for region 72. Write ‘0’ has no effect.
pub fn region73(&mut self) -> REGION73_W<'_>
[src]
pub fn region73(&mut self) -> REGION73_W<'_>
[src]Bit 9 - Enable protection for region 73. Write ‘0’ has no effect.
pub fn region74(&mut self) -> REGION74_W<'_>
[src]
pub fn region74(&mut self) -> REGION74_W<'_>
[src]Bit 10 - Enable protection for region 74. Write ‘0’ has no effect.
pub fn region75(&mut self) -> REGION75_W<'_>
[src]
pub fn region75(&mut self) -> REGION75_W<'_>
[src]Bit 11 - Enable protection for region 75. Write ‘0’ has no effect.
pub fn region76(&mut self) -> REGION76_W<'_>
[src]
pub fn region76(&mut self) -> REGION76_W<'_>
[src]Bit 12 - Enable protection for region 76. Write ‘0’ has no effect.
pub fn region77(&mut self) -> REGION77_W<'_>
[src]
pub fn region77(&mut self) -> REGION77_W<'_>
[src]Bit 13 - Enable protection for region 77. Write ‘0’ has no effect.
pub fn region78(&mut self) -> REGION78_W<'_>
[src]
pub fn region78(&mut self) -> REGION78_W<'_>
[src]Bit 14 - Enable protection for region 78. Write ‘0’ has no effect.
pub fn region79(&mut self) -> REGION79_W<'_>
[src]
pub fn region79(&mut self) -> REGION79_W<'_>
[src]Bit 15 - Enable protection for region 79. Write ‘0’ has no effect.
pub fn region80(&mut self) -> REGION80_W<'_>
[src]
pub fn region80(&mut self) -> REGION80_W<'_>
[src]Bit 16 - Enable protection for region 80. Write ‘0’ has no effect.
pub fn region81(&mut self) -> REGION81_W<'_>
[src]
pub fn region81(&mut self) -> REGION81_W<'_>
[src]Bit 17 - Enable protection for region 81. Write ‘0’ has no effect.
pub fn region82(&mut self) -> REGION82_W<'_>
[src]
pub fn region82(&mut self) -> REGION82_W<'_>
[src]Bit 18 - Enable protection for region 82. Write ‘0’ has no effect.
pub fn region83(&mut self) -> REGION83_W<'_>
[src]
pub fn region83(&mut self) -> REGION83_W<'_>
[src]Bit 19 - Enable protection for region 83. Write ‘0’ has no effect.
pub fn region84(&mut self) -> REGION84_W<'_>
[src]
pub fn region84(&mut self) -> REGION84_W<'_>
[src]Bit 20 - Enable protection for region 84. Write ‘0’ has no effect.
pub fn region85(&mut self) -> REGION85_W<'_>
[src]
pub fn region85(&mut self) -> REGION85_W<'_>
[src]Bit 21 - Enable protection for region 85. Write ‘0’ has no effect.
pub fn region86(&mut self) -> REGION86_W<'_>
[src]
pub fn region86(&mut self) -> REGION86_W<'_>
[src]Bit 22 - Enable protection for region 86. Write ‘0’ has no effect.
pub fn region87(&mut self) -> REGION87_W<'_>
[src]
pub fn region87(&mut self) -> REGION87_W<'_>
[src]Bit 23 - Enable protection for region 87. Write ‘0’ has no effect.
pub fn region88(&mut self) -> REGION88_W<'_>
[src]
pub fn region88(&mut self) -> REGION88_W<'_>
[src]Bit 24 - Enable protection for region 88. Write ‘0’ has no effect.
pub fn region89(&mut self) -> REGION89_W<'_>
[src]
pub fn region89(&mut self) -> REGION89_W<'_>
[src]Bit 25 - Enable protection for region 89. Write ‘0’ has no effect.
pub fn region90(&mut self) -> REGION90_W<'_>
[src]
pub fn region90(&mut self) -> REGION90_W<'_>
[src]Bit 26 - Enable protection for region 90. Write ‘0’ has no effect.
pub fn region91(&mut self) -> REGION91_W<'_>
[src]
pub fn region91(&mut self) -> REGION91_W<'_>
[src]Bit 27 - Enable protection for region 91. Write ‘0’ has no effect.
pub fn region92(&mut self) -> REGION92_W<'_>
[src]
pub fn region92(&mut self) -> REGION92_W<'_>
[src]Bit 28 - Enable protection for region 92. Write ‘0’ has no effect.
pub fn region93(&mut self) -> REGION93_W<'_>
[src]
pub fn region93(&mut self) -> REGION93_W<'_>
[src]Bit 29 - Enable protection for region 93. Write ‘0’ has no effect.
pub fn region94(&mut self) -> REGION94_W<'_>
[src]
pub fn region94(&mut self) -> REGION94_W<'_>
[src]Bit 30 - Enable protection for region 94. Write ‘0’ has no effect.
pub fn region95(&mut self) -> REGION95_W<'_>
[src]
pub fn region95(&mut self) -> REGION95_W<'_>
[src]Bit 31 - Enable protection for region 95. Write ‘0’ has no effect.
impl W<u32, Reg<u32, _CONFIG3>>
[src]
impl W<u32, Reg<u32, _CONFIG3>>
[src]pub fn region96(&mut self) -> REGION96_W<'_>
[src]
pub fn region96(&mut self) -> REGION96_W<'_>
[src]Bit 0 - Enable protection for region 96. Write ‘0’ has no effect.
pub fn region97(&mut self) -> REGION97_W<'_>
[src]
pub fn region97(&mut self) -> REGION97_W<'_>
[src]Bit 1 - Enable protection for region 97. Write ‘0’ has no effect.
pub fn region98(&mut self) -> REGION98_W<'_>
[src]
pub fn region98(&mut self) -> REGION98_W<'_>
[src]Bit 2 - Enable protection for region 98. Write ‘0’ has no effect.
pub fn region99(&mut self) -> REGION99_W<'_>
[src]
pub fn region99(&mut self) -> REGION99_W<'_>
[src]Bit 3 - Enable protection for region 99. Write ‘0’ has no effect.
pub fn region100(&mut self) -> REGION100_W<'_>
[src]
pub fn region100(&mut self) -> REGION100_W<'_>
[src]Bit 4 - Enable protection for region 100. Write ‘0’ has no effect.
pub fn region101(&mut self) -> REGION101_W<'_>
[src]
pub fn region101(&mut self) -> REGION101_W<'_>
[src]Bit 5 - Enable protection for region 101. Write ‘0’ has no effect.
pub fn region102(&mut self) -> REGION102_W<'_>
[src]
pub fn region102(&mut self) -> REGION102_W<'_>
[src]Bit 6 - Enable protection for region 102. Write ‘0’ has no effect.
pub fn region103(&mut self) -> REGION103_W<'_>
[src]
pub fn region103(&mut self) -> REGION103_W<'_>
[src]Bit 7 - Enable protection for region 103. Write ‘0’ has no effect.
pub fn region104(&mut self) -> REGION104_W<'_>
[src]
pub fn region104(&mut self) -> REGION104_W<'_>
[src]Bit 8 - Enable protection for region 104. Write ‘0’ has no effect.
pub fn region105(&mut self) -> REGION105_W<'_>
[src]
pub fn region105(&mut self) -> REGION105_W<'_>
[src]Bit 9 - Enable protection for region 105. Write ‘0’ has no effect.
pub fn region106(&mut self) -> REGION106_W<'_>
[src]
pub fn region106(&mut self) -> REGION106_W<'_>
[src]Bit 10 - Enable protection for region 106. Write ‘0’ has no effect.
pub fn region107(&mut self) -> REGION107_W<'_>
[src]
pub fn region107(&mut self) -> REGION107_W<'_>
[src]Bit 11 - Enable protection for region 107. Write ‘0’ has no effect.
pub fn region108(&mut self) -> REGION108_W<'_>
[src]
pub fn region108(&mut self) -> REGION108_W<'_>
[src]Bit 12 - Enable protection for region 108. Write ‘0’ has no effect.
pub fn region109(&mut self) -> REGION109_W<'_>
[src]
pub fn region109(&mut self) -> REGION109_W<'_>
[src]Bit 13 - Enable protection for region 109. Write ‘0’ has no effect.
pub fn region110(&mut self) -> REGION110_W<'_>
[src]
pub fn region110(&mut self) -> REGION110_W<'_>
[src]Bit 14 - Enable protection for region 110. Write ‘0’ has no effect.
pub fn region111(&mut self) -> REGION111_W<'_>
[src]
pub fn region111(&mut self) -> REGION111_W<'_>
[src]Bit 15 - Enable protection for region 111. Write ‘0’ has no effect.
pub fn region112(&mut self) -> REGION112_W<'_>
[src]
pub fn region112(&mut self) -> REGION112_W<'_>
[src]Bit 16 - Enable protection for region 112. Write ‘0’ has no effect.
pub fn region113(&mut self) -> REGION113_W<'_>
[src]
pub fn region113(&mut self) -> REGION113_W<'_>
[src]Bit 17 - Enable protection for region 113. Write ‘0’ has no effect.
pub fn region114(&mut self) -> REGION114_W<'_>
[src]
pub fn region114(&mut self) -> REGION114_W<'_>
[src]Bit 18 - Enable protection for region 114. Write ‘0’ has no effect.
pub fn region115(&mut self) -> REGION115_W<'_>
[src]
pub fn region115(&mut self) -> REGION115_W<'_>
[src]Bit 19 - Enable protection for region 115. Write ‘0’ has no effect.
pub fn region116(&mut self) -> REGION116_W<'_>
[src]
pub fn region116(&mut self) -> REGION116_W<'_>
[src]Bit 20 - Enable protection for region 116. Write ‘0’ has no effect.
pub fn region117(&mut self) -> REGION117_W<'_>
[src]
pub fn region117(&mut self) -> REGION117_W<'_>
[src]Bit 21 - Enable protection for region 117. Write ‘0’ has no effect.
pub fn region118(&mut self) -> REGION118_W<'_>
[src]
pub fn region118(&mut self) -> REGION118_W<'_>
[src]Bit 22 - Enable protection for region 118. Write ‘0’ has no effect.
pub fn region119(&mut self) -> REGION119_W<'_>
[src]
pub fn region119(&mut self) -> REGION119_W<'_>
[src]Bit 23 - Enable protection for region 119. Write ‘0’ has no effect.
pub fn region120(&mut self) -> REGION120_W<'_>
[src]
pub fn region120(&mut self) -> REGION120_W<'_>
[src]Bit 24 - Enable protection for region 120. Write ‘0’ has no effect.
pub fn region121(&mut self) -> REGION121_W<'_>
[src]
pub fn region121(&mut self) -> REGION121_W<'_>
[src]Bit 25 - Enable protection for region 121. Write ‘0’ has no effect.
pub fn region122(&mut self) -> REGION122_W<'_>
[src]
pub fn region122(&mut self) -> REGION122_W<'_>
[src]Bit 26 - Enable protection for region 122. Write ‘0’ has no effect.
pub fn region123(&mut self) -> REGION123_W<'_>
[src]
pub fn region123(&mut self) -> REGION123_W<'_>
[src]Bit 27 - Enable protection for region 123. Write ‘0’ has no effect.
pub fn region124(&mut self) -> REGION124_W<'_>
[src]
pub fn region124(&mut self) -> REGION124_W<'_>
[src]Bit 28 - Enable protection for region 124. Write ‘0’ has no effect.
pub fn region125(&mut self) -> REGION125_W<'_>
[src]
pub fn region125(&mut self) -> REGION125_W<'_>
[src]Bit 29 - Enable protection for region 125. Write ‘0’ has no effect.
pub fn region126(&mut self) -> REGION126_W<'_>
[src]
pub fn region126(&mut self) -> REGION126_W<'_>
[src]Bit 30 - Enable protection for region 126. Write ‘0’ has no effect.
pub fn region127(&mut self) -> REGION127_W<'_>
[src]
pub fn region127(&mut self) -> REGION127_W<'_>
[src]Bit 31 - Enable protection for region 127. Write ‘0’ has no effect.
impl W<u32, Reg<u32, _POWER>>
[src]
impl W<u32, Reg<u32, _POWER>>
[src]pub fn s0power(&mut self) -> S0POWER_W<'_>
[src]
pub fn s0power(&mut self) -> S0POWER_W<'_>
[src]Bit 0 - Keep RAM section S0 ON or OFF in System ON mode.
pub fn s1power(&mut self) -> S1POWER_W<'_>
[src]
pub fn s1power(&mut self) -> S1POWER_W<'_>
[src]Bit 1 - Keep RAM section S1 ON or OFF in System ON mode.
pub fn s0retention(&mut self) -> S0RETENTION_W<'_>
[src]
pub fn s0retention(&mut self) -> S0RETENTION_W<'_>
[src]Bit 16 - Keep retention on RAM section S0 when RAM section is in OFF
pub fn s1retention(&mut self) -> S1RETENTION_W<'_>
[src]
pub fn s1retention(&mut self) -> S1RETENTION_W<'_>
[src]Bit 17 - Keep retention on RAM section S1 when RAM section is in OFF
impl W<u32, Reg<u32, _POWERSET>>
[src]
impl W<u32, Reg<u32, _POWERSET>>
[src]pub fn s0power(&mut self) -> S0POWER_W<'_>
[src]
pub fn s0power(&mut self) -> S0POWER_W<'_>
[src]Bit 0 - Keep RAM section S0 of RAM0 on or off in System ON mode
pub fn s1power(&mut self) -> S1POWER_W<'_>
[src]
pub fn s1power(&mut self) -> S1POWER_W<'_>
[src]Bit 1 - Keep RAM section S1 of RAM0 on or off in System ON mode
pub fn s0retention(&mut self) -> S0RETENTION_W<'_>
[src]
pub fn s0retention(&mut self) -> S0RETENTION_W<'_>
[src]Bit 16 - Keep retention on RAM section S0 when RAM section is switched off
pub fn s1retention(&mut self) -> S1RETENTION_W<'_>
[src]
pub fn s1retention(&mut self) -> S1RETENTION_W<'_>
[src]Bit 17 - Keep retention on RAM section S1 when RAM section is switched off
impl W<u32, Reg<u32, _POWERCLR>>
[src]
impl W<u32, Reg<u32, _POWERCLR>>
[src]pub fn s0power(&mut self) -> S0POWER_W<'_>
[src]
pub fn s0power(&mut self) -> S0POWER_W<'_>
[src]Bit 0 - Keep RAM section S0 of RAM0 on or off in System ON mode
pub fn s1power(&mut self) -> S1POWER_W<'_>
[src]
pub fn s1power(&mut self) -> S1POWER_W<'_>
[src]Bit 1 - Keep RAM section S1 of RAM0 on or off in System ON mode
pub fn s0retention(&mut self) -> S0RETENTION_W<'_>
[src]
pub fn s0retention(&mut self) -> S0RETENTION_W<'_>
[src]Bit 16 - Keep retention on RAM section S0 when RAM section is switched off
pub fn s1retention(&mut self) -> S1RETENTION_W<'_>
[src]
pub fn s1retention(&mut self) -> S1RETENTION_W<'_>
[src]Bit 17 - Keep retention on RAM section S1 when RAM section is switched off
impl W<u32, Reg<u32, _INTENSET>>
[src]
impl W<u32, Reg<u32, _INTENSET>>
[src]pub fn pofwarn(&mut self) -> POFWARN_W<'_>
[src]
pub fn pofwarn(&mut self) -> POFWARN_W<'_>
[src]Bit 2 - Write ‘1’ to Enable interrupt for POFWARN event
pub fn sleepenter(&mut self) -> SLEEPENTER_W<'_>
[src]
pub fn sleepenter(&mut self) -> SLEEPENTER_W<'_>
[src]Bit 5 - Write ‘1’ to Enable interrupt for SLEEPENTER event
pub fn sleepexit(&mut self) -> SLEEPEXIT_W<'_>
[src]
pub fn sleepexit(&mut self) -> SLEEPEXIT_W<'_>
[src]Bit 6 - Write ‘1’ to Enable interrupt for SLEEPEXIT event
impl W<u32, Reg<u32, _INTENCLR>>
[src]
impl W<u32, Reg<u32, _INTENCLR>>
[src]pub fn pofwarn(&mut self) -> POFWARN_W<'_>
[src]
pub fn pofwarn(&mut self) -> POFWARN_W<'_>
[src]Bit 2 - Write ‘1’ to Disable interrupt for POFWARN event
pub fn sleepenter(&mut self) -> SLEEPENTER_W<'_>
[src]
pub fn sleepenter(&mut self) -> SLEEPENTER_W<'_>
[src]Bit 5 - Write ‘1’ to Disable interrupt for SLEEPENTER event
pub fn sleepexit(&mut self) -> SLEEPEXIT_W<'_>
[src]
pub fn sleepexit(&mut self) -> SLEEPEXIT_W<'_>
[src]Bit 6 - Write ‘1’ to Disable interrupt for SLEEPEXIT event
impl W<u32, Reg<u32, _RESETREAS>>
[src]
impl W<u32, Reg<u32, _RESETREAS>>
[src]pub fn resetpin(&mut self) -> RESETPIN_W<'_>
[src]
pub fn resetpin(&mut self) -> RESETPIN_W<'_>
[src]Bit 0 - Reset from pin-reset detected
pub fn off(&mut self) -> OFF_W<'_>
[src]
pub fn off(&mut self) -> OFF_W<'_>
[src]Bit 16 - Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO
pub fn lpcomp(&mut self) -> LPCOMP_W<'_>
[src]
pub fn lpcomp(&mut self) -> LPCOMP_W<'_>
[src]Bit 17 - Reset due to wake up from System OFF mode when wakeup is triggered from ANADETECT signal from LPCOMP
impl W<u32, Reg<u32, _SYSTEMOFF>>
[src]
impl W<u32, Reg<u32, _SYSTEMOFF>>
[src]pub fn systemoff(&mut self) -> SYSTEMOFF_W<'_>
[src]
pub fn systemoff(&mut self) -> SYSTEMOFF_W<'_>
[src]Bit 0 - Enable System OFF mode
impl W<u32, Reg<u32, _GPREGRET>>
[src]
impl W<u32, Reg<u32, _GPREGRET>>
[src]pub fn gpregret(&mut self) -> GPREGRET_W<'_>
[src]
pub fn gpregret(&mut self) -> GPREGRET_W<'_>
[src]Bits 0:7 - General purpose retention register
impl W<u32, Reg<u32, _GPREGRET2>>
[src]
impl W<u32, Reg<u32, _GPREGRET2>>
[src]pub fn gpregret(&mut self) -> GPREGRET_W<'_>
[src]
pub fn gpregret(&mut self) -> GPREGRET_W<'_>
[src]Bits 0:7 - General purpose retention register
impl W<u32, Reg<u32, _RAMON>>
[src]
impl W<u32, Reg<u32, _RAMON>>
[src]impl W<u32, Reg<u32, _RAMONB>>
[src]
impl W<u32, Reg<u32, _RAMONB>>
[src]impl W<u32, Reg<u32, _INTENSET>>
[src]
impl W<u32, Reg<u32, _INTENSET>>
[src]pub fn hfclkstarted(&mut self) -> HFCLKSTARTED_W<'_>
[src]
pub fn hfclkstarted(&mut self) -> HFCLKSTARTED_W<'_>
[src]Bit 0 - Write ‘1’ to Enable interrupt for HFCLKSTARTED event
pub fn lfclkstarted(&mut self) -> LFCLKSTARTED_W<'_>
[src]
pub fn lfclkstarted(&mut self) -> LFCLKSTARTED_W<'_>
[src]Bit 1 - Write ‘1’ to Enable interrupt for LFCLKSTARTED event
impl W<u32, Reg<u32, _INTENCLR>>
[src]
impl W<u32, Reg<u32, _INTENCLR>>
[src]pub fn hfclkstarted(&mut self) -> HFCLKSTARTED_W<'_>
[src]
pub fn hfclkstarted(&mut self) -> HFCLKSTARTED_W<'_>
[src]Bit 0 - Write ‘1’ to Disable interrupt for HFCLKSTARTED event
pub fn lfclkstarted(&mut self) -> LFCLKSTARTED_W<'_>
[src]
pub fn lfclkstarted(&mut self) -> LFCLKSTARTED_W<'_>
[src]Bit 1 - Write ‘1’ to Disable interrupt for LFCLKSTARTED event
impl W<u32, Reg<u32, _TRACECONFIG>>
[src]
impl W<u32, Reg<u32, _TRACECONFIG>>
[src]pub fn traceportspeed(&mut self) -> TRACEPORTSPEED_W<'_>
[src]
pub fn traceportspeed(&mut self) -> TRACEPORTSPEED_W<'_>
[src]Bits 0:1 - Speed of Trace Port clock. Note that the TRACECLK pin will output this clock divided by two.
pub fn tracemux(&mut self) -> TRACEMUX_W<'_>
[src]
pub fn tracemux(&mut self) -> TRACEMUX_W<'_>
[src]Bits 16:17 - Pin multiplexing of trace signals.
impl W<u32, Reg<u32, _SHORTS>>
[src]
impl W<u32, Reg<u32, _SHORTS>>
[src]pub fn ready_start(&mut self) -> READY_START_W<'_>
[src]
pub fn ready_start(&mut self) -> READY_START_W<'_>
[src]Bit 0 - Shortcut between READY event and START task
pub fn end_disable(&mut self) -> END_DISABLE_W<'_>
[src]
pub fn end_disable(&mut self) -> END_DISABLE_W<'_>
[src]Bit 1 - Shortcut between END event and DISABLE task
pub fn disabled_txen(&mut self) -> DISABLED_TXEN_W<'_>
[src]
pub fn disabled_txen(&mut self) -> DISABLED_TXEN_W<'_>
[src]Bit 2 - Shortcut between DISABLED event and TXEN task
pub fn disabled_rxen(&mut self) -> DISABLED_RXEN_W<'_>
[src]
pub fn disabled_rxen(&mut self) -> DISABLED_RXEN_W<'_>
[src]Bit 3 - Shortcut between DISABLED event and RXEN task
pub fn address_rssistart(&mut self) -> ADDRESS_RSSISTART_W<'_>
[src]
pub fn address_rssistart(&mut self) -> ADDRESS_RSSISTART_W<'_>
[src]Bit 4 - Shortcut between ADDRESS event and RSSISTART task
pub fn end_start(&mut self) -> END_START_W<'_>
[src]
pub fn end_start(&mut self) -> END_START_W<'_>
[src]Bit 5 - Shortcut between END event and START task
pub fn address_bcstart(&mut self) -> ADDRESS_BCSTART_W<'_>
[src]
pub fn address_bcstart(&mut self) -> ADDRESS_BCSTART_W<'_>
[src]Bit 6 - Shortcut between ADDRESS event and BCSTART task
pub fn disabled_rssistop(&mut self) -> DISABLED_RSSISTOP_W<'_>
[src]
pub fn disabled_rssistop(&mut self) -> DISABLED_RSSISTOP_W<'_>
[src]Bit 8 - Shortcut between DISABLED event and RSSISTOP task
impl W<u32, Reg<u32, _INTENSET>>
[src]
impl W<u32, Reg<u32, _INTENSET>>
[src]pub fn address(&mut self) -> ADDRESS_W<'_>
[src]
pub fn address(&mut self) -> ADDRESS_W<'_>
[src]Bit 1 - Write ‘1’ to Enable interrupt for ADDRESS event
pub fn payload(&mut self) -> PAYLOAD_W<'_>
[src]
pub fn payload(&mut self) -> PAYLOAD_W<'_>
[src]Bit 2 - Write ‘1’ to Enable interrupt for PAYLOAD event
pub fn disabled(&mut self) -> DISABLED_W<'_>
[src]
pub fn disabled(&mut self) -> DISABLED_W<'_>
[src]Bit 4 - Write ‘1’ to Enable interrupt for DISABLED event
pub fn devmatch(&mut self) -> DEVMATCH_W<'_>
[src]
pub fn devmatch(&mut self) -> DEVMATCH_W<'_>
[src]Bit 5 - Write ‘1’ to Enable interrupt for DEVMATCH event
pub fn devmiss(&mut self) -> DEVMISS_W<'_>
[src]
pub fn devmiss(&mut self) -> DEVMISS_W<'_>
[src]Bit 6 - Write ‘1’ to Enable interrupt for DEVMISS event
pub fn rssiend(&mut self) -> RSSIEND_W<'_>
[src]
pub fn rssiend(&mut self) -> RSSIEND_W<'_>
[src]Bit 7 - Write ‘1’ to Enable interrupt for RSSIEND event
pub fn bcmatch(&mut self) -> BCMATCH_W<'_>
[src]
pub fn bcmatch(&mut self) -> BCMATCH_W<'_>
[src]Bit 10 - Write ‘1’ to Enable interrupt for BCMATCH event
pub fn crcerror(&mut self) -> CRCERROR_W<'_>
[src]
pub fn crcerror(&mut self) -> CRCERROR_W<'_>
[src]Bit 13 - Write ‘1’ to Enable interrupt for CRCERROR event
impl W<u32, Reg<u32, _INTENCLR>>
[src]
impl W<u32, Reg<u32, _INTENCLR>>
[src]pub fn address(&mut self) -> ADDRESS_W<'_>
[src]
pub fn address(&mut self) -> ADDRESS_W<'_>
[src]Bit 1 - Write ‘1’ to Disable interrupt for ADDRESS event
pub fn payload(&mut self) -> PAYLOAD_W<'_>
[src]
pub fn payload(&mut self) -> PAYLOAD_W<'_>
[src]Bit 2 - Write ‘1’ to Disable interrupt for PAYLOAD event
pub fn disabled(&mut self) -> DISABLED_W<'_>
[src]
pub fn disabled(&mut self) -> DISABLED_W<'_>
[src]Bit 4 - Write ‘1’ to Disable interrupt for DISABLED event
pub fn devmatch(&mut self) -> DEVMATCH_W<'_>
[src]
pub fn devmatch(&mut self) -> DEVMATCH_W<'_>
[src]Bit 5 - Write ‘1’ to Disable interrupt for DEVMATCH event
pub fn devmiss(&mut self) -> DEVMISS_W<'_>
[src]
pub fn devmiss(&mut self) -> DEVMISS_W<'_>
[src]Bit 6 - Write ‘1’ to Disable interrupt for DEVMISS event
pub fn rssiend(&mut self) -> RSSIEND_W<'_>
[src]
pub fn rssiend(&mut self) -> RSSIEND_W<'_>
[src]Bit 7 - Write ‘1’ to Disable interrupt for RSSIEND event
pub fn bcmatch(&mut self) -> BCMATCH_W<'_>
[src]
pub fn bcmatch(&mut self) -> BCMATCH_W<'_>
[src]Bit 10 - Write ‘1’ to Disable interrupt for BCMATCH event
pub fn crcerror(&mut self) -> CRCERROR_W<'_>
[src]
pub fn crcerror(&mut self) -> CRCERROR_W<'_>
[src]Bit 13 - Write ‘1’ to Disable interrupt for CRCERROR event
impl W<u32, Reg<u32, _PACKETPTR>>
[src]
impl W<u32, Reg<u32, _PACKETPTR>>
[src]pub fn packetptr(&mut self) -> PACKETPTR_W<'_>
[src]
pub fn packetptr(&mut self) -> PACKETPTR_W<'_>
[src]Bits 0:31 - Packet pointer
impl W<u32, Reg<u32, _PCNF0>>
[src]
impl W<u32, Reg<u32, _PCNF0>>
[src]impl W<u32, Reg<u32, _PCNF1>>
[src]
impl W<u32, Reg<u32, _PCNF1>>
[src]pub fn maxlen(&mut self) -> MAXLEN_W<'_>
[src]
pub fn maxlen(&mut self) -> MAXLEN_W<'_>
[src]Bits 0:7 - Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN.
impl W<u32, Reg<u32, _TXADDRESS>>
[src]
impl W<u32, Reg<u32, _TXADDRESS>>
[src]pub fn txaddress(&mut self) -> TXADDRESS_W<'_>
[src]
pub fn txaddress(&mut self) -> TXADDRESS_W<'_>
[src]Bits 0:2 - Transmit address select
impl W<u32, Reg<u32, _RXADDRESSES>>
[src]
impl W<u32, Reg<u32, _RXADDRESSES>>
[src]pub fn addr0(&mut self) -> ADDR0_W<'_>
[src]
pub fn addr0(&mut self) -> ADDR0_W<'_>
[src]Bit 0 - Enable or disable reception on logical address 0.
pub fn addr1(&mut self) -> ADDR1_W<'_>
[src]
pub fn addr1(&mut self) -> ADDR1_W<'_>
[src]Bit 1 - Enable or disable reception on logical address 1.
pub fn addr2(&mut self) -> ADDR2_W<'_>
[src]
pub fn addr2(&mut self) -> ADDR2_W<'_>
[src]Bit 2 - Enable or disable reception on logical address 2.
pub fn addr3(&mut self) -> ADDR3_W<'_>
[src]
pub fn addr3(&mut self) -> ADDR3_W<'_>
[src]Bit 3 - Enable or disable reception on logical address 3.
pub fn addr4(&mut self) -> ADDR4_W<'_>
[src]
pub fn addr4(&mut self) -> ADDR4_W<'_>
[src]Bit 4 - Enable or disable reception on logical address 4.
pub fn addr5(&mut self) -> ADDR5_W<'_>
[src]
pub fn addr5(&mut self) -> ADDR5_W<'_>
[src]Bit 5 - Enable or disable reception on logical address 5.
impl W<u32, Reg<u32, _DATAWHITEIV>>
[src]
impl W<u32, Reg<u32, _DATAWHITEIV>>
[src]pub fn datawhiteiv(&mut self) -> DATAWHITEIV_W<'_>
[src]
pub fn datawhiteiv(&mut self) -> DATAWHITEIV_W<'_>
[src]Bits 0:6 - Data whitening initial value. Bit 6 is hard-wired to ‘1’, writing ‘0’ to it has no effect, and it will always be read back and used by the device as ‘1’.
impl W<u32, Reg<u32, _DACNF>>
[src]
impl W<u32, Reg<u32, _DACNF>>
[src]pub fn ena0(&mut self) -> ENA0_W<'_>
[src]
pub fn ena0(&mut self) -> ENA0_W<'_>
[src]Bit 0 - Enable or disable device address matching using device address 0
pub fn ena1(&mut self) -> ENA1_W<'_>
[src]
pub fn ena1(&mut self) -> ENA1_W<'_>
[src]Bit 1 - Enable or disable device address matching using device address 1
pub fn ena2(&mut self) -> ENA2_W<'_>
[src]
pub fn ena2(&mut self) -> ENA2_W<'_>
[src]Bit 2 - Enable or disable device address matching using device address 2
pub fn ena3(&mut self) -> ENA3_W<'_>
[src]
pub fn ena3(&mut self) -> ENA3_W<'_>
[src]Bit 3 - Enable or disable device address matching using device address 3
pub fn ena4(&mut self) -> ENA4_W<'_>
[src]
pub fn ena4(&mut self) -> ENA4_W<'_>
[src]Bit 4 - Enable or disable device address matching using device address 4
pub fn ena5(&mut self) -> ENA5_W<'_>
[src]
pub fn ena5(&mut self) -> ENA5_W<'_>
[src]Bit 5 - Enable or disable device address matching using device address 5
pub fn ena6(&mut self) -> ENA6_W<'_>
[src]
pub fn ena6(&mut self) -> ENA6_W<'_>
[src]Bit 6 - Enable or disable device address matching using device address 6
impl W<u32, Reg<u32, _SHORTS>>
[src]
impl W<u32, Reg<u32, _SHORTS>>
[src]pub fn endrx_startrx(&mut self) -> ENDRX_STARTRX_W<'_>
[src]
pub fn endrx_startrx(&mut self) -> ENDRX_STARTRX_W<'_>
[src]Bit 5 - Shortcut between ENDRX event and STARTRX task
pub fn endrx_stoprx(&mut self) -> ENDRX_STOPRX_W<'_>
[src]
pub fn endrx_stoprx(&mut self) -> ENDRX_STOPRX_W<'_>
[src]Bit 6 - Shortcut between ENDRX event and STOPRX task
impl W<u32, Reg<u32, _INTEN>>
[src]
impl W<u32, Reg<u32, _INTEN>>
[src]pub fn rxstarted(&mut self) -> RXSTARTED_W<'_>
[src]
pub fn rxstarted(&mut self) -> RXSTARTED_W<'_>
[src]Bit 19 - Enable or disable interrupt for RXSTARTED event
pub fn txstarted(&mut self) -> TXSTARTED_W<'_>
[src]
pub fn txstarted(&mut self) -> TXSTARTED_W<'_>
[src]Bit 20 - Enable or disable interrupt for TXSTARTED event
pub fn txstopped(&mut self) -> TXSTOPPED_W<'_>
[src]
pub fn txstopped(&mut self) -> TXSTOPPED_W<'_>
[src]Bit 22 - Enable or disable interrupt for TXSTOPPED event
impl W<u32, Reg<u32, _INTENSET>>
[src]
impl W<u32, Reg<u32, _INTENSET>>
[src]pub fn rxstarted(&mut self) -> RXSTARTED_W<'_>
[src]
pub fn rxstarted(&mut self) -> RXSTARTED_W<'_>
[src]Bit 19 - Write ‘1’ to Enable interrupt for RXSTARTED event
pub fn txstarted(&mut self) -> TXSTARTED_W<'_>
[src]
pub fn txstarted(&mut self) -> TXSTARTED_W<'_>
[src]Bit 20 - Write ‘1’ to Enable interrupt for TXSTARTED event
pub fn txstopped(&mut self) -> TXSTOPPED_W<'_>
[src]
pub fn txstopped(&mut self) -> TXSTOPPED_W<'_>
[src]Bit 22 - Write ‘1’ to Enable interrupt for TXSTOPPED event
impl W<u32, Reg<u32, _INTENCLR>>
[src]
impl W<u32, Reg<u32, _INTENCLR>>
[src]pub fn rxdrdy(&mut self) -> RXDRDY_W<'_>
[src]
pub fn rxdrdy(&mut self) -> RXDRDY_W<'_>
[src]Bit 2 - Write ‘1’ to Disable interrupt for RXDRDY event
pub fn txdrdy(&mut self) -> TXDRDY_W<'_>
[src]
pub fn txdrdy(&mut self) -> TXDRDY_W<'_>
[src]Bit 7 - Write ‘1’ to Disable interrupt for TXDRDY event
pub fn rxstarted(&mut self) -> RXSTARTED_W<'_>
[src]
pub fn rxstarted(&mut self) -> RXSTARTED_W<'_>
[src]Bit 19 - Write ‘1’ to Disable interrupt for RXSTARTED event
pub fn txstarted(&mut self) -> TXSTARTED_W<'_>
[src]
pub fn txstarted(&mut self) -> TXSTARTED_W<'_>
[src]Bit 20 - Write ‘1’ to Disable interrupt for TXSTARTED event
pub fn txstopped(&mut self) -> TXSTOPPED_W<'_>
[src]
pub fn txstopped(&mut self) -> TXSTOPPED_W<'_>
[src]Bit 22 - Write ‘1’ to Disable interrupt for TXSTOPPED event
impl W<u32, Reg<u32, _BAUDRATE>>
[src]
impl W<u32, Reg<u32, _BAUDRATE>>
[src]pub fn baudrate(&mut self) -> BAUDRATE_W<'_>
[src]
pub fn baudrate(&mut self) -> BAUDRATE_W<'_>
[src]Bits 0:31 - Baud rate
impl W<u32, Reg<u32, _SHORTS>>
[src]
impl W<u32, Reg<u32, _SHORTS>>
[src]pub fn cts_startrx(&mut self) -> CTS_STARTRX_W<'_>
[src]
pub fn cts_startrx(&mut self) -> CTS_STARTRX_W<'_>
[src]Bit 3 - Shortcut between CTS event and STARTRX task
pub fn ncts_stoprx(&mut self) -> NCTS_STOPRX_W<'_>
[src]
pub fn ncts_stoprx(&mut self) -> NCTS_STOPRX_W<'_>
[src]Bit 4 - Shortcut between NCTS event and STOPRX task
impl W<u32, Reg<u32, _INTENCLR>>
[src]
impl W<u32, Reg<u32, _INTENCLR>>
[src]impl W<u32, Reg<u32, _BAUDRATE>>
[src]
impl W<u32, Reg<u32, _BAUDRATE>>
[src]pub fn baudrate(&mut self) -> BAUDRATE_W<'_>
[src]
pub fn baudrate(&mut self) -> BAUDRATE_W<'_>
[src]Bits 0:31 - Baud rate
impl W<u32, Reg<u32, _SHORTS>>
[src]
impl W<u32, Reg<u32, _SHORTS>>
[src]pub fn end_start(&mut self) -> END_START_W<'_>
[src]
pub fn end_start(&mut self) -> END_START_W<'_>
[src]Bit 17 - Shortcut between END event and START task
impl W<u32, Reg<u32, _INTENSET>>
[src]
impl W<u32, Reg<u32, _INTENSET>>
[src]impl W<u32, Reg<u32, _INTENCLR>>
[src]
impl W<u32, Reg<u32, _INTENCLR>>
[src]impl W<u32, Reg<u32, _FREQUENCY>>
[src]
impl W<u32, Reg<u32, _FREQUENCY>>
[src]pub fn frequency(&mut self) -> FREQUENCY_W<'_>
[src]
pub fn frequency(&mut self) -> FREQUENCY_W<'_>
[src]Bits 0:31 - SPI master data rate
impl W<u32, Reg<u32, _SHORTS>>
[src]
impl W<u32, Reg<u32, _SHORTS>>
[src]pub fn end_acquire(&mut self) -> END_ACQUIRE_W<'_>
[src]
pub fn end_acquire(&mut self) -> END_ACQUIRE_W<'_>
[src]Bit 2 - Shortcut between END event and ACQUIRE task
impl W<u32, Reg<u32, _STATUS>>
[src]
impl W<u32, Reg<u32, _STATUS>>
[src]pub fn overread(&mut self) -> OVERREAD_W<'_>
[src]
pub fn overread(&mut self) -> OVERREAD_W<'_>
[src]Bit 0 - TX buffer over-read detected, and prevented
pub fn overflow(&mut self) -> OVERFLOW_W<'_>
[src]
pub fn overflow(&mut self) -> OVERFLOW_W<'_>
[src]Bit 1 - RX buffer overflow detected, and prevented
impl W<u32, Reg<u32, _SHORTS>>
[src]
impl W<u32, Reg<u32, _SHORTS>>
[src]pub fn lasttx_startrx(&mut self) -> LASTTX_STARTRX_W<'_>
[src]
pub fn lasttx_startrx(&mut self) -> LASTTX_STARTRX_W<'_>
[src]Bit 7 - Shortcut between LASTTX event and STARTRX task
pub fn lasttx_suspend(&mut self) -> LASTTX_SUSPEND_W<'_>
[src]
pub fn lasttx_suspend(&mut self) -> LASTTX_SUSPEND_W<'_>
[src]Bit 8 - Shortcut between LASTTX event and SUSPEND task
pub fn lasttx_stop(&mut self) -> LASTTX_STOP_W<'_>
[src]
pub fn lasttx_stop(&mut self) -> LASTTX_STOP_W<'_>
[src]Bit 9 - Shortcut between LASTTX event and STOP task
pub fn lastrx_starttx(&mut self) -> LASTRX_STARTTX_W<'_>
[src]
pub fn lastrx_starttx(&mut self) -> LASTRX_STARTTX_W<'_>
[src]Bit 10 - Shortcut between LASTRX event and STARTTX task
pub fn lastrx_stop(&mut self) -> LASTRX_STOP_W<'_>
[src]
pub fn lastrx_stop(&mut self) -> LASTRX_STOP_W<'_>
[src]Bit 12 - Shortcut between LASTRX event and STOP task
impl W<u32, Reg<u32, _INTEN>>
[src]
impl W<u32, Reg<u32, _INTEN>>
[src]pub fn stopped(&mut self) -> STOPPED_W<'_>
[src]
pub fn stopped(&mut self) -> STOPPED_W<'_>
[src]Bit 1 - Enable or disable interrupt for STOPPED event
pub fn suspended(&mut self) -> SUSPENDED_W<'_>
[src]
pub fn suspended(&mut self) -> SUSPENDED_W<'_>
[src]Bit 18 - Enable or disable interrupt for SUSPENDED event
pub fn rxstarted(&mut self) -> RXSTARTED_W<'_>
[src]
pub fn rxstarted(&mut self) -> RXSTARTED_W<'_>
[src]Bit 19 - Enable or disable interrupt for RXSTARTED event
pub fn txstarted(&mut self) -> TXSTARTED_W<'_>
[src]
pub fn txstarted(&mut self) -> TXSTARTED_W<'_>
[src]Bit 20 - Enable or disable interrupt for TXSTARTED event
impl W<u32, Reg<u32, _INTENSET>>
[src]
impl W<u32, Reg<u32, _INTENSET>>
[src]pub fn stopped(&mut self) -> STOPPED_W<'_>
[src]
pub fn stopped(&mut self) -> STOPPED_W<'_>
[src]Bit 1 - Write ‘1’ to Enable interrupt for STOPPED event
pub fn suspended(&mut self) -> SUSPENDED_W<'_>
[src]
pub fn suspended(&mut self) -> SUSPENDED_W<'_>
[src]Bit 18 - Write ‘1’ to Enable interrupt for SUSPENDED event
pub fn rxstarted(&mut self) -> RXSTARTED_W<'_>
[src]
pub fn rxstarted(&mut self) -> RXSTARTED_W<'_>
[src]Bit 19 - Write ‘1’ to Enable interrupt for RXSTARTED event
pub fn txstarted(&mut self) -> TXSTARTED_W<'_>
[src]
pub fn txstarted(&mut self) -> TXSTARTED_W<'_>
[src]Bit 20 - Write ‘1’ to Enable interrupt for TXSTARTED event
impl W<u32, Reg<u32, _INTENCLR>>
[src]
impl W<u32, Reg<u32, _INTENCLR>>
[src]pub fn stopped(&mut self) -> STOPPED_W<'_>
[src]
pub fn stopped(&mut self) -> STOPPED_W<'_>
[src]Bit 1 - Write ‘1’ to Disable interrupt for STOPPED event
pub fn suspended(&mut self) -> SUSPENDED_W<'_>
[src]
pub fn suspended(&mut self) -> SUSPENDED_W<'_>
[src]Bit 18 - Write ‘1’ to Disable interrupt for SUSPENDED event
pub fn rxstarted(&mut self) -> RXSTARTED_W<'_>
[src]
pub fn rxstarted(&mut self) -> RXSTARTED_W<'_>
[src]Bit 19 - Write ‘1’ to Disable interrupt for RXSTARTED event
pub fn txstarted(&mut self) -> TXSTARTED_W<'_>
[src]
pub fn txstarted(&mut self) -> TXSTARTED_W<'_>
[src]Bit 20 - Write ‘1’ to Disable interrupt for TXSTARTED event
impl W<u32, Reg<u32, _FREQUENCY>>
[src]
impl W<u32, Reg<u32, _FREQUENCY>>
[src]pub fn frequency(&mut self) -> FREQUENCY_W<'_>
[src]
pub fn frequency(&mut self) -> FREQUENCY_W<'_>
[src]Bits 0:31 - TWI master clock frequency
impl W<u32, Reg<u32, _SHORTS>>
[src]
impl W<u32, Reg<u32, _SHORTS>>
[src]pub fn write_suspend(&mut self) -> WRITE_SUSPEND_W<'_>
[src]
pub fn write_suspend(&mut self) -> WRITE_SUSPEND_W<'_>
[src]Bit 13 - Shortcut between WRITE event and SUSPEND task
pub fn read_suspend(&mut self) -> READ_SUSPEND_W<'_>
[src]
pub fn read_suspend(&mut self) -> READ_SUSPEND_W<'_>
[src]Bit 14 - Shortcut between READ event and SUSPEND task
impl W<u32, Reg<u32, _INTEN>>
[src]
impl W<u32, Reg<u32, _INTEN>>
[src]pub fn stopped(&mut self) -> STOPPED_W<'_>
[src]
pub fn stopped(&mut self) -> STOPPED_W<'_>
[src]Bit 1 - Enable or disable interrupt for STOPPED event
pub fn rxstarted(&mut self) -> RXSTARTED_W<'_>
[src]
pub fn rxstarted(&mut self) -> RXSTARTED_W<'_>
[src]Bit 19 - Enable or disable interrupt for RXSTARTED event
pub fn txstarted(&mut self) -> TXSTARTED_W<'_>
[src]
pub fn txstarted(&mut self) -> TXSTARTED_W<'_>
[src]Bit 20 - Enable or disable interrupt for TXSTARTED event
impl W<u32, Reg<u32, _INTENSET>>
[src]
impl W<u32, Reg<u32, _INTENSET>>
[src]pub fn stopped(&mut self) -> STOPPED_W<'_>
[src]
pub fn stopped(&mut self) -> STOPPED_W<'_>
[src]Bit 1 - Write ‘1’ to Enable interrupt for STOPPED event
pub fn rxstarted(&mut self) -> RXSTARTED_W<'_>
[src]
pub fn rxstarted(&mut self) -> RXSTARTED_W<'_>
[src]Bit 19 - Write ‘1’ to Enable interrupt for RXSTARTED event
pub fn txstarted(&mut self) -> TXSTARTED_W<'_>
[src]
pub fn txstarted(&mut self) -> TXSTARTED_W<'_>
[src]Bit 20 - Write ‘1’ to Enable interrupt for TXSTARTED event
impl W<u32, Reg<u32, _INTENCLR>>
[src]
impl W<u32, Reg<u32, _INTENCLR>>
[src]pub fn stopped(&mut self) -> STOPPED_W<'_>
[src]
pub fn stopped(&mut self) -> STOPPED_W<'_>
[src]Bit 1 - Write ‘1’ to Disable interrupt for STOPPED event
pub fn rxstarted(&mut self) -> RXSTARTED_W<'_>
[src]
pub fn rxstarted(&mut self) -> RXSTARTED_W<'_>
[src]Bit 19 - Write ‘1’ to Disable interrupt for RXSTARTED event
pub fn txstarted(&mut self) -> TXSTARTED_W<'_>
[src]
pub fn txstarted(&mut self) -> TXSTARTED_W<'_>
[src]Bit 20 - Write ‘1’ to Disable interrupt for TXSTARTED event
impl W<u32, Reg<u32, _ERRORSRC>>
[src]
impl W<u32, Reg<u32, _ERRORSRC>>
[src]pub fn overflow(&mut self) -> OVERFLOW_W<'_>
[src]
pub fn overflow(&mut self) -> OVERFLOW_W<'_>
[src]Bit 0 - RX buffer overflow detected, and prevented
pub fn overread(&mut self) -> OVERREAD_W<'_>
[src]
pub fn overread(&mut self) -> OVERREAD_W<'_>
[src]Bit 3 - TX buffer over-read detected, and prevented
impl W<u32, Reg<u32, _CONFIG>>
[src]
impl W<u32, Reg<u32, _CONFIG>>
[src]pub fn address0(&mut self) -> ADDRESS0_W<'_>
[src]
pub fn address0(&mut self) -> ADDRESS0_W<'_>
[src]Bit 0 - Enable or disable address matching on ADDRESS[0]
pub fn address1(&mut self) -> ADDRESS1_W<'_>
[src]
pub fn address1(&mut self) -> ADDRESS1_W<'_>
[src]Bit 1 - Enable or disable address matching on ADDRESS[1]
impl W<u32, Reg<u32, _MOSI>>
[src]
impl W<u32, Reg<u32, _MOSI>>
[src]pub fn pselmosi(&mut self) -> PSELMOSI_W<'_>
[src]
pub fn pselmosi(&mut self) -> PSELMOSI_W<'_>
[src]Bits 0:31 - Pin number configuration for SPI MOSI signal
impl W<u32, Reg<u32, _MISO>>
[src]
impl W<u32, Reg<u32, _MISO>>
[src]pub fn pselmiso(&mut self) -> PSELMISO_W<'_>
[src]
pub fn pselmiso(&mut self) -> PSELMISO_W<'_>
[src]Bits 0:31 - Pin number configuration for SPI MISO signal
impl W<u32, Reg<u32, _FREQUENCY>>
[src]
impl W<u32, Reg<u32, _FREQUENCY>>
[src]pub fn frequency(&mut self) -> FREQUENCY_W<'_>
[src]
pub fn frequency(&mut self) -> FREQUENCY_W<'_>
[src]Bits 0:31 - SPI master data rate
impl W<u32, Reg<u32, _SHORTS>>
[src]
impl W<u32, Reg<u32, _SHORTS>>
[src]pub fn bb_suspend(&mut self) -> BB_SUSPEND_W<'_>
[src]
pub fn bb_suspend(&mut self) -> BB_SUSPEND_W<'_>
[src]Bit 0 - Shortcut between BB event and SUSPEND task
impl W<u32, Reg<u32, _INTENSET>>
[src]
impl W<u32, Reg<u32, _INTENSET>>
[src]pub fn stopped(&mut self) -> STOPPED_W<'_>
[src]
pub fn stopped(&mut self) -> STOPPED_W<'_>
[src]Bit 1 - Write ‘1’ to Enable interrupt for STOPPED event
pub fn rxdready(&mut self) -> RXDREADY_W<'_>
[src]
pub fn rxdready(&mut self) -> RXDREADY_W<'_>
[src]Bit 2 - Write ‘1’ to Enable interrupt for RXDREADY event
pub fn txdsent(&mut self) -> TXDSENT_W<'_>
[src]
pub fn txdsent(&mut self) -> TXDSENT_W<'_>
[src]Bit 7 - Write ‘1’ to Enable interrupt for TXDSENT event
pub fn suspended(&mut self) -> SUSPENDED_W<'_>
[src]
pub fn suspended(&mut self) -> SUSPENDED_W<'_>
[src]Bit 18 - Write ‘1’ to Enable interrupt for SUSPENDED event
impl W<u32, Reg<u32, _INTENCLR>>
[src]
impl W<u32, Reg<u32, _INTENCLR>>
[src]pub fn stopped(&mut self) -> STOPPED_W<'_>
[src]
pub fn stopped(&mut self) -> STOPPED_W<'_>
[src]Bit 1 - Write ‘1’ to Disable interrupt for STOPPED event
pub fn rxdready(&mut self) -> RXDREADY_W<'_>
[src]
pub fn rxdready(&mut self) -> RXDREADY_W<'_>
[src]Bit 2 - Write ‘1’ to Disable interrupt for RXDREADY event
pub fn txdsent(&mut self) -> TXDSENT_W<'_>
[src]
pub fn txdsent(&mut self) -> TXDSENT_W<'_>
[src]Bit 7 - Write ‘1’ to Disable interrupt for TXDSENT event
pub fn suspended(&mut self) -> SUSPENDED_W<'_>
[src]
pub fn suspended(&mut self) -> SUSPENDED_W<'_>
[src]Bit 18 - Write ‘1’ to Disable interrupt for SUSPENDED event
impl W<u32, Reg<u32, _FREQUENCY>>
[src]
impl W<u32, Reg<u32, _FREQUENCY>>
[src]pub fn frequency(&mut self) -> FREQUENCY_W<'_>
[src]
pub fn frequency(&mut self) -> FREQUENCY_W<'_>
[src]Bits 0:31 - TWI master clock frequency
impl W<u32, Reg<u32, _RX>>
[src]
impl W<u32, Reg<u32, _RX>>
[src]pub fn crcerror(&mut self) -> CRCERROR_W<'_>
[src]
pub fn crcerror(&mut self) -> CRCERROR_W<'_>
[src]Bit 0 - No valid End of Frame detected
pub fn paritystatus(&mut self) -> PARITYSTATUS_W<'_>
[src]
pub fn paritystatus(&mut self) -> PARITYSTATUS_W<'_>
[src]Bit 2 - Parity status of received frame
impl W<u32, Reg<u32, _FRAMECONFIG>>
[src]
impl W<u32, Reg<u32, _FRAMECONFIG>>
[src]pub fn discardmode(&mut self) -> DISCARDMODE_W<'_>
[src]
pub fn discardmode(&mut self) -> DISCARDMODE_W<'_>
[src]Bit 1 - Discarding unused bits in start or at end of a Frame
pub fn crcmodetx(&mut self) -> CRCMODETX_W<'_>
[src]
pub fn crcmodetx(&mut self) -> CRCMODETX_W<'_>
[src]Bit 4 - CRC mode for outgoing frames
impl W<u32, Reg<u32, _AMOUNT>>
[src]
impl W<u32, Reg<u32, _AMOUNT>>
[src]pub fn txdatabits(&mut self) -> TXDATABITS_W<'_>
[src]
pub fn txdatabits(&mut self) -> TXDATABITS_W<'_>
[src]Bits 0:2 - Number of bits in the last or first byte read from RAM that shall be included in the frame (excluding parity bit).
pub fn txdatabytes(&mut self) -> TXDATABYTES_W<'_>
[src]
pub fn txdatabytes(&mut self) -> TXDATABYTES_W<'_>
[src]Bits 3:11 - Number of complete bytes that shall be included in the frame, excluding CRC, parity and framing
impl W<u32, Reg<u32, _SHORTS>>
[src]
impl W<u32, Reg<u32, _SHORTS>>
[src]pub fn fielddetected_activate(&mut self) -> FIELDDETECTED_ACTIVATE_W<'_>
[src]
pub fn fielddetected_activate(&mut self) -> FIELDDETECTED_ACTIVATE_W<'_>
[src]Bit 0 - Shortcut between FIELDDETECTED event and ACTIVATE task
pub fn fieldlost_sense(&mut self) -> FIELDLOST_SENSE_W<'_>
[src]
pub fn fieldlost_sense(&mut self) -> FIELDLOST_SENSE_W<'_>
[src]Bit 1 - Shortcut between FIELDLOST event and SENSE task
impl W<u32, Reg<u32, _INTEN>>
[src]
impl W<u32, Reg<u32, _INTEN>>
[src]pub fn fielddetected(&mut self) -> FIELDDETECTED_W<'_>
[src]
pub fn fielddetected(&mut self) -> FIELDDETECTED_W<'_>
[src]Bit 1 - Enable or disable interrupt for FIELDDETECTED event
pub fn fieldlost(&mut self) -> FIELDLOST_W<'_>
[src]
pub fn fieldlost(&mut self) -> FIELDLOST_W<'_>
[src]Bit 2 - Enable or disable interrupt for FIELDLOST event
pub fn txframestart(&mut self) -> TXFRAMESTART_W<'_>
[src]
pub fn txframestart(&mut self) -> TXFRAMESTART_W<'_>
[src]Bit 3 - Enable or disable interrupt for TXFRAMESTART event
pub fn txframeend(&mut self) -> TXFRAMEEND_W<'_>
[src]
pub fn txframeend(&mut self) -> TXFRAMEEND_W<'_>
[src]Bit 4 - Enable or disable interrupt for TXFRAMEEND event
pub fn rxframestart(&mut self) -> RXFRAMESTART_W<'_>
[src]
pub fn rxframestart(&mut self) -> RXFRAMESTART_W<'_>
[src]Bit 5 - Enable or disable interrupt for RXFRAMESTART event
pub fn rxframeend(&mut self) -> RXFRAMEEND_W<'_>
[src]
pub fn rxframeend(&mut self) -> RXFRAMEEND_W<'_>
[src]Bit 6 - Enable or disable interrupt for RXFRAMEEND event
pub fn rxerror(&mut self) -> RXERROR_W<'_>
[src]
pub fn rxerror(&mut self) -> RXERROR_W<'_>
[src]Bit 10 - Enable or disable interrupt for RXERROR event
pub fn autocolresstarted(&mut self) -> AUTOCOLRESSTARTED_W<'_>
[src]
pub fn autocolresstarted(&mut self) -> AUTOCOLRESSTARTED_W<'_>
[src]Bit 14 - Enable or disable interrupt for AUTOCOLRESSTARTED event
pub fn collision(&mut self) -> COLLISION_W<'_>
[src]
pub fn collision(&mut self) -> COLLISION_W<'_>
[src]Bit 18 - Enable or disable interrupt for COLLISION event
pub fn selected(&mut self) -> SELECTED_W<'_>
[src]
pub fn selected(&mut self) -> SELECTED_W<'_>
[src]Bit 19 - Enable or disable interrupt for SELECTED event
impl W<u32, Reg<u32, _INTENSET>>
[src]
impl W<u32, Reg<u32, _INTENSET>>
[src]pub fn fielddetected(&mut self) -> FIELDDETECTED_W<'_>
[src]
pub fn fielddetected(&mut self) -> FIELDDETECTED_W<'_>
[src]Bit 1 - Write ‘1’ to Enable interrupt for FIELDDETECTED event
pub fn fieldlost(&mut self) -> FIELDLOST_W<'_>
[src]
pub fn fieldlost(&mut self) -> FIELDLOST_W<'_>
[src]Bit 2 - Write ‘1’ to Enable interrupt for FIELDLOST event
pub fn txframestart(&mut self) -> TXFRAMESTART_W<'_>
[src]
pub fn txframestart(&mut self) -> TXFRAMESTART_W<'_>
[src]Bit 3 - Write ‘1’ to Enable interrupt for TXFRAMESTART event
pub fn txframeend(&mut self) -> TXFRAMEEND_W<'_>
[src]
pub fn txframeend(&mut self) -> TXFRAMEEND_W<'_>
[src]Bit 4 - Write ‘1’ to Enable interrupt for TXFRAMEEND event
pub fn rxframestart(&mut self) -> RXFRAMESTART_W<'_>
[src]
pub fn rxframestart(&mut self) -> RXFRAMESTART_W<'_>
[src]Bit 5 - Write ‘1’ to Enable interrupt for RXFRAMESTART event
pub fn rxframeend(&mut self) -> RXFRAMEEND_W<'_>
[src]
pub fn rxframeend(&mut self) -> RXFRAMEEND_W<'_>
[src]Bit 6 - Write ‘1’ to Enable interrupt for RXFRAMEEND event
pub fn rxerror(&mut self) -> RXERROR_W<'_>
[src]
pub fn rxerror(&mut self) -> RXERROR_W<'_>
[src]Bit 10 - Write ‘1’ to Enable interrupt for RXERROR event
pub fn autocolresstarted(&mut self) -> AUTOCOLRESSTARTED_W<'_>
[src]
pub fn autocolresstarted(&mut self) -> AUTOCOLRESSTARTED_W<'_>
[src]Bit 14 - Write ‘1’ to Enable interrupt for AUTOCOLRESSTARTED event
pub fn collision(&mut self) -> COLLISION_W<'_>
[src]
pub fn collision(&mut self) -> COLLISION_W<'_>
[src]Bit 18 - Write ‘1’ to Enable interrupt for COLLISION event
pub fn selected(&mut self) -> SELECTED_W<'_>
[src]
pub fn selected(&mut self) -> SELECTED_W<'_>
[src]Bit 19 - Write ‘1’ to Enable interrupt for SELECTED event
impl W<u32, Reg<u32, _INTENCLR>>
[src]
impl W<u32, Reg<u32, _INTENCLR>>
[src]pub fn fielddetected(&mut self) -> FIELDDETECTED_W<'_>
[src]
pub fn fielddetected(&mut self) -> FIELDDETECTED_W<'_>
[src]Bit 1 - Write ‘1’ to Disable interrupt for FIELDDETECTED event
pub fn fieldlost(&mut self) -> FIELDLOST_W<'_>
[src]
pub fn fieldlost(&mut self) -> FIELDLOST_W<'_>
[src]Bit 2 - Write ‘1’ to Disable interrupt for FIELDLOST event
pub fn txframestart(&mut self) -> TXFRAMESTART_W<'_>
[src]
pub fn txframestart(&mut self) -> TXFRAMESTART_W<'_>
[src]Bit 3 - Write ‘1’ to Disable interrupt for TXFRAMESTART event
pub fn txframeend(&mut self) -> TXFRAMEEND_W<'_>
[src]
pub fn txframeend(&mut self) -> TXFRAMEEND_W<'_>
[src]Bit 4 - Write ‘1’ to Disable interrupt for TXFRAMEEND event
pub fn rxframestart(&mut self) -> RXFRAMESTART_W<'_>
[src]
pub fn rxframestart(&mut self) -> RXFRAMESTART_W<'_>
[src]Bit 5 - Write ‘1’ to Disable interrupt for RXFRAMESTART event
pub fn rxframeend(&mut self) -> RXFRAMEEND_W<'_>
[src]
pub fn rxframeend(&mut self) -> RXFRAMEEND_W<'_>
[src]Bit 6 - Write ‘1’ to Disable interrupt for RXFRAMEEND event
pub fn rxerror(&mut self) -> RXERROR_W<'_>
[src]
pub fn rxerror(&mut self) -> RXERROR_W<'_>
[src]Bit 10 - Write ‘1’ to Disable interrupt for RXERROR event
pub fn autocolresstarted(&mut self) -> AUTOCOLRESSTARTED_W<'_>
[src]
pub fn autocolresstarted(&mut self) -> AUTOCOLRESSTARTED_W<'_>
[src]Bit 14 - Write ‘1’ to Disable interrupt for AUTOCOLRESSTARTED event
pub fn collision(&mut self) -> COLLISION_W<'_>
[src]
pub fn collision(&mut self) -> COLLISION_W<'_>
[src]Bit 18 - Write ‘1’ to Disable interrupt for COLLISION event
pub fn selected(&mut self) -> SELECTED_W<'_>
[src]
pub fn selected(&mut self) -> SELECTED_W<'_>
[src]Bit 19 - Write ‘1’ to Disable interrupt for SELECTED event
impl W<u32, Reg<u32, _ERRORSTATUS>>
[src]
impl W<u32, Reg<u32, _ERRORSTATUS>>
[src]pub fn framedelaytimeout(&mut self) -> FRAMEDELAYTIMEOUT_W<'_>
[src]
pub fn framedelaytimeout(&mut self) -> FRAMEDELAYTIMEOUT_W<'_>
[src]Bit 0 - No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX
pub fn nfcfieldtoostrong(&mut self) -> NFCFIELDTOOSTRONG_W<'_>
[src]
pub fn nfcfieldtoostrong(&mut self) -> NFCFIELDTOOSTRONG_W<'_>
[src]Bit 2 - Field level is too high at max load resistance
pub fn nfcfieldtooweak(&mut self) -> NFCFIELDTOOWEAK_W<'_>
[src]
pub fn nfcfieldtooweak(&mut self) -> NFCFIELDTOOWEAK_W<'_>
[src]Bit 3 - Field level is too low at min load resistance
impl W<u32, Reg<u32, _FRAMEDELAYMIN>>
[src]
impl W<u32, Reg<u32, _FRAMEDELAYMIN>>
[src]pub fn framedelaymin(&mut self) -> FRAMEDELAYMIN_W<'_>
[src]
pub fn framedelaymin(&mut self) -> FRAMEDELAYMIN_W<'_>
[src]Bits 0:15 - Minimum frame delay in number of 13.56 MHz clocks
impl W<u32, Reg<u32, _FRAMEDELAYMAX>>
[src]
impl W<u32, Reg<u32, _FRAMEDELAYMAX>>
[src]pub fn framedelaymax(&mut self) -> FRAMEDELAYMAX_W<'_>
[src]
pub fn framedelaymax(&mut self) -> FRAMEDELAYMAX_W<'_>
[src]Bits 0:15 - Maximum frame delay in number of 13.56 MHz clocks
impl W<u32, Reg<u32, _FRAMEDELAYMODE>>
[src]
impl W<u32, Reg<u32, _FRAMEDELAYMODE>>
[src]pub fn framedelaymode(&mut self) -> FRAMEDELAYMODE_W<'_>
[src]
pub fn framedelaymode(&mut self) -> FRAMEDELAYMODE_W<'_>
[src]Bits 0:1 - Configuration register for the Frame Delay Timer
impl W<u32, Reg<u32, _NFCID1_LAST>>
[src]
impl W<u32, Reg<u32, _NFCID1_LAST>>
[src]pub fn nfcid1_z(&mut self) -> NFCID1_Z_W<'_>
[src]
pub fn nfcid1_z(&mut self) -> NFCID1_Z_W<'_>
[src]Bits 0:7 - NFCID1 byte Z (very last byte sent)
pub fn nfcid1_y(&mut self) -> NFCID1_Y_W<'_>
[src]
pub fn nfcid1_y(&mut self) -> NFCID1_Y_W<'_>
[src]Bits 8:15 - NFCID1 byte Y
pub fn nfcid1_x(&mut self) -> NFCID1_X_W<'_>
[src]
pub fn nfcid1_x(&mut self) -> NFCID1_X_W<'_>
[src]Bits 16:23 - NFCID1 byte X
pub fn nfcid1_w(&mut self) -> NFCID1_W_W<'_>
[src]
pub fn nfcid1_w(&mut self) -> NFCID1_W_W<'_>
[src]Bits 24:31 - NFCID1 byte W
impl W<u32, Reg<u32, _NFCID1_2ND_LAST>>
[src]
impl W<u32, Reg<u32, _NFCID1_2ND_LAST>>
[src]pub fn nfcid1_v(&mut self) -> NFCID1_V_W<'_>
[src]
pub fn nfcid1_v(&mut self) -> NFCID1_V_W<'_>
[src]Bits 0:7 - NFCID1 byte V
pub fn nfcid1_u(&mut self) -> NFCID1_U_W<'_>
[src]
pub fn nfcid1_u(&mut self) -> NFCID1_U_W<'_>
[src]Bits 8:15 - NFCID1 byte U
pub fn nfcid1_t(&mut self) -> NFCID1_T_W<'_>
[src]
pub fn nfcid1_t(&mut self) -> NFCID1_T_W<'_>
[src]Bits 16:23 - NFCID1 byte T
impl W<u32, Reg<u32, _NFCID1_3RD_LAST>>
[src]
impl W<u32, Reg<u32, _NFCID1_3RD_LAST>>
[src]pub fn nfcid1_s(&mut self) -> NFCID1_S_W<'_>
[src]
pub fn nfcid1_s(&mut self) -> NFCID1_S_W<'_>
[src]Bits 0:7 - NFCID1 byte S
pub fn nfcid1_r(&mut self) -> NFCID1_R_W<'_>
[src]
pub fn nfcid1_r(&mut self) -> NFCID1_R_W<'_>
[src]Bits 8:15 - NFCID1 byte R
pub fn nfcid1_q(&mut self) -> NFCID1_Q_W<'_>
[src]
pub fn nfcid1_q(&mut self) -> NFCID1_Q_W<'_>
[src]Bits 16:23 - NFCID1 byte Q
impl W<u32, Reg<u32, _SENSRES>>
[src]
impl W<u32, Reg<u32, _SENSRES>>
[src]pub fn bitframesdd(&mut self) -> BITFRAMESDD_W<'_>
[src]
pub fn bitframesdd(&mut self) -> BITFRAMESDD_W<'_>
[src]Bits 0:4 - Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification
pub fn nfcidsize(&mut self) -> NFCIDSIZE_W<'_>
[src]
pub fn nfcidsize(&mut self) -> NFCIDSIZE_W<'_>
[src]Bits 6:7 - NFCID1 size. This value is used by the Auto collision resolution engine.
pub fn platfconfig(&mut self) -> PLATFCONFIG_W<'_>
[src]
pub fn platfconfig(&mut self) -> PLATFCONFIG_W<'_>
[src]Bits 8:11 - Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification
impl W<u32, Reg<u32, _SELRES>>
[src]
impl W<u32, Reg<u32, _SELRES>>
[src]impl W<u32, Reg<u32, _CONFIG>>
[src]
impl W<u32, Reg<u32, _CONFIG>>
[src]pub fn psel(&mut self) -> PSEL_W<'_>
[src]
pub fn psel(&mut self) -> PSEL_W<'_>
[src]Bits 8:12 - GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event
pub fn polarity(&mut self) -> POLARITY_W<'_>
[src]
pub fn polarity(&mut self) -> POLARITY_W<'_>
[src]Bits 16:17 - When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event.
impl W<u32, Reg<u32, _CONFIG>>
[src]
impl W<u32, Reg<u32, _CONFIG>>
[src]impl W<u32, Reg<u32, _INTEN>>
[src]
impl W<u32, Reg<u32, _INTEN>>
[src]pub fn started(&mut self) -> STARTED_W<'_>
[src]
pub fn started(&mut self) -> STARTED_W<'_>
[src]Bit 0 - Enable or disable interrupt for STARTED event
pub fn resultdone(&mut self) -> RESULTDONE_W<'_>
[src]
pub fn resultdone(&mut self) -> RESULTDONE_W<'_>
[src]Bit 3 - Enable or disable interrupt for RESULTDONE event
pub fn calibratedone(&mut self) -> CALIBRATEDONE_W<'_>
[src]
pub fn calibratedone(&mut self) -> CALIBRATEDONE_W<'_>
[src]Bit 4 - Enable or disable interrupt for CALIBRATEDONE event
pub fn stopped(&mut self) -> STOPPED_W<'_>
[src]
pub fn stopped(&mut self) -> STOPPED_W<'_>
[src]Bit 5 - Enable or disable interrupt for STOPPED event
pub fn ch0limith(&mut self) -> CH0LIMITH_W<'_>
[src]
pub fn ch0limith(&mut self) -> CH0LIMITH_W<'_>
[src]Bit 6 - Enable or disable interrupt for CH[0].LIMITH event
pub fn ch0limitl(&mut self) -> CH0LIMITL_W<'_>
[src]
pub fn ch0limitl(&mut self) -> CH0LIMITL_W<'_>
[src]Bit 7 - Enable or disable interrupt for CH[0].LIMITL event
pub fn ch1limith(&mut self) -> CH1LIMITH_W<'_>
[src]
pub fn ch1limith(&mut self) -> CH1LIMITH_W<'_>
[src]Bit 8 - Enable or disable interrupt for CH[1].LIMITH event
pub fn ch1limitl(&mut self) -> CH1LIMITL_W<'_>
[src]
pub fn ch1limitl(&mut self) -> CH1LIMITL_W<'_>
[src]Bit 9 - Enable or disable interrupt for CH[1].LIMITL event
pub fn ch2limith(&mut self) -> CH2LIMITH_W<'_>
[src]
pub fn ch2limith(&mut self) -> CH2LIMITH_W<'_>
[src]Bit 10 - Enable or disable interrupt for CH[2].LIMITH event
pub fn ch2limitl(&mut self) -> CH2LIMITL_W<'_>
[src]
pub fn ch2limitl(&mut self) -> CH2LIMITL_W<'_>
[src]Bit 11 - Enable or disable interrupt for CH[2].LIMITL event
pub fn ch3limith(&mut self) -> CH3LIMITH_W<'_>
[src]
pub fn ch3limith(&mut self) -> CH3LIMITH_W<'_>
[src]Bit 12 - Enable or disable interrupt for CH[3].LIMITH event
pub fn ch3limitl(&mut self) -> CH3LIMITL_W<'_>
[src]
pub fn ch3limitl(&mut self) -> CH3LIMITL_W<'_>
[src]Bit 13 - Enable or disable interrupt for CH[3].LIMITL event
pub fn ch4limith(&mut self) -> CH4LIMITH_W<'_>
[src]
pub fn ch4limith(&mut self) -> CH4LIMITH_W<'_>
[src]Bit 14 - Enable or disable interrupt for CH[4].LIMITH event
pub fn ch4limitl(&mut self) -> CH4LIMITL_W<'_>
[src]
pub fn ch4limitl(&mut self) -> CH4LIMITL_W<'_>
[src]Bit 15 - Enable or disable interrupt for CH[4].LIMITL event
pub fn ch5limith(&mut self) -> CH5LIMITH_W<'_>
[src]
pub fn ch5limith(&mut self) -> CH5LIMITH_W<'_>
[src]Bit 16 - Enable or disable interrupt for CH[5].LIMITH event
pub fn ch5limitl(&mut self) -> CH5LIMITL_W<'_>
[src]
pub fn ch5limitl(&mut self) -> CH5LIMITL_W<'_>
[src]Bit 17 - Enable or disable interrupt for CH[5].LIMITL event
pub fn ch6limith(&mut self) -> CH6LIMITH_W<'_>
[src]
pub fn ch6limith(&mut self) -> CH6LIMITH_W<'_>
[src]Bit 18 - Enable or disable interrupt for CH[6].LIMITH event
pub fn ch6limitl(&mut self) -> CH6LIMITL_W<'_>
[src]
pub fn ch6limitl(&mut self) -> CH6LIMITL_W<'_>
[src]Bit 19 - Enable or disable interrupt for CH[6].LIMITL event
pub fn ch7limith(&mut self) -> CH7LIMITH_W<'_>
[src]
pub fn ch7limith(&mut self) -> CH7LIMITH_W<'_>
[src]Bit 20 - Enable or disable interrupt for CH[7].LIMITH event
pub fn ch7limitl(&mut self) -> CH7LIMITL_W<'_>
[src]
pub fn ch7limitl(&mut self) -> CH7LIMITL_W<'_>
[src]Bit 21 - Enable or disable interrupt for CH[7].LIMITL event
impl W<u32, Reg<u32, _INTENSET>>
[src]
impl W<u32, Reg<u32, _INTENSET>>
[src]pub fn started(&mut self) -> STARTED_W<'_>
[src]
pub fn started(&mut self) -> STARTED_W<'_>
[src]Bit 0 - Write ‘1’ to Enable interrupt for STARTED event
pub fn resultdone(&mut self) -> RESULTDONE_W<'_>
[src]
pub fn resultdone(&mut self) -> RESULTDONE_W<'_>
[src]Bit 3 - Write ‘1’ to Enable interrupt for RESULTDONE event
pub fn calibratedone(&mut self) -> CALIBRATEDONE_W<'_>
[src]
pub fn calibratedone(&mut self) -> CALIBRATEDONE_W<'_>
[src]Bit 4 - Write ‘1’ to Enable interrupt for CALIBRATEDONE event
pub fn stopped(&mut self) -> STOPPED_W<'_>
[src]
pub fn stopped(&mut self) -> STOPPED_W<'_>
[src]Bit 5 - Write ‘1’ to Enable interrupt for STOPPED event
pub fn ch0limith(&mut self) -> CH0LIMITH_W<'_>
[src]
pub fn ch0limith(&mut self) -> CH0LIMITH_W<'_>
[src]Bit 6 - Write ‘1’ to Enable interrupt for CH[0].LIMITH event
pub fn ch0limitl(&mut self) -> CH0LIMITL_W<'_>
[src]
pub fn ch0limitl(&mut self) -> CH0LIMITL_W<'_>
[src]Bit 7 - Write ‘1’ to Enable interrupt for CH[0].LIMITL event
pub fn ch1limith(&mut self) -> CH1LIMITH_W<'_>
[src]
pub fn ch1limith(&mut self) -> CH1LIMITH_W<'_>
[src]Bit 8 - Write ‘1’ to Enable interrupt for CH[1].LIMITH event
pub fn ch1limitl(&mut self) -> CH1LIMITL_W<'_>
[src]
pub fn ch1limitl(&mut self) -> CH1LIMITL_W<'_>
[src]Bit 9 - Write ‘1’ to Enable interrupt for CH[1].LIMITL event
pub fn ch2limith(&mut self) -> CH2LIMITH_W<'_>
[src]
pub fn ch2limith(&mut self) -> CH2LIMITH_W<'_>
[src]Bit 10 - Write ‘1’ to Enable interrupt for CH[2].LIMITH event
pub fn ch2limitl(&mut self) -> CH2LIMITL_W<'_>
[src]
pub fn ch2limitl(&mut self) -> CH2LIMITL_W<'_>
[src]Bit 11 - Write ‘1’ to Enable interrupt for CH[2].LIMITL event
pub fn ch3limith(&mut self) -> CH3LIMITH_W<'_>
[src]
pub fn ch3limith(&mut self) -> CH3LIMITH_W<'_>
[src]Bit 12 - Write ‘1’ to Enable interrupt for CH[3].LIMITH event
pub fn ch3limitl(&mut self) -> CH3LIMITL_W<'_>
[src]
pub fn ch3limitl(&mut self) -> CH3LIMITL_W<'_>
[src]Bit 13 - Write ‘1’ to Enable interrupt for CH[3].LIMITL event
pub fn ch4limith(&mut self) -> CH4LIMITH_W<'_>
[src]
pub fn ch4limith(&mut self) -> CH4LIMITH_W<'_>
[src]Bit 14 - Write ‘1’ to Enable interrupt for CH[4].LIMITH event
pub fn ch4limitl(&mut self) -> CH4LIMITL_W<'_>
[src]
pub fn ch4limitl(&mut self) -> CH4LIMITL_W<'_>
[src]Bit 15 - Write ‘1’ to Enable interrupt for CH[4].LIMITL event
pub fn ch5limith(&mut self) -> CH5LIMITH_W<'_>
[src]
pub fn ch5limith(&mut self) -> CH5LIMITH_W<'_>
[src]Bit 16 - Write ‘1’ to Enable interrupt for CH[5].LIMITH event
pub fn ch5limitl(&mut self) -> CH5LIMITL_W<'_>
[src]
pub fn ch5limitl(&mut self) -> CH5LIMITL_W<'_>
[src]Bit 17 - Write ‘1’ to Enable interrupt for CH[5].LIMITL event
pub fn ch6limith(&mut self) -> CH6LIMITH_W<'_>
[src]
pub fn ch6limith(&mut self) -> CH6LIMITH_W<'_>
[src]Bit 18 - Write ‘1’ to Enable interrupt for CH[6].LIMITH event
pub fn ch6limitl(&mut self) -> CH6LIMITL_W<'_>
[src]
pub fn ch6limitl(&mut self) -> CH6LIMITL_W<'_>
[src]Bit 19 - Write ‘1’ to Enable interrupt for CH[6].LIMITL event
pub fn ch7limith(&mut self) -> CH7LIMITH_W<'_>
[src]
pub fn ch7limith(&mut self) -> CH7LIMITH_W<'_>
[src]Bit 20 - Write ‘1’ to Enable interrupt for CH[7].LIMITH event
pub fn ch7limitl(&mut self) -> CH7LIMITL_W<'_>
[src]
pub fn ch7limitl(&mut self) -> CH7LIMITL_W<'_>
[src]Bit 21 - Write ‘1’ to Enable interrupt for CH[7].LIMITL event
impl W<u32, Reg<u32, _INTENCLR>>
[src]
impl W<u32, Reg<u32, _INTENCLR>>
[src]pub fn started(&mut self) -> STARTED_W<'_>
[src]
pub fn started(&mut self) -> STARTED_W<'_>
[src]Bit 0 - Write ‘1’ to Disable interrupt for STARTED event
pub fn resultdone(&mut self) -> RESULTDONE_W<'_>
[src]
pub fn resultdone(&mut self) -> RESULTDONE_W<'_>
[src]Bit 3 - Write ‘1’ to Disable interrupt for RESULTDONE event
pub fn calibratedone(&mut self) -> CALIBRATEDONE_W<'_>
[src]
pub fn calibratedone(&mut self) -> CALIBRATEDONE_W<'_>
[src]Bit 4 - Write ‘1’ to Disable interrupt for CALIBRATEDONE event
pub fn stopped(&mut self) -> STOPPED_W<'_>
[src]
pub fn stopped(&mut self) -> STOPPED_W<'_>
[src]Bit 5 - Write ‘1’ to Disable interrupt for STOPPED event
pub fn ch0limith(&mut self) -> CH0LIMITH_W<'_>
[src]
pub fn ch0limith(&mut self) -> CH0LIMITH_W<'_>
[src]Bit 6 - Write ‘1’ to Disable interrupt for CH[0].LIMITH event
pub fn ch0limitl(&mut self) -> CH0LIMITL_W<'_>
[src]
pub fn ch0limitl(&mut self) -> CH0LIMITL_W<'_>
[src]Bit 7 - Write ‘1’ to Disable interrupt for CH[0].LIMITL event
pub fn ch1limith(&mut self) -> CH1LIMITH_W<'_>
[src]
pub fn ch1limith(&mut self) -> CH1LIMITH_W<'_>
[src]Bit 8 - Write ‘1’ to Disable interrupt for CH[1].LIMITH event
pub fn ch1limitl(&mut self) -> CH1LIMITL_W<'_>
[src]
pub fn ch1limitl(&mut self) -> CH1LIMITL_W<'_>
[src]Bit 9 - Write ‘1’ to Disable interrupt for CH[1].LIMITL event
pub fn ch2limith(&mut self) -> CH2LIMITH_W<'_>
[src]
pub fn ch2limith(&mut self) -> CH2LIMITH_W<'_>
[src]Bit 10 - Write ‘1’ to Disable interrupt for CH[2].LIMITH event
pub fn ch2limitl(&mut self) -> CH2LIMITL_W<'_>
[src]
pub fn ch2limitl(&mut self) -> CH2LIMITL_W<'_>
[src]Bit 11 - Write ‘1’ to Disable interrupt for CH[2].LIMITL event
pub fn ch3limith(&mut self) -> CH3LIMITH_W<'_>
[src]
pub fn ch3limith(&mut self) -> CH3LIMITH_W<'_>
[src]Bit 12 - Write ‘1’ to Disable interrupt for CH[3].LIMITH event
pub fn ch3limitl(&mut self) -> CH3LIMITL_W<'_>
[src]
pub fn ch3limitl(&mut self) -> CH3LIMITL_W<'_>
[src]Bit 13 - Write ‘1’ to Disable interrupt for CH[3].LIMITL event
pub fn ch4limith(&mut self) -> CH4LIMITH_W<'_>
[src]
pub fn ch4limith(&mut self) -> CH4LIMITH_W<'_>
[src]Bit 14 - Write ‘1’ to Disable interrupt for CH[4].LIMITH event
pub fn ch4limitl(&mut self) -> CH4LIMITL_W<'_>
[src]
pub fn ch4limitl(&mut self) -> CH4LIMITL_W<'_>
[src]Bit 15 - Write ‘1’ to Disable interrupt for CH[4].LIMITL event
pub fn ch5limith(&mut self) -> CH5LIMITH_W<'_>
[src]
pub fn ch5limith(&mut self) -> CH5LIMITH_W<'_>
[src]Bit 16 - Write ‘1’ to Disable interrupt for CH[5].LIMITH event
pub fn ch5limitl(&mut self) -> CH5LIMITL_W<'_>
[src]
pub fn ch5limitl(&mut self) -> CH5LIMITL_W<'_>
[src]Bit 17 - Write ‘1’ to Disable interrupt for CH[5].LIMITL event
pub fn ch6limith(&mut self) -> CH6LIMITH_W<'_>
[src]
pub fn ch6limith(&mut self) -> CH6LIMITH_W<'_>
[src]Bit 18 - Write ‘1’ to Disable interrupt for CH[6].LIMITH event
pub fn ch6limitl(&mut self) -> CH6LIMITL_W<'_>
[src]
pub fn ch6limitl(&mut self) -> CH6LIMITL_W<'_>
[src]Bit 19 - Write ‘1’ to Disable interrupt for CH[6].LIMITL event
pub fn ch7limith(&mut self) -> CH7LIMITH_W<'_>
[src]
pub fn ch7limith(&mut self) -> CH7LIMITH_W<'_>
[src]Bit 20 - Write ‘1’ to Disable interrupt for CH[7].LIMITH event
pub fn ch7limitl(&mut self) -> CH7LIMITL_W<'_>
[src]
pub fn ch7limitl(&mut self) -> CH7LIMITL_W<'_>
[src]Bit 21 - Write ‘1’ to Disable interrupt for CH[7].LIMITL event
impl W<u32, Reg<u32, _OVERSAMPLE>>
[src]
impl W<u32, Reg<u32, _OVERSAMPLE>>
[src]pub fn oversample(&mut self) -> OVERSAMPLE_W<'_>
[src]
pub fn oversample(&mut self) -> OVERSAMPLE_W<'_>
[src]Bits 0:3 - Oversample control
impl W<u32, Reg<u32, _SHORTS>>
[src]
impl W<u32, Reg<u32, _SHORTS>>
[src]pub fn compare0_clear(&mut self) -> COMPARE0_CLEAR_W<'_>
[src]
pub fn compare0_clear(&mut self) -> COMPARE0_CLEAR_W<'_>
[src]Bit 0 - Shortcut between COMPARE[0] event and CLEAR task
pub fn compare1_clear(&mut self) -> COMPARE1_CLEAR_W<'_>
[src]
pub fn compare1_clear(&mut self) -> COMPARE1_CLEAR_W<'_>
[src]Bit 1 - Shortcut between COMPARE[1] event and CLEAR task
pub fn compare2_clear(&mut self) -> COMPARE2_CLEAR_W<'_>
[src]
pub fn compare2_clear(&mut self) -> COMPARE2_CLEAR_W<'_>
[src]Bit 2 - Shortcut between COMPARE[2] event and CLEAR task
pub fn compare3_clear(&mut self) -> COMPARE3_CLEAR_W<'_>
[src]
pub fn compare3_clear(&mut self) -> COMPARE3_CLEAR_W<'_>
[src]Bit 3 - Shortcut between COMPARE[3] event and CLEAR task
pub fn compare0_stop(&mut self) -> COMPARE0_STOP_W<'_>
[src]
pub fn compare0_stop(&mut self) -> COMPARE0_STOP_W<'_>
[src]Bit 8 - Shortcut between COMPARE[0] event and STOP task
pub fn compare1_stop(&mut self) -> COMPARE1_STOP_W<'_>
[src]
pub fn compare1_stop(&mut self) -> COMPARE1_STOP_W<'_>
[src]Bit 9 - Shortcut between COMPARE[1] event and STOP task
pub fn compare2_stop(&mut self) -> COMPARE2_STOP_W<'_>
[src]
pub fn compare2_stop(&mut self) -> COMPARE2_STOP_W<'_>
[src]Bit 10 - Shortcut between COMPARE[2] event and STOP task
pub fn compare3_stop(&mut self) -> COMPARE3_STOP_W<'_>
[src]
pub fn compare3_stop(&mut self) -> COMPARE3_STOP_W<'_>
[src]Bit 11 - Shortcut between COMPARE[3] event and STOP task
impl W<u32, Reg<u32, _INTENSET>>
[src]
impl W<u32, Reg<u32, _INTENSET>>
[src]pub fn compare0(&mut self) -> COMPARE0_W<'_>
[src]
pub fn compare0(&mut self) -> COMPARE0_W<'_>
[src]Bit 16 - Write ‘1’ to Enable interrupt for COMPARE[0] event
pub fn compare1(&mut self) -> COMPARE1_W<'_>
[src]
pub fn compare1(&mut self) -> COMPARE1_W<'_>
[src]Bit 17 - Write ‘1’ to Enable interrupt for COMPARE[1] event
pub fn compare2(&mut self) -> COMPARE2_W<'_>
[src]
pub fn compare2(&mut self) -> COMPARE2_W<'_>
[src]Bit 18 - Write ‘1’ to Enable interrupt for COMPARE[2] event
pub fn compare3(&mut self) -> COMPARE3_W<'_>
[src]
pub fn compare3(&mut self) -> COMPARE3_W<'_>
[src]Bit 19 - Write ‘1’ to Enable interrupt for COMPARE[3] event
impl W<u32, Reg<u32, _INTENCLR>>
[src]
impl W<u32, Reg<u32, _INTENCLR>>
[src]pub fn compare0(&mut self) -> COMPARE0_W<'_>
[src]
pub fn compare0(&mut self) -> COMPARE0_W<'_>
[src]Bit 16 - Write ‘1’ to Disable interrupt for COMPARE[0] event
pub fn compare1(&mut self) -> COMPARE1_W<'_>
[src]
pub fn compare1(&mut self) -> COMPARE1_W<'_>
[src]Bit 17 - Write ‘1’ to Disable interrupt for COMPARE[1] event
pub fn compare2(&mut self) -> COMPARE2_W<'_>
[src]
pub fn compare2(&mut self) -> COMPARE2_W<'_>
[src]Bit 18 - Write ‘1’ to Disable interrupt for COMPARE[2] event
pub fn compare3(&mut self) -> COMPARE3_W<'_>
[src]
pub fn compare3(&mut self) -> COMPARE3_W<'_>
[src]Bit 19 - Write ‘1’ to Disable interrupt for COMPARE[3] event
impl W<u32, Reg<u32, _PRESCALER>>
[src]
impl W<u32, Reg<u32, _PRESCALER>>
[src]pub fn prescaler(&mut self) -> PRESCALER_W<'_>
[src]
pub fn prescaler(&mut self) -> PRESCALER_W<'_>
[src]Bits 0:3 - Prescaler value
impl W<u32, Reg<u32, _INTENSET>>
[src]
impl W<u32, Reg<u32, _INTENSET>>
[src]pub fn compare0(&mut self) -> COMPARE0_W<'_>
[src]
pub fn compare0(&mut self) -> COMPARE0_W<'_>
[src]Bit 16 - Write ‘1’ to Enable interrupt for COMPARE[0] event
pub fn compare1(&mut self) -> COMPARE1_W<'_>
[src]
pub fn compare1(&mut self) -> COMPARE1_W<'_>
[src]Bit 17 - Write ‘1’ to Enable interrupt for COMPARE[1] event
pub fn compare2(&mut self) -> COMPARE2_W<'_>
[src]
pub fn compare2(&mut self) -> COMPARE2_W<'_>
[src]Bit 18 - Write ‘1’ to Enable interrupt for COMPARE[2] event
pub fn compare3(&mut self) -> COMPARE3_W<'_>
[src]
pub fn compare3(&mut self) -> COMPARE3_W<'_>
[src]Bit 19 - Write ‘1’ to Enable interrupt for COMPARE[3] event
impl W<u32, Reg<u32, _INTENCLR>>
[src]
impl W<u32, Reg<u32, _INTENCLR>>
[src]pub fn ovrflw(&mut self) -> OVRFLW_W<'_>
[src]
pub fn ovrflw(&mut self) -> OVRFLW_W<'_>
[src]Bit 1 - Write ‘1’ to Disable interrupt for OVRFLW event
pub fn compare0(&mut self) -> COMPARE0_W<'_>
[src]
pub fn compare0(&mut self) -> COMPARE0_W<'_>
[src]Bit 16 - Write ‘1’ to Disable interrupt for COMPARE[0] event
pub fn compare1(&mut self) -> COMPARE1_W<'_>
[src]
pub fn compare1(&mut self) -> COMPARE1_W<'_>
[src]Bit 17 - Write ‘1’ to Disable interrupt for COMPARE[1] event
pub fn compare2(&mut self) -> COMPARE2_W<'_>
[src]
pub fn compare2(&mut self) -> COMPARE2_W<'_>
[src]Bit 18 - Write ‘1’ to Disable interrupt for COMPARE[2] event
pub fn compare3(&mut self) -> COMPARE3_W<'_>
[src]
pub fn compare3(&mut self) -> COMPARE3_W<'_>
[src]Bit 19 - Write ‘1’ to Disable interrupt for COMPARE[3] event
impl W<u32, Reg<u32, _EVTEN>>
[src]
impl W<u32, Reg<u32, _EVTEN>>
[src]pub fn ovrflw(&mut self) -> OVRFLW_W<'_>
[src]
pub fn ovrflw(&mut self) -> OVRFLW_W<'_>
[src]Bit 1 - Enable or disable event routing for OVRFLW event
pub fn compare0(&mut self) -> COMPARE0_W<'_>
[src]
pub fn compare0(&mut self) -> COMPARE0_W<'_>
[src]Bit 16 - Enable or disable event routing for COMPARE[0] event
pub fn compare1(&mut self) -> COMPARE1_W<'_>
[src]
pub fn compare1(&mut self) -> COMPARE1_W<'_>
[src]Bit 17 - Enable or disable event routing for COMPARE[1] event
pub fn compare2(&mut self) -> COMPARE2_W<'_>
[src]
pub fn compare2(&mut self) -> COMPARE2_W<'_>
[src]Bit 18 - Enable or disable event routing for COMPARE[2] event
pub fn compare3(&mut self) -> COMPARE3_W<'_>
[src]
pub fn compare3(&mut self) -> COMPARE3_W<'_>
[src]Bit 19 - Enable or disable event routing for COMPARE[3] event
impl W<u32, Reg<u32, _EVTENSET>>
[src]
impl W<u32, Reg<u32, _EVTENSET>>
[src]pub fn ovrflw(&mut self) -> OVRFLW_W<'_>
[src]
pub fn ovrflw(&mut self) -> OVRFLW_W<'_>
[src]Bit 1 - Write ‘1’ to Enable event routing for OVRFLW event
pub fn compare0(&mut self) -> COMPARE0_W<'_>
[src]
pub fn compare0(&mut self) -> COMPARE0_W<'_>
[src]Bit 16 - Write ‘1’ to Enable event routing for COMPARE[0] event
pub fn compare1(&mut self) -> COMPARE1_W<'_>
[src]
pub fn compare1(&mut self) -> COMPARE1_W<'_>
[src]Bit 17 - Write ‘1’ to Enable event routing for COMPARE[1] event
pub fn compare2(&mut self) -> COMPARE2_W<'_>
[src]
pub fn compare2(&mut self) -> COMPARE2_W<'_>
[src]Bit 18 - Write ‘1’ to Enable event routing for COMPARE[2] event
pub fn compare3(&mut self) -> COMPARE3_W<'_>
[src]
pub fn compare3(&mut self) -> COMPARE3_W<'_>
[src]Bit 19 - Write ‘1’ to Enable event routing for COMPARE[3] event
impl W<u32, Reg<u32, _EVTENCLR>>
[src]
impl W<u32, Reg<u32, _EVTENCLR>>
[src]pub fn ovrflw(&mut self) -> OVRFLW_W<'_>
[src]
pub fn ovrflw(&mut self) -> OVRFLW_W<'_>
[src]Bit 1 - Write ‘1’ to Disable event routing for OVRFLW event
pub fn compare0(&mut self) -> COMPARE0_W<'_>
[src]
pub fn compare0(&mut self) -> COMPARE0_W<'_>
[src]Bit 16 - Write ‘1’ to Disable event routing for COMPARE[0] event
pub fn compare1(&mut self) -> COMPARE1_W<'_>
[src]
pub fn compare1(&mut self) -> COMPARE1_W<'_>
[src]Bit 17 - Write ‘1’ to Disable event routing for COMPARE[1] event
pub fn compare2(&mut self) -> COMPARE2_W<'_>
[src]
pub fn compare2(&mut self) -> COMPARE2_W<'_>
[src]Bit 18 - Write ‘1’ to Disable event routing for COMPARE[2] event
pub fn compare3(&mut self) -> COMPARE3_W<'_>
[src]
pub fn compare3(&mut self) -> COMPARE3_W<'_>
[src]Bit 19 - Write ‘1’ to Disable event routing for COMPARE[3] event
impl W<u32, Reg<u32, _PRESCALER>>
[src]
impl W<u32, Reg<u32, _PRESCALER>>
[src]pub fn prescaler(&mut self) -> PRESCALER_W<'_>
[src]
pub fn prescaler(&mut self) -> PRESCALER_W<'_>
[src]Bits 0:11 - Prescaler value
impl W<u32, Reg<u32, _SHORTS>>
[src]
impl W<u32, Reg<u32, _SHORTS>>
[src]pub fn valrdy_stop(&mut self) -> VALRDY_STOP_W<'_>
[src]
pub fn valrdy_stop(&mut self) -> VALRDY_STOP_W<'_>
[src]Bit 0 - Shortcut between VALRDY event and STOP task
impl W<u32, Reg<u32, _ECBDATAPTR>>
[src]
impl W<u32, Reg<u32, _ECBDATAPTR>>
[src]pub fn ecbdataptr(&mut self) -> ECBDATAPTR_W<'_>
[src]
pub fn ecbdataptr(&mut self) -> ECBDATAPTR_W<'_>
[src]Bits 0:31 - Pointer to the ECB data structure (see Table 1 ECB data structure overview)
impl W<u32, Reg<u32, _SHORTS>>
[src]
impl W<u32, Reg<u32, _SHORTS>>
[src]pub fn endksgen_crypt(&mut self) -> ENDKSGEN_CRYPT_W<'_>
[src]
pub fn endksgen_crypt(&mut self) -> ENDKSGEN_CRYPT_W<'_>
[src]Bit 0 - Shortcut between ENDKSGEN event and CRYPT task
impl W<u32, Reg<u32, _INTENSET>>
[src]
impl W<u32, Reg<u32, _INTENSET>>
[src]pub fn endksgen(&mut self) -> ENDKSGEN_W<'_>
[src]
pub fn endksgen(&mut self) -> ENDKSGEN_W<'_>
[src]Bit 0 - Write ‘1’ to Enable interrupt for ENDKSGEN event
pub fn endcrypt(&mut self) -> ENDCRYPT_W<'_>
[src]
pub fn endcrypt(&mut self) -> ENDCRYPT_W<'_>
[src]Bit 1 - Write ‘1’ to Enable interrupt for ENDCRYPT event
impl W<u32, Reg<u32, _INTENCLR>>
[src]
impl W<u32, Reg<u32, _INTENCLR>>
[src]pub fn endksgen(&mut self) -> ENDKSGEN_W<'_>
[src]
pub fn endksgen(&mut self) -> ENDKSGEN_W<'_>
[src]Bit 0 - Write ‘1’ to Disable interrupt for ENDKSGEN event
pub fn endcrypt(&mut self) -> ENDCRYPT_W<'_>
[src]
pub fn endcrypt(&mut self) -> ENDCRYPT_W<'_>
[src]Bit 1 - Write ‘1’ to Disable interrupt for ENDCRYPT event
impl W<u32, Reg<u32, _SCRATCHPTR>>
[src]
impl W<u32, Reg<u32, _SCRATCHPTR>>
[src]pub fn scratchptr(&mut self) -> SCRATCHPTR_W<'_>
[src]
pub fn scratchptr(&mut self) -> SCRATCHPTR_W<'_>
[src]Bits 0:31 - Pointer to a scratch data area used for temporary storage during key-stream generation, MIC generation and encryption/decryption.
impl W<u32, Reg<u32, _INTENSET>>
[src]
impl W<u32, Reg<u32, _INTENSET>>
[src]pub fn resolved(&mut self) -> RESOLVED_W<'_>
[src]
pub fn resolved(&mut self) -> RESOLVED_W<'_>
[src]Bit 1 - Write ‘1’ to Enable interrupt for RESOLVED event
pub fn notresolved(&mut self) -> NOTRESOLVED_W<'_>
[src]
pub fn notresolved(&mut self) -> NOTRESOLVED_W<'_>
[src]Bit 2 - Write ‘1’ to Enable interrupt for NOTRESOLVED event
impl W<u32, Reg<u32, _INTENCLR>>
[src]
impl W<u32, Reg<u32, _INTENCLR>>
[src]pub fn resolved(&mut self) -> RESOLVED_W<'_>
[src]
pub fn resolved(&mut self) -> RESOLVED_W<'_>
[src]Bit 1 - Write ‘1’ to Disable interrupt for RESOLVED event
pub fn notresolved(&mut self) -> NOTRESOLVED_W<'_>
[src]
pub fn notresolved(&mut self) -> NOTRESOLVED_W<'_>
[src]Bit 2 - Write ‘1’ to Disable interrupt for NOTRESOLVED event
impl W<u32, Reg<u32, _SCRATCHPTR>>
[src]
impl W<u32, Reg<u32, _SCRATCHPTR>>
[src]pub fn scratchptr(&mut self) -> SCRATCHPTR_W<'_>
[src]
pub fn scratchptr(&mut self) -> SCRATCHPTR_W<'_>
[src]Bits 0:31 - Pointer to a scratch data area used for temporary storage during resolution.A space of minimum 3 bytes must be reserved.
impl W<u32, Reg<u32, _SHORTS>>
[src]
impl W<u32, Reg<u32, _SHORTS>>
[src]pub fn reportrdy_readclracc(&mut self) -> REPORTRDY_READCLRACC_W<'_>
[src]
pub fn reportrdy_readclracc(&mut self) -> REPORTRDY_READCLRACC_W<'_>
[src]Bit 0 - Shortcut between REPORTRDY event and READCLRACC task
pub fn samplerdy_stop(&mut self) -> SAMPLERDY_STOP_W<'_>
[src]
pub fn samplerdy_stop(&mut self) -> SAMPLERDY_STOP_W<'_>
[src]Bit 1 - Shortcut between SAMPLERDY event and STOP task
pub fn reportrdy_rdclracc(&mut self) -> REPORTRDY_RDCLRACC_W<'_>
[src]
pub fn reportrdy_rdclracc(&mut self) -> REPORTRDY_RDCLRACC_W<'_>
[src]Bit 2 - Shortcut between REPORTRDY event and RDCLRACC task
pub fn reportrdy_stop(&mut self) -> REPORTRDY_STOP_W<'_>
[src]
pub fn reportrdy_stop(&mut self) -> REPORTRDY_STOP_W<'_>
[src]Bit 3 - Shortcut between REPORTRDY event and STOP task
pub fn dblrdy_rdclrdbl(&mut self) -> DBLRDY_RDCLRDBL_W<'_>
[src]
pub fn dblrdy_rdclrdbl(&mut self) -> DBLRDY_RDCLRDBL_W<'_>
[src]Bit 4 - Shortcut between DBLRDY event and RDCLRDBL task
pub fn dblrdy_stop(&mut self) -> DBLRDY_STOP_W<'_>
[src]
pub fn dblrdy_stop(&mut self) -> DBLRDY_STOP_W<'_>
[src]Bit 5 - Shortcut between DBLRDY event and STOP task
pub fn samplerdy_readclracc(&mut self) -> SAMPLERDY_READCLRACC_W<'_>
[src]
pub fn samplerdy_readclracc(&mut self) -> SAMPLERDY_READCLRACC_W<'_>
[src]Bit 6 - Shortcut between SAMPLERDY event and READCLRACC task
impl W<u32, Reg<u32, _INTENSET>>
[src]
impl W<u32, Reg<u32, _INTENSET>>
[src]pub fn samplerdy(&mut self) -> SAMPLERDY_W<'_>
[src]
pub fn samplerdy(&mut self) -> SAMPLERDY_W<'_>
[src]Bit 0 - Write ‘1’ to Enable interrupt for SAMPLERDY event
pub fn reportrdy(&mut self) -> REPORTRDY_W<'_>
[src]
pub fn reportrdy(&mut self) -> REPORTRDY_W<'_>
[src]Bit 1 - Write ‘1’ to Enable interrupt for REPORTRDY event
impl W<u32, Reg<u32, _INTENCLR>>
[src]
impl W<u32, Reg<u32, _INTENCLR>>
[src]pub fn samplerdy(&mut self) -> SAMPLERDY_W<'_>
[src]
pub fn samplerdy(&mut self) -> SAMPLERDY_W<'_>
[src]Bit 0 - Write ‘1’ to Disable interrupt for SAMPLERDY event
pub fn reportrdy(&mut self) -> REPORTRDY_W<'_>
[src]
pub fn reportrdy(&mut self) -> REPORTRDY_W<'_>
[src]Bit 1 - Write ‘1’ to Disable interrupt for REPORTRDY event
impl W<u32, Reg<u32, _SAMPLEPER>>
[src]
impl W<u32, Reg<u32, _SAMPLEPER>>
[src]pub fn sampleper(&mut self) -> SAMPLEPER_W<'_>
[src]
pub fn sampleper(&mut self) -> SAMPLEPER_W<'_>
[src]Bits 0:3 - Sample period. The SAMPLE register will be updated for every new sample
impl W<u32, Reg<u32, _REPORTPER>>
[src]
impl W<u32, Reg<u32, _REPORTPER>>
[src]pub fn reportper(&mut self) -> REPORTPER_W<'_>
[src]
pub fn reportper(&mut self) -> REPORTPER_W<'_>
[src]Bits 0:3 - Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated
impl W<u32, Reg<u32, _SHORTS>>
[src]
impl W<u32, Reg<u32, _SHORTS>>
[src]pub fn ready_sample(&mut self) -> READY_SAMPLE_W<'_>
[src]
pub fn ready_sample(&mut self) -> READY_SAMPLE_W<'_>
[src]Bit 0 - Shortcut between READY event and SAMPLE task
pub fn ready_stop(&mut self) -> READY_STOP_W<'_>
[src]
pub fn ready_stop(&mut self) -> READY_STOP_W<'_>
[src]Bit 1 - Shortcut between READY event and STOP task
pub fn down_stop(&mut self) -> DOWN_STOP_W<'_>
[src]
pub fn down_stop(&mut self) -> DOWN_STOP_W<'_>
[src]Bit 2 - Shortcut between DOWN event and STOP task
pub fn cross_stop(&mut self) -> CROSS_STOP_W<'_>
[src]
pub fn cross_stop(&mut self) -> CROSS_STOP_W<'_>
[src]Bit 4 - Shortcut between CROSS event and STOP task
impl W<u32, Reg<u32, _EXTREFSEL>>
[src]
impl W<u32, Reg<u32, _EXTREFSEL>>
[src]pub fn extrefsel(&mut self) -> EXTREFSEL_W<'_>
[src]
pub fn extrefsel(&mut self) -> EXTREFSEL_W<'_>
[src]Bits 0:2 - External analog reference select
impl W<u32, Reg<u32, _SHORTS>>
[src]
impl W<u32, Reg<u32, _SHORTS>>
[src]pub fn ready_sample(&mut self) -> READY_SAMPLE_W<'_>
[src]
pub fn ready_sample(&mut self) -> READY_SAMPLE_W<'_>
[src]Bit 0 - Shortcut between READY event and SAMPLE task
pub fn ready_stop(&mut self) -> READY_STOP_W<'_>
[src]
pub fn ready_stop(&mut self) -> READY_STOP_W<'_>
[src]Bit 1 - Shortcut between READY event and STOP task
pub fn down_stop(&mut self) -> DOWN_STOP_W<'_>
[src]
pub fn down_stop(&mut self) -> DOWN_STOP_W<'_>
[src]Bit 2 - Shortcut between DOWN event and STOP task
pub fn cross_stop(&mut self) -> CROSS_STOP_W<'_>
[src]
pub fn cross_stop(&mut self) -> CROSS_STOP_W<'_>
[src]Bit 4 - Shortcut between CROSS event and STOP task
impl W<u32, Reg<u32, _EXTREFSEL>>
[src]
impl W<u32, Reg<u32, _EXTREFSEL>>
[src]pub fn extrefsel(&mut self) -> EXTREFSEL_W<'_>
[src]
pub fn extrefsel(&mut self) -> EXTREFSEL_W<'_>
[src]Bit 0 - External analog reference select
impl W<u32, Reg<u32, _ANADETECT>>
[src]
impl W<u32, Reg<u32, _ANADETECT>>
[src]pub fn anadetect(&mut self) -> ANADETECT_W<'_>
[src]
pub fn anadetect(&mut self) -> ANADETECT_W<'_>
[src]Bits 0:1 - Analog detect configuration
impl W<u32, Reg<u32, _INTEN>>
[src]
impl W<u32, Reg<u32, _INTEN>>
[src]pub fn triggered0(&mut self) -> TRIGGERED0_W<'_>
[src]
pub fn triggered0(&mut self) -> TRIGGERED0_W<'_>
[src]Bit 0 - Enable or disable interrupt for TRIGGERED[0] event
pub fn triggered1(&mut self) -> TRIGGERED1_W<'_>
[src]
pub fn triggered1(&mut self) -> TRIGGERED1_W<'_>
[src]Bit 1 - Enable or disable interrupt for TRIGGERED[1] event
pub fn triggered2(&mut self) -> TRIGGERED2_W<'_>
[src]
pub fn triggered2(&mut self) -> TRIGGERED2_W<'_>
[src]Bit 2 - Enable or disable interrupt for TRIGGERED[2] event
pub fn triggered3(&mut self) -> TRIGGERED3_W<'_>
[src]
pub fn triggered3(&mut self) -> TRIGGERED3_W<'_>
[src]Bit 3 - Enable or disable interrupt for TRIGGERED[3] event
pub fn triggered4(&mut self) -> TRIGGERED4_W<'_>
[src]
pub fn triggered4(&mut self) -> TRIGGERED4_W<'_>
[src]Bit 4 - Enable or disable interrupt for TRIGGERED[4] event
pub fn triggered5(&mut self) -> TRIGGERED5_W<'_>
[src]
pub fn triggered5(&mut self) -> TRIGGERED5_W<'_>
[src]Bit 5 - Enable or disable interrupt for TRIGGERED[5] event
pub fn triggered6(&mut self) -> TRIGGERED6_W<'_>
[src]
pub fn triggered6(&mut self) -> TRIGGERED6_W<'_>
[src]Bit 6 - Enable or disable interrupt for TRIGGERED[6] event
pub fn triggered7(&mut self) -> TRIGGERED7_W<'_>
[src]
pub fn triggered7(&mut self) -> TRIGGERED7_W<'_>
[src]Bit 7 - Enable or disable interrupt for TRIGGERED[7] event
pub fn triggered8(&mut self) -> TRIGGERED8_W<'_>
[src]
pub fn triggered8(&mut self) -> TRIGGERED8_W<'_>
[src]Bit 8 - Enable or disable interrupt for TRIGGERED[8] event
pub fn triggered9(&mut self) -> TRIGGERED9_W<'_>
[src]
pub fn triggered9(&mut self) -> TRIGGERED9_W<'_>
[src]Bit 9 - Enable or disable interrupt for TRIGGERED[9] event
pub fn triggered10(&mut self) -> TRIGGERED10_W<'_>
[src]
pub fn triggered10(&mut self) -> TRIGGERED10_W<'_>
[src]Bit 10 - Enable or disable interrupt for TRIGGERED[10] event
pub fn triggered11(&mut self) -> TRIGGERED11_W<'_>
[src]
pub fn triggered11(&mut self) -> TRIGGERED11_W<'_>
[src]Bit 11 - Enable or disable interrupt for TRIGGERED[11] event
pub fn triggered12(&mut self) -> TRIGGERED12_W<'_>
[src]
pub fn triggered12(&mut self) -> TRIGGERED12_W<'_>
[src]Bit 12 - Enable or disable interrupt for TRIGGERED[12] event
pub fn triggered13(&mut self) -> TRIGGERED13_W<'_>
[src]
pub fn triggered13(&mut self) -> TRIGGERED13_W<'_>
[src]Bit 13 - Enable or disable interrupt for TRIGGERED[13] event
pub fn triggered14(&mut self) -> TRIGGERED14_W<'_>
[src]
pub fn triggered14(&mut self) -> TRIGGERED14_W<'_>
[src]Bit 14 - Enable or disable interrupt for TRIGGERED[14] event
pub fn triggered15(&mut self) -> TRIGGERED15_W<'_>
[src]
pub fn triggered15(&mut self) -> TRIGGERED15_W<'_>
[src]Bit 15 - Enable or disable interrupt for TRIGGERED[15] event
impl W<u32, Reg<u32, _INTENSET>>
[src]
impl W<u32, Reg<u32, _INTENSET>>
[src]pub fn triggered0(&mut self) -> TRIGGERED0_W<'_>
[src]
pub fn triggered0(&mut self) -> TRIGGERED0_W<'_>
[src]Bit 0 - Write ‘1’ to Enable interrupt for TRIGGERED[0] event
pub fn triggered1(&mut self) -> TRIGGERED1_W<'_>
[src]
pub fn triggered1(&mut self) -> TRIGGERED1_W<'_>
[src]Bit 1 - Write ‘1’ to Enable interrupt for TRIGGERED[1] event
pub fn triggered2(&mut self) -> TRIGGERED2_W<'_>
[src]
pub fn triggered2(&mut self) -> TRIGGERED2_W<'_>
[src]Bit 2 - Write ‘1’ to Enable interrupt for TRIGGERED[2] event
pub fn triggered3(&mut self) -> TRIGGERED3_W<'_>
[src]
pub fn triggered3(&mut self) -> TRIGGERED3_W<'_>
[src]Bit 3 - Write ‘1’ to Enable interrupt for TRIGGERED[3] event
pub fn triggered4(&mut self) -> TRIGGERED4_W<'_>
[src]
pub fn triggered4(&mut self) -> TRIGGERED4_W<'_>
[src]Bit 4 - Write ‘1’ to Enable interrupt for TRIGGERED[4] event
pub fn triggered5(&mut self) -> TRIGGERED5_W<'_>
[src]
pub fn triggered5(&mut self) -> TRIGGERED5_W<'_>
[src]Bit 5 - Write ‘1’ to Enable interrupt for TRIGGERED[5] event
pub fn triggered6(&mut self) -> TRIGGERED6_W<'_>
[src]
pub fn triggered6(&mut self) -> TRIGGERED6_W<'_>
[src]Bit 6 - Write ‘1’ to Enable interrupt for TRIGGERED[6] event
pub fn triggered7(&mut self) -> TRIGGERED7_W<'_>
[src]
pub fn triggered7(&mut self) -> TRIGGERED7_W<'_>
[src]Bit 7 - Write ‘1’ to Enable interrupt for TRIGGERED[7] event
pub fn triggered8(&mut self) -> TRIGGERED8_W<'_>
[src]
pub fn triggered8(&mut self) -> TRIGGERED8_W<'_>
[src]Bit 8 - Write ‘1’ to Enable interrupt for TRIGGERED[8] event
pub fn triggered9(&mut self) -> TRIGGERED9_W<'_>
[src]
pub fn triggered9(&mut self) -> TRIGGERED9_W<'_>
[src]Bit 9 - Write ‘1’ to Enable interrupt for TRIGGERED[9] event
pub fn triggered10(&mut self) -> TRIGGERED10_W<'_>
[src]
pub fn triggered10(&mut self) -> TRIGGERED10_W<'_>
[src]Bit 10 - Write ‘1’ to Enable interrupt for TRIGGERED[10] event
pub fn triggered11(&mut self) -> TRIGGERED11_W<'_>
[src]
pub fn triggered11(&mut self) -> TRIGGERED11_W<'_>
[src]Bit 11 - Write ‘1’ to Enable interrupt for TRIGGERED[11] event
pub fn triggered12(&mut self) -> TRIGGERED12_W<'_>
[src]
pub fn triggered12(&mut self) -> TRIGGERED12_W<'_>
[src]Bit 12 - Write ‘1’ to Enable interrupt for TRIGGERED[12] event
pub fn triggered13(&mut self) -> TRIGGERED13_W<'_>
[src]
pub fn triggered13(&mut self) -> TRIGGERED13_W<'_>
[src]Bit 13 - Write ‘1’ to Enable interrupt for TRIGGERED[13] event
pub fn triggered14(&mut self) -> TRIGGERED14_W<'_>
[src]
pub fn triggered14(&mut self) -> TRIGGERED14_W<'_>
[src]Bit 14 - Write ‘1’ to Enable interrupt for TRIGGERED[14] event
pub fn triggered15(&mut self) -> TRIGGERED15_W<'_>
[src]
pub fn triggered15(&mut self) -> TRIGGERED15_W<'_>
[src]Bit 15 - Write ‘1’ to Enable interrupt for TRIGGERED[15] event
impl W<u32, Reg<u32, _INTENCLR>>
[src]
impl W<u32, Reg<u32, _INTENCLR>>
[src]pub fn triggered0(&mut self) -> TRIGGERED0_W<'_>
[src]
pub fn triggered0(&mut self) -> TRIGGERED0_W<'_>
[src]Bit 0 - Write ‘1’ to Disable interrupt for TRIGGERED[0] event
pub fn triggered1(&mut self) -> TRIGGERED1_W<'_>
[src]
pub fn triggered1(&mut self) -> TRIGGERED1_W<'_>
[src]Bit 1 - Write ‘1’ to Disable interrupt for TRIGGERED[1] event
pub fn triggered2(&mut self) -> TRIGGERED2_W<'_>
[src]
pub fn triggered2(&mut self) -> TRIGGERED2_W<'_>
[src]Bit 2 - Write ‘1’ to Disable interrupt for TRIGGERED[2] event
pub fn triggered3(&mut self) -> TRIGGERED3_W<'_>
[src]
pub fn triggered3(&mut self) -> TRIGGERED3_W<'_>
[src]Bit 3 - Write ‘1’ to Disable interrupt for TRIGGERED[3] event
pub fn triggered4(&mut self) -> TRIGGERED4_W<'_>
[src]
pub fn triggered4(&mut self) -> TRIGGERED4_W<'_>
[src]Bit 4 - Write ‘1’ to Disable interrupt for TRIGGERED[4] event
pub fn triggered5(&mut self) -> TRIGGERED5_W<'_>
[src]
pub fn triggered5(&mut self) -> TRIGGERED5_W<'_>
[src]Bit 5 - Write ‘1’ to Disable interrupt for TRIGGERED[5] event
pub fn triggered6(&mut self) -> TRIGGERED6_W<'_>
[src]
pub fn triggered6(&mut self) -> TRIGGERED6_W<'_>
[src]Bit 6 - Write ‘1’ to Disable interrupt for TRIGGERED[6] event
pub fn triggered7(&mut self) -> TRIGGERED7_W<'_>
[src]
pub fn triggered7(&mut self) -> TRIGGERED7_W<'_>
[src]Bit 7 - Write ‘1’ to Disable interrupt for TRIGGERED[7] event
pub fn triggered8(&mut self) -> TRIGGERED8_W<'_>
[src]
pub fn triggered8(&mut self) -> TRIGGERED8_W<'_>
[src]Bit 8 - Write ‘1’ to Disable interrupt for TRIGGERED[8] event
pub fn triggered9(&mut self) -> TRIGGERED9_W<'_>
[src]
pub fn triggered9(&mut self) -> TRIGGERED9_W<'_>
[src]Bit 9 - Write ‘1’ to Disable interrupt for TRIGGERED[9] event
pub fn triggered10(&mut self) -> TRIGGERED10_W<'_>
[src]
pub fn triggered10(&mut self) -> TRIGGERED10_W<'_>
[src]Bit 10 - Write ‘1’ to Disable interrupt for TRIGGERED[10] event
pub fn triggered11(&mut self) -> TRIGGERED11_W<'_>
[src]
pub fn triggered11(&mut self) -> TRIGGERED11_W<'_>
[src]Bit 11 - Write ‘1’ to Disable interrupt for TRIGGERED[11] event
pub fn triggered12(&mut self) -> TRIGGERED12_W<'_>
[src]
pub fn triggered12(&mut self) -> TRIGGERED12_W<'_>
[src]Bit 12 - Write ‘1’ to Disable interrupt for TRIGGERED[12] event
pub fn triggered13(&mut self) -> TRIGGERED13_W<'_>
[src]
pub fn triggered13(&mut self) -> TRIGGERED13_W<'_>
[src]Bit 13 - Write ‘1’ to Disable interrupt for TRIGGERED[13] event
pub fn triggered14(&mut self) -> TRIGGERED14_W<'_>
[src]
pub fn triggered14(&mut self) -> TRIGGERED14_W<'_>
[src]Bit 14 - Write ‘1’ to Disable interrupt for TRIGGERED[14] event
pub fn triggered15(&mut self) -> TRIGGERED15_W<'_>
[src]
pub fn triggered15(&mut self) -> TRIGGERED15_W<'_>
[src]Bit 15 - Write ‘1’ to Disable interrupt for TRIGGERED[15] event
impl W<u32, Reg<u32, _SHORTS>>
[src]
impl W<u32, Reg<u32, _SHORTS>>
[src]pub fn compare0_clear(&mut self) -> COMPARE0_CLEAR_W<'_>
[src]
pub fn compare0_clear(&mut self) -> COMPARE0_CLEAR_W<'_>
[src]Bit 0 - Shortcut between COMPARE[0] event and CLEAR task
pub fn compare1_clear(&mut self) -> COMPARE1_CLEAR_W<'_>
[src]
pub fn compare1_clear(&mut self) -> COMPARE1_CLEAR_W<'_>
[src]Bit 1 - Shortcut between COMPARE[1] event and CLEAR task
pub fn compare2_clear(&mut self) -> COMPARE2_CLEAR_W<'_>
[src]
pub fn compare2_clear(&mut self) -> COMPARE2_CLEAR_W<'_>
[src]Bit 2 - Shortcut between COMPARE[2] event and CLEAR task
pub fn compare3_clear(&mut self) -> COMPARE3_CLEAR_W<'_>
[src]
pub fn compare3_clear(&mut self) -> COMPARE3_CLEAR_W<'_>
[src]Bit 3 - Shortcut between COMPARE[3] event and CLEAR task
pub fn compare4_clear(&mut self) -> COMPARE4_CLEAR_W<'_>
[src]
pub fn compare4_clear(&mut self) -> COMPARE4_CLEAR_W<'_>
[src]Bit 4 - Shortcut between COMPARE[4] event and CLEAR task
pub fn compare5_clear(&mut self) -> COMPARE5_CLEAR_W<'_>
[src]
pub fn compare5_clear(&mut self) -> COMPARE5_CLEAR_W<'_>
[src]Bit 5 - Shortcut between COMPARE[5] event and CLEAR task
pub fn compare0_stop(&mut self) -> COMPARE0_STOP_W<'_>
[src]
pub fn compare0_stop(&mut self) -> COMPARE0_STOP_W<'_>
[src]Bit 8 - Shortcut between COMPARE[0] event and STOP task
pub fn compare1_stop(&mut self) -> COMPARE1_STOP_W<'_>
[src]
pub fn compare1_stop(&mut self) -> COMPARE1_STOP_W<'_>
[src]Bit 9 - Shortcut between COMPARE[1] event and STOP task
pub fn compare2_stop(&mut self) -> COMPARE2_STOP_W<'_>
[src]
pub fn compare2_stop(&mut self) -> COMPARE2_STOP_W<'_>
[src]Bit 10 - Shortcut between COMPARE[2] event and STOP task
pub fn compare3_stop(&mut self) -> COMPARE3_STOP_W<'_>
[src]
pub fn compare3_stop(&mut self) -> COMPARE3_STOP_W<'_>
[src]Bit 11 - Shortcut between COMPARE[3] event and STOP task
pub fn compare4_stop(&mut self) -> COMPARE4_STOP_W<'_>
[src]
pub fn compare4_stop(&mut self) -> COMPARE4_STOP_W<'_>
[src]Bit 12 - Shortcut between COMPARE[4] event and STOP task
pub fn compare5_stop(&mut self) -> COMPARE5_STOP_W<'_>
[src]
pub fn compare5_stop(&mut self) -> COMPARE5_STOP_W<'_>
[src]Bit 13 - Shortcut between COMPARE[5] event and STOP task
impl W<u32, Reg<u32, _INTENSET>>
[src]
impl W<u32, Reg<u32, _INTENSET>>
[src]pub fn compare0(&mut self) -> COMPARE0_W<'_>
[src]
pub fn compare0(&mut self) -> COMPARE0_W<'_>
[src]Bit 16 - Write ‘1’ to Enable interrupt for COMPARE[0] event
pub fn compare1(&mut self) -> COMPARE1_W<'_>
[src]
pub fn compare1(&mut self) -> COMPARE1_W<'_>
[src]Bit 17 - Write ‘1’ to Enable interrupt for COMPARE[1] event
pub fn compare2(&mut self) -> COMPARE2_W<'_>
[src]
pub fn compare2(&mut self) -> COMPARE2_W<'_>
[src]Bit 18 - Write ‘1’ to Enable interrupt for COMPARE[2] event
pub fn compare3(&mut self) -> COMPARE3_W<'_>
[src]
pub fn compare3(&mut self) -> COMPARE3_W<'_>
[src]Bit 19 - Write ‘1’ to Enable interrupt for COMPARE[3] event
pub fn compare4(&mut self) -> COMPARE4_W<'_>
[src]
pub fn compare4(&mut self) -> COMPARE4_W<'_>
[src]Bit 20 - Write ‘1’ to Enable interrupt for COMPARE[4] event
pub fn compare5(&mut self) -> COMPARE5_W<'_>
[src]
pub fn compare5(&mut self) -> COMPARE5_W<'_>
[src]Bit 21 - Write ‘1’ to Enable interrupt for COMPARE[5] event
impl W<u32, Reg<u32, _INTENCLR>>
[src]
impl W<u32, Reg<u32, _INTENCLR>>
[src]pub fn compare0(&mut self) -> COMPARE0_W<'_>
[src]
pub fn compare0(&mut self) -> COMPARE0_W<'_>
[src]Bit 16 - Write ‘1’ to Disable interrupt for COMPARE[0] event
pub fn compare1(&mut self) -> COMPARE1_W<'_>
[src]
pub fn compare1(&mut self) -> COMPARE1_W<'_>
[src]Bit 17 - Write ‘1’ to Disable interrupt for COMPARE[1] event
pub fn compare2(&mut self) -> COMPARE2_W<'_>
[src]
pub fn compare2(&mut self) -> COMPARE2_W<'_>
[src]Bit 18 - Write ‘1’ to Disable interrupt for COMPARE[2] event
pub fn compare3(&mut self) -> COMPARE3_W<'_>
[src]
pub fn compare3(&mut self) -> COMPARE3_W<'_>
[src]Bit 19 - Write ‘1’ to Disable interrupt for COMPARE[3] event
pub fn compare4(&mut self) -> COMPARE4_W<'_>
[src]
pub fn compare4(&mut self) -> COMPARE4_W<'_>
[src]Bit 20 - Write ‘1’ to Disable interrupt for COMPARE[4] event
pub fn compare5(&mut self) -> COMPARE5_W<'_>
[src]
pub fn compare5(&mut self) -> COMPARE5_W<'_>
[src]Bit 21 - Write ‘1’ to Disable interrupt for COMPARE[5] event
impl W<u32, Reg<u32, _PRESCALER>>
[src]
impl W<u32, Reg<u32, _PRESCALER>>
[src]pub fn prescaler(&mut self) -> PRESCALER_W<'_>
[src]
pub fn prescaler(&mut self) -> PRESCALER_W<'_>
[src]Bits 0:3 - Prescaler value
impl W<u32, Reg<u32, _SHORTS>>
[src]
impl W<u32, Reg<u32, _SHORTS>>
[src]pub fn seqend0_stop(&mut self) -> SEQEND0_STOP_W<'_>
[src]
pub fn seqend0_stop(&mut self) -> SEQEND0_STOP_W<'_>
[src]Bit 0 - Shortcut between SEQEND[0] event and STOP task
pub fn seqend1_stop(&mut self) -> SEQEND1_STOP_W<'_>
[src]
pub fn seqend1_stop(&mut self) -> SEQEND1_STOP_W<'_>
[src]Bit 1 - Shortcut between SEQEND[1] event and STOP task
pub fn loopsdone_seqstart0(&mut self) -> LOOPSDONE_SEQSTART0_W<'_>
[src]
pub fn loopsdone_seqstart0(&mut self) -> LOOPSDONE_SEQSTART0_W<'_>
[src]Bit 2 - Shortcut between LOOPSDONE event and SEQSTART[0] task
pub fn loopsdone_seqstart1(&mut self) -> LOOPSDONE_SEQSTART1_W<'_>
[src]
pub fn loopsdone_seqstart1(&mut self) -> LOOPSDONE_SEQSTART1_W<'_>
[src]Bit 3 - Shortcut between LOOPSDONE event and SEQSTART[1] task
pub fn loopsdone_stop(&mut self) -> LOOPSDONE_STOP_W<'_>
[src]
pub fn loopsdone_stop(&mut self) -> LOOPSDONE_STOP_W<'_>
[src]Bit 4 - Shortcut between LOOPSDONE event and STOP task
impl W<u32, Reg<u32, _INTEN>>
[src]
impl W<u32, Reg<u32, _INTEN>>
[src]pub fn stopped(&mut self) -> STOPPED_W<'_>
[src]
pub fn stopped(&mut self) -> STOPPED_W<'_>
[src]Bit 1 - Enable or disable interrupt for STOPPED event
pub fn seqstarted0(&mut self) -> SEQSTARTED0_W<'_>
[src]
pub fn seqstarted0(&mut self) -> SEQSTARTED0_W<'_>
[src]Bit 2 - Enable or disable interrupt for SEQSTARTED[0] event
pub fn seqstarted1(&mut self) -> SEQSTARTED1_W<'_>
[src]
pub fn seqstarted1(&mut self) -> SEQSTARTED1_W<'_>
[src]Bit 3 - Enable or disable interrupt for SEQSTARTED[1] event
pub fn seqend0(&mut self) -> SEQEND0_W<'_>
[src]
pub fn seqend0(&mut self) -> SEQEND0_W<'_>
[src]Bit 4 - Enable or disable interrupt for SEQEND[0] event
pub fn seqend1(&mut self) -> SEQEND1_W<'_>
[src]
pub fn seqend1(&mut self) -> SEQEND1_W<'_>
[src]Bit 5 - Enable or disable interrupt for SEQEND[1] event
pub fn pwmperiodend(&mut self) -> PWMPERIODEND_W<'_>
[src]
pub fn pwmperiodend(&mut self) -> PWMPERIODEND_W<'_>
[src]Bit 6 - Enable or disable interrupt for PWMPERIODEND event
pub fn loopsdone(&mut self) -> LOOPSDONE_W<'_>
[src]
pub fn loopsdone(&mut self) -> LOOPSDONE_W<'_>
[src]Bit 7 - Enable or disable interrupt for LOOPSDONE event
impl W<u32, Reg<u32, _INTENSET>>
[src]
impl W<u32, Reg<u32, _INTENSET>>
[src]pub fn stopped(&mut self) -> STOPPED_W<'_>
[src]
pub fn stopped(&mut self) -> STOPPED_W<'_>
[src]Bit 1 - Write ‘1’ to Enable interrupt for STOPPED event
pub fn seqstarted0(&mut self) -> SEQSTARTED0_W<'_>
[src]
pub fn seqstarted0(&mut self) -> SEQSTARTED0_W<'_>
[src]Bit 2 - Write ‘1’ to Enable interrupt for SEQSTARTED[0] event
pub fn seqstarted1(&mut self) -> SEQSTARTED1_W<'_>
[src]
pub fn seqstarted1(&mut self) -> SEQSTARTED1_W<'_>
[src]Bit 3 - Write ‘1’ to Enable interrupt for SEQSTARTED[1] event
pub fn seqend0(&mut self) -> SEQEND0_W<'_>
[src]
pub fn seqend0(&mut self) -> SEQEND0_W<'_>
[src]Bit 4 - Write ‘1’ to Enable interrupt for SEQEND[0] event
pub fn seqend1(&mut self) -> SEQEND1_W<'_>
[src]
pub fn seqend1(&mut self) -> SEQEND1_W<'_>
[src]Bit 5 - Write ‘1’ to Enable interrupt for SEQEND[1] event
pub fn pwmperiodend(&mut self) -> PWMPERIODEND_W<'_>
[src]
pub fn pwmperiodend(&mut self) -> PWMPERIODEND_W<'_>
[src]Bit 6 - Write ‘1’ to Enable interrupt for PWMPERIODEND event
pub fn loopsdone(&mut self) -> LOOPSDONE_W<'_>
[src]
pub fn loopsdone(&mut self) -> LOOPSDONE_W<'_>
[src]Bit 7 - Write ‘1’ to Enable interrupt for LOOPSDONE event
impl W<u32, Reg<u32, _INTENCLR>>
[src]
impl W<u32, Reg<u32, _INTENCLR>>
[src]pub fn stopped(&mut self) -> STOPPED_W<'_>
[src]
pub fn stopped(&mut self) -> STOPPED_W<'_>
[src]Bit 1 - Write ‘1’ to Disable interrupt for STOPPED event
pub fn seqstarted0(&mut self) -> SEQSTARTED0_W<'_>
[src]
pub fn seqstarted0(&mut self) -> SEQSTARTED0_W<'_>
[src]Bit 2 - Write ‘1’ to Disable interrupt for SEQSTARTED[0] event
pub fn seqstarted1(&mut self) -> SEQSTARTED1_W<'_>
[src]
pub fn seqstarted1(&mut self) -> SEQSTARTED1_W<'_>
[src]Bit 3 - Write ‘1’ to Disable interrupt for SEQSTARTED[1] event
pub fn seqend0(&mut self) -> SEQEND0_W<'_>
[src]
pub fn seqend0(&mut self) -> SEQEND0_W<'_>
[src]Bit 4 - Write ‘1’ to Disable interrupt for SEQEND[0] event
pub fn seqend1(&mut self) -> SEQEND1_W<'_>
[src]
pub fn seqend1(&mut self) -> SEQEND1_W<'_>
[src]Bit 5 - Write ‘1’ to Disable interrupt for SEQEND[1] event
pub fn pwmperiodend(&mut self) -> PWMPERIODEND_W<'_>
[src]
pub fn pwmperiodend(&mut self) -> PWMPERIODEND_W<'_>
[src]Bit 6 - Write ‘1’ to Disable interrupt for PWMPERIODEND event
pub fn loopsdone(&mut self) -> LOOPSDONE_W<'_>
[src]
pub fn loopsdone(&mut self) -> LOOPSDONE_W<'_>
[src]Bit 7 - Write ‘1’ to Disable interrupt for LOOPSDONE event
impl W<u32, Reg<u32, _COUNTERTOP>>
[src]
impl W<u32, Reg<u32, _COUNTERTOP>>
[src]pub fn countertop(&mut self) -> COUNTERTOP_W<'_>
[src]
pub fn countertop(&mut self) -> COUNTERTOP_W<'_>
[src]Bits 0:14 - Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM will be used.
impl W<u32, Reg<u32, _PRESCALER>>
[src]
impl W<u32, Reg<u32, _PRESCALER>>
[src]pub fn prescaler(&mut self) -> PRESCALER_W<'_>
[src]
pub fn prescaler(&mut self) -> PRESCALER_W<'_>
[src]Bits 0:2 - Pre-scaler of PWM_CLK
impl W<u32, Reg<u32, _PTR>>
[src]
impl W<u32, Reg<u32, _PTR>>
[src]pub fn sampleptr(&mut self) -> SAMPLEPTR_W<'_>
[src]
pub fn sampleptr(&mut self) -> SAMPLEPTR_W<'_>
[src]Bits 0:31 - Address to write PDM samples to over DMA
impl W<u32, Reg<u32, _MAXCNT>>
[src]
impl W<u32, Reg<u32, _MAXCNT>>
[src]pub fn buffsize(&mut self) -> BUFFSIZE_W<'_>
[src]
pub fn buffsize(&mut self) -> BUFFSIZE_W<'_>
[src]Bits 0:14 - Length of DMA RAM allocation in number of samples
impl W<u32, Reg<u32, _GAINL>>
[src]
impl W<u32, Reg<u32, _GAINL>>
[src]pub fn gainl(&mut self) -> GAINL_W<'_>
[src]
pub fn gainl(&mut self) -> GAINL_W<'_>
[src]Bits 0:6 - Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (…) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (…) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust
impl W<u32, Reg<u32, _ERASEPAGE>>
[src]
impl W<u32, Reg<u32, _ERASEPAGE>>
[src]pub fn erasepage(&mut self) -> ERASEPAGE_W<'_>
[src]
pub fn erasepage(&mut self) -> ERASEPAGE_W<'_>
[src]Bits 0:31 - Register for starting erase of a page in Code area
impl W<u32, Reg<u32, _ERASEPCR1>>
[src]
impl W<u32, Reg<u32, _ERASEPCR1>>
[src]pub fn erasepcr1(&mut self) -> ERASEPCR1_W<'_>
[src]
pub fn erasepcr1(&mut self) -> ERASEPCR1_W<'_>
[src]Bits 0:31 - Register for erasing a page in Code area. Equivalent to ERASEPAGE.
impl W<u32, Reg<u32, _ERASEALL>>
[src]
impl W<u32, Reg<u32, _ERASEALL>>
[src]pub fn eraseall(&mut self) -> ERASEALL_W<'_>
[src]
pub fn eraseall(&mut self) -> ERASEALL_W<'_>
[src]Bit 0 - Erase all non-volatile memory including UICR registers. Note that code erase has to be enabled by CONFIG.EEN before the UICR can be erased.
impl W<u32, Reg<u32, _ERASEPCR0>>
[src]
impl W<u32, Reg<u32, _ERASEPCR0>>
[src]pub fn erasepcr0(&mut self) -> ERASEPCR0_W<'_>
[src]
pub fn erasepcr0(&mut self) -> ERASEPCR0_W<'_>
[src]Bits 0:31 - Register for starting erase of a page in Code area. Equivalent to ERASEPAGE.
impl W<u32, Reg<u32, _ERASEUICR>>
[src]
impl W<u32, Reg<u32, _ERASEUICR>>
[src]pub fn eraseuicr(&mut self) -> ERASEUICR_W<'_>
[src]
pub fn eraseuicr(&mut self) -> ERASEUICR_W<'_>
[src]Bit 0 - Register starting erase of all User Information Configuration Registers. Note that code erase has to be enabled by CONFIG.EEN before the UICR can be erased.
impl W<u32, Reg<u32, _ICACHECNF>>
[src]
impl W<u32, Reg<u32, _ICACHECNF>>
[src]pub fn cacheprofen(&mut self) -> CACHEPROFEN_W<'_>
[src]
pub fn cacheprofen(&mut self) -> CACHEPROFEN_W<'_>
[src]Bit 8 - Cache profiling enable
impl W<u32, Reg<u32, _CHENSET>>
[src]
impl W<u32, Reg<u32, _CHENSET>>
[src]pub fn ch0(&mut self) -> CH0_W<'_>
[src]
pub fn ch0(&mut self) -> CH0_W<'_>
[src]Bit 0 - Channel 0 enable set register. Writing ‘0’ has no effect
pub fn ch1(&mut self) -> CH1_W<'_>
[src]
pub fn ch1(&mut self) -> CH1_W<'_>
[src]Bit 1 - Channel 1 enable set register. Writing ‘0’ has no effect
pub fn ch2(&mut self) -> CH2_W<'_>
[src]
pub fn ch2(&mut self) -> CH2_W<'_>
[src]Bit 2 - Channel 2 enable set register. Writing ‘0’ has no effect
pub fn ch3(&mut self) -> CH3_W<'_>
[src]
pub fn ch3(&mut self) -> CH3_W<'_>
[src]Bit 3 - Channel 3 enable set register. Writing ‘0’ has no effect
pub fn ch4(&mut self) -> CH4_W<'_>
[src]
pub fn ch4(&mut self) -> CH4_W<'_>
[src]Bit 4 - Channel 4 enable set register. Writing ‘0’ has no effect
pub fn ch5(&mut self) -> CH5_W<'_>
[src]
pub fn ch5(&mut self) -> CH5_W<'_>
[src]Bit 5 - Channel 5 enable set register. Writing ‘0’ has no effect
pub fn ch6(&mut self) -> CH6_W<'_>
[src]
pub fn ch6(&mut self) -> CH6_W<'_>
[src]Bit 6 - Channel 6 enable set register. Writing ‘0’ has no effect
pub fn ch7(&mut self) -> CH7_W<'_>
[src]
pub fn ch7(&mut self) -> CH7_W<'_>
[src]Bit 7 - Channel 7 enable set register. Writing ‘0’ has no effect
pub fn ch8(&mut self) -> CH8_W<'_>
[src]
pub fn ch8(&mut self) -> CH8_W<'_>
[src]Bit 8 - Channel 8 enable set register. Writing ‘0’ has no effect
pub fn ch9(&mut self) -> CH9_W<'_>
[src]
pub fn ch9(&mut self) -> CH9_W<'_>
[src]Bit 9 - Channel 9 enable set register. Writing ‘0’ has no effect
pub fn ch10(&mut self) -> CH10_W<'_>
[src]
pub fn ch10(&mut self) -> CH10_W<'_>
[src]Bit 10 - Channel 10 enable set register. Writing ‘0’ has no effect
pub fn ch11(&mut self) -> CH11_W<'_>
[src]
pub fn ch11(&mut self) -> CH11_W<'_>
[src]Bit 11 - Channel 11 enable set register. Writing ‘0’ has no effect
pub fn ch12(&mut self) -> CH12_W<'_>
[src]
pub fn ch12(&mut self) -> CH12_W<'_>
[src]Bit 12 - Channel 12 enable set register. Writing ‘0’ has no effect
pub fn ch13(&mut self) -> CH13_W<'_>
[src]
pub fn ch13(&mut self) -> CH13_W<'_>
[src]Bit 13 - Channel 13 enable set register. Writing ‘0’ has no effect
pub fn ch14(&mut self) -> CH14_W<'_>
[src]
pub fn ch14(&mut self) -> CH14_W<'_>
[src]Bit 14 - Channel 14 enable set register. Writing ‘0’ has no effect
pub fn ch15(&mut self) -> CH15_W<'_>
[src]
pub fn ch15(&mut self) -> CH15_W<'_>
[src]Bit 15 - Channel 15 enable set register. Writing ‘0’ has no effect
pub fn ch16(&mut self) -> CH16_W<'_>
[src]
pub fn ch16(&mut self) -> CH16_W<'_>
[src]Bit 16 - Channel 16 enable set register. Writing ‘0’ has no effect
pub fn ch17(&mut self) -> CH17_W<'_>
[src]
pub fn ch17(&mut self) -> CH17_W<'_>
[src]Bit 17 - Channel 17 enable set register. Writing ‘0’ has no effect
pub fn ch18(&mut self) -> CH18_W<'_>
[src]
pub fn ch18(&mut self) -> CH18_W<'_>
[src]Bit 18 - Channel 18 enable set register. Writing ‘0’ has no effect
pub fn ch19(&mut self) -> CH19_W<'_>
[src]
pub fn ch19(&mut self) -> CH19_W<'_>
[src]Bit 19 - Channel 19 enable set register. Writing ‘0’ has no effect
pub fn ch20(&mut self) -> CH20_W<'_>
[src]
pub fn ch20(&mut self) -> CH20_W<'_>
[src]Bit 20 - Channel 20 enable set register. Writing ‘0’ has no effect
pub fn ch21(&mut self) -> CH21_W<'_>
[src]
pub fn ch21(&mut self) -> CH21_W<'_>
[src]Bit 21 - Channel 21 enable set register. Writing ‘0’ has no effect
pub fn ch22(&mut self) -> CH22_W<'_>
[src]
pub fn ch22(&mut self) -> CH22_W<'_>
[src]Bit 22 - Channel 22 enable set register. Writing ‘0’ has no effect
pub fn ch23(&mut self) -> CH23_W<'_>
[src]
pub fn ch23(&mut self) -> CH23_W<'_>
[src]Bit 23 - Channel 23 enable set register. Writing ‘0’ has no effect
pub fn ch24(&mut self) -> CH24_W<'_>
[src]
pub fn ch24(&mut self) -> CH24_W<'_>
[src]Bit 24 - Channel 24 enable set register. Writing ‘0’ has no effect
pub fn ch25(&mut self) -> CH25_W<'_>
[src]
pub fn ch25(&mut self) -> CH25_W<'_>
[src]Bit 25 - Channel 25 enable set register. Writing ‘0’ has no effect
pub fn ch26(&mut self) -> CH26_W<'_>
[src]
pub fn ch26(&mut self) -> CH26_W<'_>
[src]Bit 26 - Channel 26 enable set register. Writing ‘0’ has no effect
pub fn ch27(&mut self) -> CH27_W<'_>
[src]
pub fn ch27(&mut self) -> CH27_W<'_>
[src]Bit 27 - Channel 27 enable set register. Writing ‘0’ has no effect
pub fn ch28(&mut self) -> CH28_W<'_>
[src]
pub fn ch28(&mut self) -> CH28_W<'_>
[src]Bit 28 - Channel 28 enable set register. Writing ‘0’ has no effect
pub fn ch29(&mut self) -> CH29_W<'_>
[src]
pub fn ch29(&mut self) -> CH29_W<'_>
[src]Bit 29 - Channel 29 enable set register. Writing ‘0’ has no effect
impl W<u32, Reg<u32, _CHENCLR>>
[src]
impl W<u32, Reg<u32, _CHENCLR>>
[src]pub fn ch0(&mut self) -> CH0_W<'_>
[src]
pub fn ch0(&mut self) -> CH0_W<'_>
[src]Bit 0 - Channel 0 enable clear register. Writing ‘0’ has no effect
pub fn ch1(&mut self) -> CH1_W<'_>
[src]
pub fn ch1(&mut self) -> CH1_W<'_>
[src]Bit 1 - Channel 1 enable clear register. Writing ‘0’ has no effect
pub fn ch2(&mut self) -> CH2_W<'_>
[src]
pub fn ch2(&mut self) -> CH2_W<'_>
[src]Bit 2 - Channel 2 enable clear register. Writing ‘0’ has no effect
pub fn ch3(&mut self) -> CH3_W<'_>
[src]
pub fn ch3(&mut self) -> CH3_W<'_>
[src]Bit 3 - Channel 3 enable clear register. Writing ‘0’ has no effect
pub fn ch4(&mut self) -> CH4_W<'_>
[src]
pub fn ch4(&mut self) -> CH4_W<'_>
[src]Bit 4 - Channel 4 enable clear register. Writing ‘0’ has no effect
pub fn ch5(&mut self) -> CH5_W<'_>
[src]
pub fn ch5(&mut self) -> CH5_W<'_>
[src]Bit 5 - Channel 5 enable clear register. Writing ‘0’ has no effect
pub fn ch6(&mut self) -> CH6_W<'_>
[src]
pub fn ch6(&mut self) -> CH6_W<'_>
[src]Bit 6 - Channel 6 enable clear register. Writing ‘0’ has no effect
pub fn ch7(&mut self) -> CH7_W<'_>
[src]
pub fn ch7(&mut self) -> CH7_W<'_>
[src]Bit 7 - Channel 7 enable clear register. Writing ‘0’ has no effect
pub fn ch8(&mut self) -> CH8_W<'_>
[src]
pub fn ch8(&mut self) -> CH8_W<'_>
[src]Bit 8 - Channel 8 enable clear register. Writing ‘0’ has no effect
pub fn ch9(&mut self) -> CH9_W<'_>
[src]
pub fn ch9(&mut self) -> CH9_W<'_>
[src]Bit 9 - Channel 9 enable clear register. Writing ‘0’ has no effect
pub fn ch10(&mut self) -> CH10_W<'_>
[src]
pub fn ch10(&mut self) -> CH10_W<'_>
[src]Bit 10 - Channel 10 enable clear register. Writing ‘0’ has no effect
pub fn ch11(&mut self) -> CH11_W<'_>
[src]
pub fn ch11(&mut self) -> CH11_W<'_>
[src]Bit 11 - Channel 11 enable clear register. Writing ‘0’ has no effect
pub fn ch12(&mut self) -> CH12_W<'_>
[src]
pub fn ch12(&mut self) -> CH12_W<'_>
[src]Bit 12 - Channel 12 enable clear register. Writing ‘0’ has no effect
pub fn ch13(&mut self) -> CH13_W<'_>
[src]
pub fn ch13(&mut self) -> CH13_W<'_>
[src]Bit 13 - Channel 13 enable clear register. Writing ‘0’ has no effect
pub fn ch14(&mut self) -> CH14_W<'_>
[src]
pub fn ch14(&mut self) -> CH14_W<'_>
[src]Bit 14 - Channel 14 enable clear register. Writing ‘0’ has no effect
pub fn ch15(&mut self) -> CH15_W<'_>
[src]
pub fn ch15(&mut self) -> CH15_W<'_>
[src]Bit 15 - Channel 15 enable clear register. Writing ‘0’ has no effect
pub fn ch16(&mut self) -> CH16_W<'_>
[src]
pub fn ch16(&mut self) -> CH16_W<'_>
[src]Bit 16 - Channel 16 enable clear register. Writing ‘0’ has no effect
pub fn ch17(&mut self) -> CH17_W<'_>
[src]
pub fn ch17(&mut self) -> CH17_W<'_>
[src]Bit 17 - Channel 17 enable clear register. Writing ‘0’ has no effect
pub fn ch18(&mut self) -> CH18_W<'_>
[src]
pub fn ch18(&mut self) -> CH18_W<'_>
[src]Bit 18 - Channel 18 enable clear register. Writing ‘0’ has no effect
pub fn ch19(&mut self) -> CH19_W<'_>
[src]
pub fn ch19(&mut self) -> CH19_W<'_>
[src]Bit 19 - Channel 19 enable clear register. Writing ‘0’ has no effect
pub fn ch20(&mut self) -> CH20_W<'_>
[src]
pub fn ch20(&mut self) -> CH20_W<'_>
[src]Bit 20 - Channel 20 enable clear register. Writing ‘0’ has no effect
pub fn ch21(&mut self) -> CH21_W<'_>
[src]
pub fn ch21(&mut self) -> CH21_W<'_>
[src]Bit 21 - Channel 21 enable clear register. Writing ‘0’ has no effect
pub fn ch22(&mut self) -> CH22_W<'_>
[src]
pub fn ch22(&mut self) -> CH22_W<'_>
[src]Bit 22 - Channel 22 enable clear register. Writing ‘0’ has no effect
pub fn ch23(&mut self) -> CH23_W<'_>
[src]
pub fn ch23(&mut self) -> CH23_W<'_>
[src]Bit 23 - Channel 23 enable clear register. Writing ‘0’ has no effect
pub fn ch24(&mut self) -> CH24_W<'_>
[src]
pub fn ch24(&mut self) -> CH24_W<'_>
[src]Bit 24 - Channel 24 enable clear register. Writing ‘0’ has no effect
pub fn ch25(&mut self) -> CH25_W<'_>
[src]
pub fn ch25(&mut self) -> CH25_W<'_>
[src]Bit 25 - Channel 25 enable clear register. Writing ‘0’ has no effect
pub fn ch26(&mut self) -> CH26_W<'_>
[src]
pub fn ch26(&mut self) -> CH26_W<'_>
[src]Bit 26 - Channel 26 enable clear register. Writing ‘0’ has no effect
pub fn ch27(&mut self) -> CH27_W<'_>
[src]
pub fn ch27(&mut self) -> CH27_W<'_>
[src]Bit 27 - Channel 27 enable clear register. Writing ‘0’ has no effect
pub fn ch28(&mut self) -> CH28_W<'_>
[src]
pub fn ch28(&mut self) -> CH28_W<'_>
[src]Bit 28 - Channel 28 enable clear register. Writing ‘0’ has no effect
pub fn ch29(&mut self) -> CH29_W<'_>
[src]
pub fn ch29(&mut self) -> CH29_W<'_>
[src]Bit 29 - Channel 29 enable clear register. Writing ‘0’ has no effect
impl W<u32, Reg<u32, _INTEN>>
[src]
impl W<u32, Reg<u32, _INTEN>>
[src]pub fn region0wa(&mut self) -> REGION0WA_W<'_>
[src]
pub fn region0wa(&mut self) -> REGION0WA_W<'_>
[src]Bit 0 - Enable or disable interrupt for REGION[0].WA event
pub fn region0ra(&mut self) -> REGION0RA_W<'_>
[src]
pub fn region0ra(&mut self) -> REGION0RA_W<'_>
[src]Bit 1 - Enable or disable interrupt for REGION[0].RA event
pub fn region1wa(&mut self) -> REGION1WA_W<'_>
[src]
pub fn region1wa(&mut self) -> REGION1WA_W<'_>
[src]Bit 2 - Enable or disable interrupt for REGION[1].WA event
pub fn region1ra(&mut self) -> REGION1RA_W<'_>
[src]
pub fn region1ra(&mut self) -> REGION1RA_W<'_>
[src]Bit 3 - Enable or disable interrupt for REGION[1].RA event
pub fn region2wa(&mut self) -> REGION2WA_W<'_>
[src]
pub fn region2wa(&mut self) -> REGION2WA_W<'_>
[src]Bit 4 - Enable or disable interrupt for REGION[2].WA event
pub fn region2ra(&mut self) -> REGION2RA_W<'_>
[src]
pub fn region2ra(&mut self) -> REGION2RA_W<'_>
[src]Bit 5 - Enable or disable interrupt for REGION[2].RA event
pub fn region3wa(&mut self) -> REGION3WA_W<'_>
[src]
pub fn region3wa(&mut self) -> REGION3WA_W<'_>
[src]Bit 6 - Enable or disable interrupt for REGION[3].WA event
pub fn region3ra(&mut self) -> REGION3RA_W<'_>
[src]
pub fn region3ra(&mut self) -> REGION3RA_W<'_>
[src]Bit 7 - Enable or disable interrupt for REGION[3].RA event
pub fn pregion0wa(&mut self) -> PREGION0WA_W<'_>
[src]
pub fn pregion0wa(&mut self) -> PREGION0WA_W<'_>
[src]Bit 24 - Enable or disable interrupt for PREGION[0].WA event
pub fn pregion0ra(&mut self) -> PREGION0RA_W<'_>
[src]
pub fn pregion0ra(&mut self) -> PREGION0RA_W<'_>
[src]Bit 25 - Enable or disable interrupt for PREGION[0].RA event
pub fn pregion1wa(&mut self) -> PREGION1WA_W<'_>
[src]
pub fn pregion1wa(&mut self) -> PREGION1WA_W<'_>
[src]Bit 26 - Enable or disable interrupt for PREGION[1].WA event
pub fn pregion1ra(&mut self) -> PREGION1RA_W<'_>
[src]
pub fn pregion1ra(&mut self) -> PREGION1RA_W<'_>
[src]Bit 27 - Enable or disable interrupt for PREGION[1].RA event
impl W<u32, Reg<u32, _INTENSET>>
[src]
impl W<u32, Reg<u32, _INTENSET>>
[src]pub fn region0wa(&mut self) -> REGION0WA_W<'_>
[src]
pub fn region0wa(&mut self) -> REGION0WA_W<'_>
[src]Bit 0 - Write ‘1’ to Enable interrupt for REGION[0].WA event
pub fn region0ra(&mut self) -> REGION0RA_W<'_>
[src]
pub fn region0ra(&mut self) -> REGION0RA_W<'_>
[src]Bit 1 - Write ‘1’ to Enable interrupt for REGION[0].RA event
pub fn region1wa(&mut self) -> REGION1WA_W<'_>
[src]
pub fn region1wa(&mut self) -> REGION1WA_W<'_>
[src]Bit 2 - Write ‘1’ to Enable interrupt for REGION[1].WA event
pub fn region1ra(&mut self) -> REGION1RA_W<'_>
[src]
pub fn region1ra(&mut self) -> REGION1RA_W<'_>
[src]Bit 3 - Write ‘1’ to Enable interrupt for REGION[1].RA event
pub fn region2wa(&mut self) -> REGION2WA_W<'_>
[src]
pub fn region2wa(&mut self) -> REGION2WA_W<'_>
[src]Bit 4 - Write ‘1’ to Enable interrupt for REGION[2].WA event
pub fn region2ra(&mut self) -> REGION2RA_W<'_>
[src]
pub fn region2ra(&mut self) -> REGION2RA_W<'_>
[src]Bit 5 - Write ‘1’ to Enable interrupt for REGION[2].RA event
pub fn region3wa(&mut self) -> REGION3WA_W<'_>
[src]
pub fn region3wa(&mut self) -> REGION3WA_W<'_>
[src]Bit 6 - Write ‘1’ to Enable interrupt for REGION[3].WA event
pub fn region3ra(&mut self) -> REGION3RA_W<'_>
[src]
pub fn region3ra(&mut self) -> REGION3RA_W<'_>
[src]Bit 7 - Write ‘1’ to Enable interrupt for REGION[3].RA event
pub fn pregion0wa(&mut self) -> PREGION0WA_W<'_>
[src]
pub fn pregion0wa(&mut self) -> PREGION0WA_W<'_>
[src]Bit 24 - Write ‘1’ to Enable interrupt for PREGION[0].WA event
pub fn pregion0ra(&mut self) -> PREGION0RA_W<'_>
[src]
pub fn pregion0ra(&mut self) -> PREGION0RA_W<'_>
[src]Bit 25 - Write ‘1’ to Enable interrupt for PREGION[0].RA event
pub fn pregion1wa(&mut self) -> PREGION1WA_W<'_>
[src]
pub fn pregion1wa(&mut self) -> PREGION1WA_W<'_>
[src]Bit 26 - Write ‘1’ to Enable interrupt for PREGION[1].WA event
pub fn pregion1ra(&mut self) -> PREGION1RA_W<'_>
[src]
pub fn pregion1ra(&mut self) -> PREGION1RA_W<'_>
[src]Bit 27 - Write ‘1’ to Enable interrupt for PREGION[1].RA event
impl W<u32, Reg<u32, _INTENCLR>>
[src]
impl W<u32, Reg<u32, _INTENCLR>>
[src]pub fn region0wa(&mut self) -> REGION0WA_W<'_>
[src]
pub fn region0wa(&mut self) -> REGION0WA_W<'_>
[src]Bit 0 - Write ‘1’ to Disable interrupt for REGION[0].WA event
pub fn region0ra(&mut self) -> REGION0RA_W<'_>
[src]
pub fn region0ra(&mut self) -> REGION0RA_W<'_>
[src]Bit 1 - Write ‘1’ to Disable interrupt for REGION[0].RA event
pub fn region1wa(&mut self) -> REGION1WA_W<'_>
[src]
pub fn region1wa(&mut self) -> REGION1WA_W<'_>
[src]Bit 2 - Write ‘1’ to Disable interrupt for REGION[1].WA event
pub fn region1ra(&mut self) -> REGION1RA_W<'_>
[src]
pub fn region1ra(&mut self) -> REGION1RA_W<'_>
[src]Bit 3 - Write ‘1’ to Disable interrupt for REGION[1].RA event
pub fn region2wa(&mut self) -> REGION2WA_W<'_>
[src]
pub fn region2wa(&mut self) -> REGION2WA_W<'_>
[src]Bit 4 - Write ‘1’ to Disable interrupt for REGION[2].WA event
pub fn region2ra(&mut self) -> REGION2RA_W<'_>
[src]
pub fn region2ra(&mut self) -> REGION2RA_W<'_>
[src]Bit 5 - Write ‘1’ to Disable interrupt for REGION[2].RA event
pub fn region3wa(&mut self) -> REGION3WA_W<'_>
[src]
pub fn region3wa(&mut self) -> REGION3WA_W<'_>
[src]Bit 6 - Write ‘1’ to Disable interrupt for REGION[3].WA event
pub fn region3ra(&mut self) -> REGION3RA_W<'_>
[src]
pub fn region3ra(&mut self) -> REGION3RA_W<'_>
[src]Bit 7 - Write ‘1’ to Disable interrupt for REGION[3].RA event
pub fn pregion0wa(&mut self) -> PREGION0WA_W<'_>
[src]
pub fn pregion0wa(&mut self) -> PREGION0WA_W<'_>
[src]Bit 24 - Write ‘1’ to Disable interrupt for PREGION[0].WA event
pub fn pregion0ra(&mut self) -> PREGION0RA_W<'_>
[src]
pub fn pregion0ra(&mut self) -> PREGION0RA_W<'_>
[src]Bit 25 - Write ‘1’ to Disable interrupt for PREGION[0].RA event
pub fn pregion1wa(&mut self) -> PREGION1WA_W<'_>
[src]
pub fn pregion1wa(&mut self) -> PREGION1WA_W<'_>
[src]Bit 26 - Write ‘1’ to Disable interrupt for PREGION[1].WA event
pub fn pregion1ra(&mut self) -> PREGION1RA_W<'_>
[src]
pub fn pregion1ra(&mut self) -> PREGION1RA_W<'_>
[src]Bit 27 - Write ‘1’ to Disable interrupt for PREGION[1].RA event
impl W<u32, Reg<u32, _NMIEN>>
[src]
impl W<u32, Reg<u32, _NMIEN>>
[src]pub fn region0wa(&mut self) -> REGION0WA_W<'_>
[src]
pub fn region0wa(&mut self) -> REGION0WA_W<'_>
[src]Bit 0 - Enable or disable non-maskable interrupt for REGION[0].WA event
pub fn region0ra(&mut self) -> REGION0RA_W<'_>
[src]
pub fn region0ra(&mut self) -> REGION0RA_W<'_>
[src]Bit 1 - Enable or disable non-maskable interrupt for REGION[0].RA event
pub fn region1wa(&mut self) -> REGION1WA_W<'_>
[src]
pub fn region1wa(&mut self) -> REGION1WA_W<'_>
[src]Bit 2 - Enable or disable non-maskable interrupt for REGION[1].WA event
pub fn region1ra(&mut self) -> REGION1RA_W<'_>
[src]
pub fn region1ra(&mut self) -> REGION1RA_W<'_>
[src]Bit 3 - Enable or disable non-maskable interrupt for REGION[1].RA event
pub fn region2wa(&mut self) -> REGION2WA_W<'_>
[src]
pub fn region2wa(&mut self) -> REGION2WA_W<'_>
[src]Bit 4 - Enable or disable non-maskable interrupt for REGION[2].WA event
pub fn region2ra(&mut self) -> REGION2RA_W<'_>
[src]
pub fn region2ra(&mut self) -> REGION2RA_W<'_>
[src]Bit 5 - Enable or disable non-maskable interrupt for REGION[2].RA event
pub fn region3wa(&mut self) -> REGION3WA_W<'_>
[src]
pub fn region3wa(&mut self) -> REGION3WA_W<'_>
[src]Bit 6 - Enable or disable non-maskable interrupt for REGION[3].WA event
pub fn region3ra(&mut self) -> REGION3RA_W<'_>
[src]
pub fn region3ra(&mut self) -> REGION3RA_W<'_>
[src]Bit 7 - Enable or disable non-maskable interrupt for REGION[3].RA event
pub fn pregion0wa(&mut self) -> PREGION0WA_W<'_>
[src]
pub fn pregion0wa(&mut self) -> PREGION0WA_W<'_>
[src]Bit 24 - Enable or disable non-maskable interrupt for PREGION[0].WA event
pub fn pregion0ra(&mut self) -> PREGION0RA_W<'_>
[src]
pub fn pregion0ra(&mut self) -> PREGION0RA_W<'_>
[src]Bit 25 - Enable or disable non-maskable interrupt for PREGION[0].RA event
pub fn pregion1wa(&mut self) -> PREGION1WA_W<'_>
[src]
pub fn pregion1wa(&mut self) -> PREGION1WA_W<'_>
[src]Bit 26 - Enable or disable non-maskable interrupt for PREGION[1].WA event
pub fn pregion1ra(&mut self) -> PREGION1RA_W<'_>
[src]
pub fn pregion1ra(&mut self) -> PREGION1RA_W<'_>
[src]Bit 27 - Enable or disable non-maskable interrupt for PREGION[1].RA event
impl W<u32, Reg<u32, _NMIENSET>>
[src]
impl W<u32, Reg<u32, _NMIENSET>>
[src]pub fn region0wa(&mut self) -> REGION0WA_W<'_>
[src]
pub fn region0wa(&mut self) -> REGION0WA_W<'_>
[src]Bit 0 - Write ‘1’ to Enable non-maskable interrupt for REGION[0].WA event
pub fn region0ra(&mut self) -> REGION0RA_W<'_>
[src]
pub fn region0ra(&mut self) -> REGION0RA_W<'_>
[src]Bit 1 - Write ‘1’ to Enable non-maskable interrupt for REGION[0].RA event
pub fn region1wa(&mut self) -> REGION1WA_W<'_>
[src]
pub fn region1wa(&mut self) -> REGION1WA_W<'_>
[src]Bit 2 - Write ‘1’ to Enable non-maskable interrupt for REGION[1].WA event
pub fn region1ra(&mut self) -> REGION1RA_W<'_>
[src]
pub fn region1ra(&mut self) -> REGION1RA_W<'_>
[src]Bit 3 - Write ‘1’ to Enable non-maskable interrupt for REGION[1].RA event
pub fn region2wa(&mut self) -> REGION2WA_W<'_>
[src]
pub fn region2wa(&mut self) -> REGION2WA_W<'_>
[src]Bit 4 - Write ‘1’ to Enable non-maskable interrupt for REGION[2].WA event
pub fn region2ra(&mut self) -> REGION2RA_W<'_>
[src]
pub fn region2ra(&mut self) -> REGION2RA_W<'_>
[src]Bit 5 - Write ‘1’ to Enable non-maskable interrupt for REGION[2].RA event
pub fn region3wa(&mut self) -> REGION3WA_W<'_>
[src]
pub fn region3wa(&mut self) -> REGION3WA_W<'_>
[src]Bit 6 - Write ‘1’ to Enable non-maskable interrupt for REGION[3].WA event
pub fn region3ra(&mut self) -> REGION3RA_W<'_>
[src]
pub fn region3ra(&mut self) -> REGION3RA_W<'_>
[src]Bit 7 - Write ‘1’ to Enable non-maskable interrupt for REGION[3].RA event
pub fn pregion0wa(&mut self) -> PREGION0WA_W<'_>
[src]
pub fn pregion0wa(&mut self) -> PREGION0WA_W<'_>
[src]Bit 24 - Write ‘1’ to Enable non-maskable interrupt for PREGION[0].WA event
pub fn pregion0ra(&mut self) -> PREGION0RA_W<'_>
[src]
pub fn pregion0ra(&mut self) -> PREGION0RA_W<'_>
[src]Bit 25 - Write ‘1’ to Enable non-maskable interrupt for PREGION[0].RA event
pub fn pregion1wa(&mut self) -> PREGION1WA_W<'_>
[src]
pub fn pregion1wa(&mut self) -> PREGION1WA_W<'_>
[src]Bit 26 - Write ‘1’ to Enable non-maskable interrupt for PREGION[1].WA event
pub fn pregion1ra(&mut self) -> PREGION1RA_W<'_>
[src]
pub fn pregion1ra(&mut self) -> PREGION1RA_W<'_>
[src]Bit 27 - Write ‘1’ to Enable non-maskable interrupt for PREGION[1].RA event
impl W<u32, Reg<u32, _NMIENCLR>>
[src]
impl W<u32, Reg<u32, _NMIENCLR>>
[src]pub fn region0wa(&mut self) -> REGION0WA_W<'_>
[src]
pub fn region0wa(&mut self) -> REGION0WA_W<'_>
[src]Bit 0 - Write ‘1’ to Disable non-maskable interrupt for REGION[0].WA event
pub fn region0ra(&mut self) -> REGION0RA_W<'_>
[src]
pub fn region0ra(&mut self) -> REGION0RA_W<'_>
[src]Bit 1 - Write ‘1’ to Disable non-maskable interrupt for REGION[0].RA event
pub fn region1wa(&mut self) -> REGION1WA_W<'_>
[src]
pub fn region1wa(&mut self) -> REGION1WA_W<'_>
[src]Bit 2 - Write ‘1’ to Disable non-maskable interrupt for REGION[1].WA event
pub fn region1ra(&mut self) -> REGION1RA_W<'_>
[src]
pub fn region1ra(&mut self) -> REGION1RA_W<'_>
[src]Bit 3 - Write ‘1’ to Disable non-maskable interrupt for REGION[1].RA event
pub fn region2wa(&mut self) -> REGION2WA_W<'_>
[src]
pub fn region2wa(&mut self) -> REGION2WA_W<'_>
[src]Bit 4 - Write ‘1’ to Disable non-maskable interrupt for REGION[2].WA event
pub fn region2ra(&mut self) -> REGION2RA_W<'_>
[src]
pub fn region2ra(&mut self) -> REGION2RA_W<'_>
[src]Bit 5 - Write ‘1’ to Disable non-maskable interrupt for REGION[2].RA event
pub fn region3wa(&mut self) -> REGION3WA_W<'_>
[src]
pub fn region3wa(&mut self) -> REGION3WA_W<'_>
[src]Bit 6 - Write ‘1’ to Disable non-maskable interrupt for REGION[3].WA event
pub fn region3ra(&mut self) -> REGION3RA_W<'_>
[src]
pub fn region3ra(&mut self) -> REGION3RA_W<'_>
[src]Bit 7 - Write ‘1’ to Disable non-maskable interrupt for REGION[3].RA event
pub fn pregion0wa(&mut self) -> PREGION0WA_W<'_>
[src]
pub fn pregion0wa(&mut self) -> PREGION0WA_W<'_>
[src]Bit 24 - Write ‘1’ to Disable non-maskable interrupt for PREGION[0].WA event
pub fn pregion0ra(&mut self) -> PREGION0RA_W<'_>
[src]
pub fn pregion0ra(&mut self) -> PREGION0RA_W<'_>
[src]Bit 25 - Write ‘1’ to Disable non-maskable interrupt for PREGION[0].RA event
pub fn pregion1wa(&mut self) -> PREGION1WA_W<'_>
[src]
pub fn pregion1wa(&mut self) -> PREGION1WA_W<'_>
[src]Bit 26 - Write ‘1’ to Disable non-maskable interrupt for PREGION[1].WA event
pub fn pregion1ra(&mut self) -> PREGION1RA_W<'_>
[src]
pub fn pregion1ra(&mut self) -> PREGION1RA_W<'_>
[src]Bit 27 - Write ‘1’ to Disable non-maskable interrupt for PREGION[1].RA event
impl W<u32, Reg<u32, _REGIONEN>>
[src]
impl W<u32, Reg<u32, _REGIONEN>>
[src]pub fn prgn0wa(&mut self) -> PRGN0WA_W<'_>
[src]
pub fn prgn0wa(&mut self) -> PRGN0WA_W<'_>
[src]Bit 24 - Enable/disable write access watch in PREGION[0]
pub fn prgn0ra(&mut self) -> PRGN0RA_W<'_>
[src]
pub fn prgn0ra(&mut self) -> PRGN0RA_W<'_>
[src]Bit 25 - Enable/disable read access watch in PREGION[0]
impl W<u32, Reg<u32, _CHANNELS>>
[src]
impl W<u32, Reg<u32, _CHANNELS>>
[src]pub fn channels(&mut self) -> CHANNELS_W<'_>
[src]
pub fn channels(&mut self) -> CHANNELS_W<'_>
[src]Bits 0:1 - Enable channels.
impl W<u32, Reg<u32, _INTEN>>
[src]
impl W<u32, Reg<u32, _INTEN>>
[src]pub fn rxptrupd(&mut self) -> RXPTRUPD_W<'_>
[src]
pub fn rxptrupd(&mut self) -> RXPTRUPD_W<'_>
[src]Bit 1 - Enable or disable interrupt for RXPTRUPD event
pub fn stopped(&mut self) -> STOPPED_W<'_>
[src]
pub fn stopped(&mut self) -> STOPPED_W<'_>
[src]Bit 2 - Enable or disable interrupt for STOPPED event
pub fn txptrupd(&mut self) -> TXPTRUPD_W<'_>
[src]
pub fn txptrupd(&mut self) -> TXPTRUPD_W<'_>
[src]Bit 5 - Enable or disable interrupt for TXPTRUPD event
impl W<u32, Reg<u32, _INTENSET>>
[src]
impl W<u32, Reg<u32, _INTENSET>>
[src]pub fn rxptrupd(&mut self) -> RXPTRUPD_W<'_>
[src]
pub fn rxptrupd(&mut self) -> RXPTRUPD_W<'_>
[src]Bit 1 - Write ‘1’ to Enable interrupt for RXPTRUPD event
pub fn stopped(&mut self) -> STOPPED_W<'_>
[src]
pub fn stopped(&mut self) -> STOPPED_W<'_>
[src]Bit 2 - Write ‘1’ to Enable interrupt for STOPPED event
pub fn txptrupd(&mut self) -> TXPTRUPD_W<'_>
[src]
pub fn txptrupd(&mut self) -> TXPTRUPD_W<'_>
[src]Bit 5 - Write ‘1’ to Enable interrupt for TXPTRUPD event
impl W<u32, Reg<u32, _INTENCLR>>
[src]
impl W<u32, Reg<u32, _INTENCLR>>
[src]pub fn rxptrupd(&mut self) -> RXPTRUPD_W<'_>
[src]
pub fn rxptrupd(&mut self) -> RXPTRUPD_W<'_>
[src]Bit 1 - Write ‘1’ to Disable interrupt for RXPTRUPD event
pub fn stopped(&mut self) -> STOPPED_W<'_>
[src]
pub fn stopped(&mut self) -> STOPPED_W<'_>
[src]Bit 2 - Write ‘1’ to Disable interrupt for STOPPED event
pub fn txptrupd(&mut self) -> TXPTRUPD_W<'_>
[src]
pub fn txptrupd(&mut self) -> TXPTRUPD_W<'_>
[src]Bit 5 - Write ‘1’ to Disable interrupt for TXPTRUPD event
impl W<u32, Reg<u32, _LATCH>>
[src]
impl W<u32, Reg<u32, _LATCH>>
[src]pub fn pin0(&mut self) -> PIN0_W<'_>
[src]
pub fn pin0(&mut self) -> PIN0_W<'_>
[src]Bit 0 - Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write ‘1’ to clear.
pub fn pin1(&mut self) -> PIN1_W<'_>
[src]
pub fn pin1(&mut self) -> PIN1_W<'_>
[src]Bit 1 - Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write ‘1’ to clear.
pub fn pin2(&mut self) -> PIN2_W<'_>
[src]
pub fn pin2(&mut self) -> PIN2_W<'_>
[src]Bit 2 - Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write ‘1’ to clear.
pub fn pin3(&mut self) -> PIN3_W<'_>
[src]
pub fn pin3(&mut self) -> PIN3_W<'_>
[src]Bit 3 - Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write ‘1’ to clear.
pub fn pin4(&mut self) -> PIN4_W<'_>
[src]
pub fn pin4(&mut self) -> PIN4_W<'_>
[src]Bit 4 - Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write ‘1’ to clear.
pub fn pin5(&mut self) -> PIN5_W<'_>
[src]
pub fn pin5(&mut self) -> PIN5_W<'_>
[src]Bit 5 - Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write ‘1’ to clear.
pub fn pin6(&mut self) -> PIN6_W<'_>
[src]
pub fn pin6(&mut self) -> PIN6_W<'_>
[src]Bit 6 - Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write ‘1’ to clear.
pub fn pin7(&mut self) -> PIN7_W<'_>
[src]
pub fn pin7(&mut self) -> PIN7_W<'_>
[src]Bit 7 - Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write ‘1’ to clear.
pub fn pin8(&mut self) -> PIN8_W<'_>
[src]
pub fn pin8(&mut self) -> PIN8_W<'_>
[src]Bit 8 - Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write ‘1’ to clear.
pub fn pin9(&mut self) -> PIN9_W<'_>
[src]
pub fn pin9(&mut self) -> PIN9_W<'_>
[src]Bit 9 - Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write ‘1’ to clear.
pub fn pin10(&mut self) -> PIN10_W<'_>
[src]
pub fn pin10(&mut self) -> PIN10_W<'_>
[src]Bit 10 - Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write ‘1’ to clear.
pub fn pin11(&mut self) -> PIN11_W<'_>
[src]
pub fn pin11(&mut self) -> PIN11_W<'_>
[src]Bit 11 - Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write ‘1’ to clear.
pub fn pin12(&mut self) -> PIN12_W<'_>
[src]
pub fn pin12(&mut self) -> PIN12_W<'_>
[src]Bit 12 - Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write ‘1’ to clear.
pub fn pin13(&mut self) -> PIN13_W<'_>
[src]
pub fn pin13(&mut self) -> PIN13_W<'_>
[src]Bit 13 - Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write ‘1’ to clear.
pub fn pin14(&mut self) -> PIN14_W<'_>
[src]
pub fn pin14(&mut self) -> PIN14_W<'_>
[src]Bit 14 - Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write ‘1’ to clear.
pub fn pin15(&mut self) -> PIN15_W<'_>
[src]
pub fn pin15(&mut self) -> PIN15_W<'_>
[src]Bit 15 - Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write ‘1’ to clear.
pub fn pin16(&mut self) -> PIN16_W<'_>
[src]
pub fn pin16(&mut self) -> PIN16_W<'_>
[src]Bit 16 - Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write ‘1’ to clear.
pub fn pin17(&mut self) -> PIN17_W<'_>
[src]
pub fn pin17(&mut self) -> PIN17_W<'_>
[src]Bit 17 - Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write ‘1’ to clear.
pub fn pin18(&mut self) -> PIN18_W<'_>
[src]
pub fn pin18(&mut self) -> PIN18_W<'_>
[src]Bit 18 - Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write ‘1’ to clear.
pub fn pin19(&mut self) -> PIN19_W<'_>
[src]
pub fn pin19(&mut self) -> PIN19_W<'_>
[src]Bit 19 - Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write ‘1’ to clear.
pub fn pin20(&mut self) -> PIN20_W<'_>
[src]
pub fn pin20(&mut self) -> PIN20_W<'_>
[src]Bit 20 - Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write ‘1’ to clear.
pub fn pin21(&mut self) -> PIN21_W<'_>
[src]
pub fn pin21(&mut self) -> PIN21_W<'_>
[src]Bit 21 - Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write ‘1’ to clear.
pub fn pin22(&mut self) -> PIN22_W<'_>
[src]
pub fn pin22(&mut self) -> PIN22_W<'_>
[src]Bit 22 - Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write ‘1’ to clear.
pub fn pin23(&mut self) -> PIN23_W<'_>
[src]
pub fn pin23(&mut self) -> PIN23_W<'_>
[src]Bit 23 - Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write ‘1’ to clear.
pub fn pin24(&mut self) -> PIN24_W<'_>
[src]
pub fn pin24(&mut self) -> PIN24_W<'_>
[src]Bit 24 - Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write ‘1’ to clear.
pub fn pin25(&mut self) -> PIN25_W<'_>
[src]
pub fn pin25(&mut self) -> PIN25_W<'_>
[src]Bit 25 - Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write ‘1’ to clear.
pub fn pin26(&mut self) -> PIN26_W<'_>
[src]
pub fn pin26(&mut self) -> PIN26_W<'_>
[src]Bit 26 - Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write ‘1’ to clear.
pub fn pin27(&mut self) -> PIN27_W<'_>
[src]
pub fn pin27(&mut self) -> PIN27_W<'_>
[src]Bit 27 - Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write ‘1’ to clear.
pub fn pin28(&mut self) -> PIN28_W<'_>
[src]
pub fn pin28(&mut self) -> PIN28_W<'_>
[src]Bit 28 - Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write ‘1’ to clear.
pub fn pin29(&mut self) -> PIN29_W<'_>
[src]
pub fn pin29(&mut self) -> PIN29_W<'_>
[src]Bit 29 - Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write ‘1’ to clear.
impl W<u32, Reg<u32, _DETECTMODE>>
[src]
impl W<u32, Reg<u32, _DETECTMODE>>
[src]pub fn detectmode(&mut self) -> DETECTMODE_W<'_>
[src]
pub fn detectmode(&mut self) -> DETECTMODE_W<'_>
[src]Bit 0 - Select between default DETECT signal behaviour and LDETECT mode
impl W<u32, Reg<u32, _PIN_CNF>>
[src]
impl W<u32, Reg<u32, _PIN_CNF>>
[src]Auto Trait Implementations
impl<U, REG> Send for W<U, REG> where
REG: Send,
U: Send,
REG: Send,
U: Send,
impl<U, REG> Sync for W<U, REG> where
REG: Sync,
U: Sync,
REG: Sync,
U: Sync,
impl<U, REG> Unpin for W<U, REG> where
REG: Unpin,
U: Unpin,
REG: Unpin,
U: Unpin,
Blanket Implementations
impl<T> BorrowMut<T> for T where
T: ?Sized,
[src]
impl<T> BorrowMut<T> for T where
T: ?Sized,
[src]pub fn borrow_mut(&mut self) -> &mut T
[src]
pub fn borrow_mut(&mut self) -> &mut T
[src]Mutably borrows from an owned value. Read more
impl<T> CheckedAs for T
[src]
impl<T> CheckedAs for T
[src]pub fn checked_as<Dst>(self) -> Option<Dst> where
T: CheckedCast<Dst>,
[src]
pub fn checked_as<Dst>(self) -> Option<Dst> where
T: CheckedCast<Dst>,
[src]Casts the value.
impl<Src, Dst> LosslessTryInto<Dst> for Src where
Dst: LosslessTryFrom<Src>,
[src]
impl<Src, Dst> LosslessTryInto<Dst> for Src where
Dst: LosslessTryFrom<Src>,
[src]pub fn lossless_try_into(self) -> Option<Dst>
[src]
pub fn lossless_try_into(self) -> Option<Dst>
[src]Performs the conversion.
impl<Src, Dst> LossyInto<Dst> for Src where
Dst: LossyFrom<Src>,
[src]
impl<Src, Dst> LossyInto<Dst> for Src where
Dst: LossyFrom<Src>,
[src]pub fn lossy_into(self) -> Dst
[src]
pub fn lossy_into(self) -> Dst
[src]Performs the conversion.
impl<T> OverflowingAs for T
[src]
impl<T> OverflowingAs for T
[src]pub fn overflowing_as<Dst>(self) -> (Dst, bool) where
T: OverflowingCast<Dst>,
[src]
pub fn overflowing_as<Dst>(self) -> (Dst, bool) where
T: OverflowingCast<Dst>,
[src]Casts the value.
impl<T> Same<T> for T
impl<T> Same<T> for T
type Output = T
type Output = T
Should always be Self
impl<T> SaturatingAs for T
[src]
impl<T> SaturatingAs for T
[src]pub fn saturating_as<Dst>(self) -> Dst where
T: SaturatingCast<Dst>,
[src]
pub fn saturating_as<Dst>(self) -> Dst where
T: SaturatingCast<Dst>,
[src]Casts the value.
impl<T> UnwrappedAs for T
[src]
impl<T> UnwrappedAs for T
[src]pub fn unwrapped_as<Dst>(self) -> Dst where
T: UnwrappedCast<Dst>,
[src]
pub fn unwrapped_as<Dst>(self) -> Dst where
T: UnwrappedCast<Dst>,
[src]Casts the value.
impl<T> WrappingAs for T
[src]
impl<T> WrappingAs for T
[src]pub fn wrapping_as<Dst>(self) -> Dst where
T: WrappingCast<Dst>,
[src]
pub fn wrapping_as<Dst>(self) -> Dst where
T: WrappingCast<Dst>,
[src]Casts the value.