Struct nrf52811_pac::ppi::chenset::W [−][src]
pub struct W(_);
Expand description
Register CHENSET
writer
Implementations
Bit 0 - Channel 0 enable set register. Writing ‘0’ has no effect
Bit 1 - Channel 1 enable set register. Writing ‘0’ has no effect
Bit 2 - Channel 2 enable set register. Writing ‘0’ has no effect
Bit 3 - Channel 3 enable set register. Writing ‘0’ has no effect
Bit 4 - Channel 4 enable set register. Writing ‘0’ has no effect
Bit 5 - Channel 5 enable set register. Writing ‘0’ has no effect
Bit 6 - Channel 6 enable set register. Writing ‘0’ has no effect
Bit 7 - Channel 7 enable set register. Writing ‘0’ has no effect
Bit 8 - Channel 8 enable set register. Writing ‘0’ has no effect
Bit 9 - Channel 9 enable set register. Writing ‘0’ has no effect
Bit 10 - Channel 10 enable set register. Writing ‘0’ has no effect
Bit 11 - Channel 11 enable set register. Writing ‘0’ has no effect
Bit 12 - Channel 12 enable set register. Writing ‘0’ has no effect
Bit 13 - Channel 13 enable set register. Writing ‘0’ has no effect
Bit 14 - Channel 14 enable set register. Writing ‘0’ has no effect
Bit 15 - Channel 15 enable set register. Writing ‘0’ has no effect
Bit 16 - Channel 16 enable set register. Writing ‘0’ has no effect
Bit 17 - Channel 17 enable set register. Writing ‘0’ has no effect
Bit 18 - Channel 18 enable set register. Writing ‘0’ has no effect
Bit 19 - Channel 19 enable set register. Writing ‘0’ has no effect
Bit 20 - Channel 20 enable set register. Writing ‘0’ has no effect
Bit 21 - Channel 21 enable set register. Writing ‘0’ has no effect
Bit 22 - Channel 22 enable set register. Writing ‘0’ has no effect
Bit 23 - Channel 23 enable set register. Writing ‘0’ has no effect
Bit 24 - Channel 24 enable set register. Writing ‘0’ has no effect
Bit 25 - Channel 25 enable set register. Writing ‘0’ has no effect
Bit 26 - Channel 26 enable set register. Writing ‘0’ has no effect
Bit 27 - Channel 27 enable set register. Writing ‘0’ has no effect
Bit 28 - Channel 28 enable set register. Writing ‘0’ has no effect
Bit 29 - Channel 29 enable set register. Writing ‘0’ has no effect
Bit 30 - Channel 30 enable set register. Writing ‘0’ has no effect
Bit 31 - Channel 31 enable set register. Writing ‘0’ has no effect
Methods from Deref<Target = W<CHENSET_SPEC>>
Trait Implementations
Performs the conversion.