Enum PortType 

pub enum PortType {
    U64,
    F64,
    U32,
    I32,
    I64,
    F32,
    U8,
    I8,
    U16,
    I16,
    F16,
    U128,
    I128,
    Reg128,
    RegI8x16,
    RegI16x8,
    RegI32x4,
    RegI64x2,
    RegF16x8,
    RegF32x4,
    RegF64x2,
    Bool,
    Str,
    Bytes,
    Json,
    Ext,
    Handle,
    VecF32,
    VecI32,
    VecF64,
    VecI64,
    VecF16,
    VecI16,
    VecI8,
    Dyn,
}

Compile-time type tag for a port on a Polydat node.

Narrow types and runtime storage:

PortType includes narrow integer and float variants (U8/U16/U32, I8/I16/I32, F16/F32) that have no Value of their own. At runtime, narrow values are stored in the wide Value of their kind, with the assumption that the bits fit:

• unsigned (u8, u16, u32) → zero-extended in Value::U64
• signed (i8, i16, i32) → sign-extended in Value::I64
• f32 → losslessly widened in Value::F64 (f16 rides Value::U64 as its bit pattern; see PortType::F16)

The narrow PortType variants exist for compile-time type checking and auto-adapter insertion (U32ToU64, F32ToF64). P2/P3 compiled kernels use flat u64 buffers where this packing is natural. The Value enum stays small — no combinatorial explosion of narrow variant types.

Every input and output port declares its PortType. The assembler uses these to validate wiring and auto-insert type adapters (e.g., u64 → f64 widening). At runtime, the corresponding Value variant is used.

Widening rules (auto-inserted by the assembler):

• U32 → U64, I32 → I64, F32 → F64 (lossless widening)
• U64 → F64 (lossless for values < 2^53)
• Bool → U64 (true=1, false=0)
• Any type → Str (via display conversion)

Narrowing is never implicit — use explicit cast functions.

Exhaustive on purpose. The language grows a type now and then, and a match over every variant is then a compile error until it decides what the new type means. Polydat’s own code relies on that, and so should a host’s code that behaves differently per type. A host that only names or classifies types should not match at all: use Self::to_keyword or Display for a label, Self::from_keyword to parse one, and Self::numeric_domain or polydat’s SlotShape queries to classify, none of which breaks when a type is added.

Variants

U64

64-bit unsigned integer. The primary numeric type.

F64

64-bit IEEE 754 float. Used for math, distributions, noise.

U32

32-bit unsigned integer. Widens to U64 automatically.

I32

32-bit signed integer. Widens to I64 automatically.

I64

64-bit signed integer.

F32

32-bit IEEE 754 float. Widens to F64 automatically.

U8

8-bit unsigned integer (cranelift I8 lane, unsigned interpretation). Zero-extended in Value::U64; widens to U64 automatically.

I8

8-bit signed integer (cranelift I8 lane, signed interpretation). Sign-extended in Value::I64; widens to I64 automatically.

U16

16-bit unsigned integer (cranelift I16 lane, unsigned interpretation). Zero-extended in Value::U64; widens to U64 automatically.

I16

16-bit signed integer (cranelift I16 lane, signed interpretation). Sign-extended in Value::I64; widens to I64 automatically.

F16

16-bit IEEE 754-2008 binary16 float (cranelift F16). Carried as its bit pattern in Value::U64 (low 16 bits), the same stuffing convention as F32; widens to F32/F64 automatically (every f16 is exactly representable in both).

U128

128-bit unsigned integer (cranelift I128, unsigned interpretation). Real Value::U128 two-limb carrier — a 128-bit value cannot ride a 64-bit slot. Rides two consecutive u64 slots (a limb pair) on the compiled engines.

I128

128-bit signed integer (cranelift I128, signed interpretation). Same carrier story as U128.

Reg128

128-bit SIMD register word, raw view — the full word as algorithm-defined buffer state (heterogeneous lane roles). Free bitcast to/from every lane-typed view.

RegI8x16

Register word viewed as 16 × i8 lanes.

RegI16x8

Register word viewed as 8 × i16 lanes.

RegI32x4

Register word viewed as 4 × i32 lanes.

RegI64x2

Register word viewed as 2 × i64 lanes.

RegF16x8

Register word viewed as 8 × f16 lanes.

RegF32x4

Register word viewed as 4 × f32 lanes.

RegF64x2

Register word viewed as 2 × f64 lanes.

Bool

Boolean (true/false). Widens to U64 (1/0).

Str

Heap-allocated string. Any type auto-converts to Str.

Bytes

Raw byte buffer.

Json

Structured JSON value.

Ext

Adapter-contributed reflected type (e.g., CQL UUID).

Handle

Type-erased Arc handle to a resolved resource (dataset, prepared statement, …). The producer node populates an Arc<dyn Any + Send + Sync>; the consumer node downcasts to the concrete type via Value::as_handle::<T>().

VecF32

Typed f32 vector slice (Arc<[f32]>). Bound natively by adapters that understand [f32] (CQL vector<float, N>).

VecI32

Typed i32 vector slice (Arc<[i32]>).

VecF64

Typed f64 vector slice (Arc<[f64]>). Bound natively for CQL vector<double, N>.

VecI64

Typed i64 vector slice (Arc<[i64]>). Bound natively for CQL vector<bigint, N>.

VecF16

Typed half-precision float vector (Arc<[half::f16]>). Bound natively for CQL vector<half_float, N>-style columns; stays at f16 on the wire so embeddings stored as 16-bit floats don’t widen to f32 at the boundary.

VecI16

Typed i16 vector slice (Arc<[i16]>). Bound natively for CQL vector<smallint, N>.

VecI8

Typed i8 vector slice (Arc<[i8]>). Completes the cranelift lane family; CQL vector<tinyint, N>.

Dyn

Any value, as written: the slot of an input whose type may vary over a kernel’s lifetime (input_variance.md). Only a converter node reads it, turning the value into the type its consumers read; no other port has this type, and no value is typed Dyn.

Implementations

impl PortType

pub const ALL: &'static [PortType]

Every port type, once.

A test that must hold for all types can walk this rather than name the ones its author thought of, so a mapping such as the value↔slot writers is checked complete rather than complete for the types some program happened to use.

Self::every_variant_is_listed keeps this honest — it is an exhaustive match, so adding a variant without adding it here fails to compile rather than quietly shrinking every sweep that walks this list.

pub fn numeric_domain(self) -> Option<NumericDomain>

The numbers this type can carry, for the types that carry numbers. None for every other type.

This is what decides whether a conversion between two types keeps the value, so that the answer is read off the types themselves rather than kept in a list of pairs beside them.

pub fn to_keyword(&self) -> &'static str

The canonical lowercase keyword for this PortType.

This is the single source of truth for the str↔PortType mapping used by every synthesizer and parser in the workspace — synthesized polydat source (extern <name>: <keyword>), the workload-author {name:<keyword>} lvalue spec, and reverse parsing via Self::from_keyword. Inverse of Self::from_keyword.

Exhaustive over the enum — adding a new PortType variant is a compile error here, forcing the addition of its canonical keyword and the round-trip closure to update.

pub fn from_keyword(name: &str) -> Option<PortType>

Parse a polydat type keyword into a PortType.

Inverse of Self::to_keyword: accepts every keyword that to_keyword emits, plus a small set of legacy aliases ("String", "Json", "Ext") that survive in older hand-written workload source. Returns None for any unrecognized keyword so callers can surface a loud diagnostic rather than silently coercing to a default.

Used by the DSL extern <name>: <keyword> parser (polydat-core/src/dsl/compile.rs). Round-trips cleanly with any source to_keyword emits.

pub fn from_workload_name(name: &str) -> Option<PortType>

Workload-author-facing parser for the {name:<keyword>} lvalue-spec surface. Strict subset of Self::from_keyword — handle and ext are rejected because they’re internal-only types a workload author should never assert.

Returns None for any unrecognized name; the caller surfaces the unknown spec as a workload-shape diagnostic.

Trait Implementations

impl Clone for PortType

fn clone(&self) -> PortType

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Copy for PortType

impl Debug for PortType

fn fmt(&self, f: &mut Formatter<'_>) -> Result<(), Error>

Formats the value using the given formatter.

impl Display for PortType

fn fmt(&self, f: &mut Formatter<'_>) -> Result<(), Error>

Formats the value using the given formatter.

impl Eq for PortType

impl Hash for PortType

fn hash<__H>(&self, state: &mut __H)

where __H: Hasher,

Feeds this value into the given Hasher.

fn hash_slice<H>(data: &[Self], state: &mut H)

where H: Hasher, Self: Sized,

Feeds a slice of this type into the given Hasher.

impl PartialEq for PortType

fn eq(&self, other: &PortType) -> bool

Equality operator ==.

fn ne(&self, other: &Rhs) -> bool

Inequality operator !=.

impl SlotShape for PortType

fn slot_color(&self) -> SlotColor

Slot color in compiled (P2/P3/hybrid) kernel buffers — axiom S1 (jit_boundary.md §“Slot-state axioms”). The single chokepoint: width and every layout/codegen/guard decision derive from this, never restate it.

fn scratch_elem(&self) -> Option<ScratchElem>

The scratch element a Ref2-colored port’s producer owns (axiom S3); None for an immediate color.

fn slot_width(&self) -> usize

Buffer slots this type occupies — derived from Self::slot_color per axiom S1.

impl StructuralPartialEq for PortType