ni_fpga_interface::fifos

Trait Fifo

Source 
pub trait Fifo {
    // Required method
    fn address(&self) -> u32;

    // Provided methods
    fn start(&mut self, session: &Session) -> Result<(), FPGAError> { ... }
    fn stop(&mut self, session: &Session) -> Result<(), FPGAError> { ... }
    fn configure(
        &mut self,
        session: &Session,
        requested_depth: usize,
    ) -> Result<usize, FPGAError> { ... }
    fn get_peer_to_peer_fifo_endpoint(
        &self,
        session: &Session,
    ) -> Result<u32, FPGAError> { ... }
}
Expand description

The elements that are common between read and write FIFOs.

Required Methods§

Source

fn address(&self) -> u32

Provided Methods§

Source

fn start(&mut self, session: &Session) -> Result<(), FPGAError>

Begins DMA data transfer between the FPGA target and the host computer. This method is optional. This method is optional as the DMA is automatically started when you attempt to read or write.

You might want to use this method if:

  • you want to start data transfer with the DMA FIFO before you read the first element of the FIFO.
  • You have reconfigured the FIFO with Fifo::configure and you want to force the buffer size to be committed.


let session = Session::new("main.lvbitx", "sig", "RIO0").unwrap();
let mut fifo = ReadFifo::<u64>::new(1);
fifo.start(&session).unwrap();
Source

fn stop(&mut self, session: &Session) -> Result<(), FPGAError>

Stops the DMA data transfer between the FPGA target and the host computer. This method deletes all data from the host memory and FPGA parts of the FIFO.

This method is optional. Most applications do not require using the Stop method.



let session = Session::new("main.lvbitx", "sig", "RIO0").unwrap();
let mut fifo = ReadFifo::<u64>::new(1);
fifo.stop(&session).unwrap();
Source

fn configure( &mut self, session: &Session, requested_depth: usize, ) -> Result<usize, FPGAError>

Specifies the capacity, or depth, in elements of the host FIFO of the DMA channel. The new depth is implemented when the next FIFO Start, FIFO Read, or FIFO Write method executes. Before the new depth is set, the driver empties all data from the host memory and FPGA FIFO.

This method is optional as the buffer is set by default to 10000 elements or twice the size of the FPGA buffer size.

NI recommend this is set to 5 times the number of elements you specify to read and write.

This method returns the actual size configured which may be larger than the request.



let session = Session::new("main.lvbitx", "sig", "RIO0").unwrap();
let mut fifo = ReadFifo::<u64>::new(1);

let configured_depth = fifo.configure(&session, 10_000).unwrap();
// Start to apply the config.
fifo.start(&session).unwrap();
Source

fn get_peer_to_peer_fifo_endpoint( &self, session: &Session, ) -> Result<u32, FPGAError>

Implementors§