Type Definition muscab1_pac::system_control::SYSCLK_DIV

type SYSCLK_DIV = Reg<u32, _SYSCLK_DIV>;

System Clock Divider Configuration

This register you can read, reset, write, write_with_zero, modify. See API.

For information about avaliable fields see sysclk_div module

Trait Implementations

impl Readable for SYSCLK_DIV

read() method returns sysclk_div::R reader structure

impl Writable for SYSCLK_DIV

write(|w| ..) method takes sysclk_div::W writer structure

impl ResetValue for SYSCLK_DIV

Register SYSCLK_DIV reset()'s with value 0

type Type = u32

Register size

fn reset_value() -> Self::Type

Reset value of the register