[−][src]Module muscab1_pac::system_control
System Control
Modules
| cidr0 | Component ID 0 |
| cidr1 | Component ID 1 |
| cidr2 | Component ID 2 |
| cidr3 | Component ID 3 |
| clock_force | Clock Force |
| cpuwait | CPU Boot wait control after reset |
| ewctrl | External Wakeup Control |
| fclk_div | Fast Clock Divider Configuration |
| gretreg | General Purpose Retention |
| initsvrtor0 | Initial Secure Reset Vector Register For CPU 0 |
| initsvrtor1 | Initial Secure Reset Vector Register For CPU 1 |
| nmi_enable | NMI Enable Register |
| pdcm_pd_sram0_sense | Power Control Depedendency Matrix PD_SRAM0 Power Domain Sensitivity |
| pdcm_pd_sram1_sense | Power Control Depedendency Matrix PD_SRAM1 Power Domain Sensitivity |
| pdcm_pd_sram2_sense | Power Control Depedendency Matrix PD_SRAM2 Power Domain Sensitivity |
| pdcm_pd_sram3_sense | Power Control Depedendency Matrix PD_SRAM3 Power Domain Sensitivity |
| pdcm_pd_sys_sense | External Wakeup Control |
| pidr0 | Peripheral ID 0 |
| pidr1 | Peripheral ID 1 |
| pidr2 | Peripheral ID 2 |
| pidr3 | Peripheral ID 3 |
| pidr4 | Peripheral ID 4 |
| reset_mask | Reset Mask |
| reset_syndrome | Reset Syndrome |
| scsecctrl | System Security Control |
| secdbgclr | Secure Debug Configuration Clear |
| secdbgset | Secure Debug Configuration Set |
| secdbgstat | Secure Debug Configuration Status |
| swreset | Software Reset |
| sysclk_div | System Clock Divider Configuration |
| wicctrl | WIC request and acknowledge handshake |
Structs
| RegisterBlock | Register block |
Type Definitions
| CIDR0 | Component ID 0 |
| CIDR1 | Component ID 1 |
| CIDR2 | Component ID 2 |
| CIDR3 | Component ID 3 |
| CLOCK_FORCE | Clock Force |
| CPUWAIT | CPU Boot wait control after reset |
| EWCTRL | External Wakeup Control |
| FCLK_DIV | Fast Clock Divider Configuration |
| GRETREG | General Purpose Retention |
| INITSVRTOR0 | Initial Secure Reset Vector Register For CPU 0 |
| INITSVRTOR1 | Initial Secure Reset Vector Register For CPU 1 |
| NMI_ENABLE | NMI Enable Register |
| PDCM_PD_SRAM0_SENSE | Power Control Depedendency Matrix PD_SRAM0 Power Domain Sensitivity |
| PDCM_PD_SRAM1_SENSE | Power Control Depedendency Matrix PD_SRAM1 Power Domain Sensitivity |
| PDCM_PD_SRAM2_SENSE | Power Control Depedendency Matrix PD_SRAM2 Power Domain Sensitivity |
| PDCM_PD_SRAM3_SENSE | Power Control Depedendency Matrix PD_SRAM3 Power Domain Sensitivity |
| PDCM_PD_SYS_SENSE | External Wakeup Control |
| PIDR0 | Peripheral ID 0 |
| PIDR1 | Peripheral ID 1 |
| PIDR2 | Peripheral ID 2 |
| PIDR3 | Peripheral ID 3 |
| PIDR4 | Peripheral ID 4 |
| RESET_MASK | Reset Mask |
| RESET_SYNDROME | Reset Syndrome |
| SCSECCTRL | System Security Control |
| SECDBGCLR | Secure Debug Configuration Clear |
| SECDBGSET | Secure Debug Configuration Set |
| SECDBGSTAT | Secure Debug Configuration Status |
| SWRESET | Software Reset |
| SYSCLK_DIV | System Clock Divider Configuration |
| WICCTRL | WIC request and acknowledge handshake |