Type Definition muscab1_pac::system_control::FCLK_DIV

type FCLK_DIV = Reg<u32, _FCLK_DIV>;

Fast Clock Divider Configuration

This register you can read, reset, write, write_with_zero, modify. See API.

For information about avaliable fields see fclk_div module

Trait Implementations

impl Readable for FCLK_DIV

read() method returns fclk_div::R reader structure

impl Writable for FCLK_DIV

write(|w| ..) method takes fclk_div::W writer structure

impl ResetValue for FCLK_DIV

Register FCLK_DIV reset()'s with value 0

type Type = u32

Register size

fn reset_value() -> Self::Type

Reset value of the register