Type Alias R 

pub type R = R<CTL0_SPEC>;

Register CTL0 reader

Aliased Type

pub struct R { /* private fields */ }

Implementations

impl R

pub fn ctl0_enable(&self) -> CTL0_ENABLE_R

Bit 0 - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state.

pub fn ctl0_lbe(&self) -> CTL0_LBE_R

Bit 2 - UART Loop Back Enable

pub fn ctl0_rxe(&self) -> CTL0_RXE_R

Bit 3 - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set.

pub fn ctl0_txe(&self) -> CTL0_TXE_R

Bit 4 - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set.

pub fn ctl0_txd_out_en(&self) -> CTL0_TXD_OUT_EN_R

Bit 5 - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0

pub fn ctl0_txd_out(&self) -> CTL0_TXD_OUT_R

Bit 6 - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0.

pub fn ctl0_menc(&self) -> CTL0_MENC_R

Bit 7 - Manchester Encode enable

pub fn ctl0_mode(&self) -> CTL0_MODE_R

Bits 8:10 - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)

pub fn ctl0_rts(&self) -> CTL0_RTS_R

Bit 12 - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output.

pub fn ctl0_rtsen(&self) -> CTL0_RTSEN_R

Bit 13 - Enable hardware controlled Request to Send

pub fn ctl0_ctsen(&self) -> CTL0_CTSEN_R

Bit 14 - Enable Clear To Send

pub fn ctl0_hse(&self) -> CTL0_HSE_R

Bits 15:16 - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set).

pub fn ctl0_fen(&self) -> CTL0_FEN_R

Bit 17 - UART Enable FIFOs

pub fn ctl0_majvote(&self) -> CTL0_MAJVOTE_R

Bit 18 - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken.

pub fn ctl0_msbfirst(&self) -> CTL0_MSBFIRST_R

Bit 19 - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit.